KR20020069454A - Apparatus for loop back test in interface port - Google Patents

Abstract

PURPOSE: A device for testing a loopback of an interface port is provided to perform a loopback test by performing an open short of control signals to be looped back simply when a loopback of an interface port is tested in a communication system. CONSTITUTION: An internal loopback device(20) which is tri-state buffer(21) performs a control operation in accordance with a communication protocol supplied in a CPU or a controller, loops TXCLK, TXD, RTS, CD, RXCLK, RXD, CTS, and GND signals of the controller, and checks an operation status. An external loopback device(30) which is tri-state buffer(31) performs a loopback of TXCLK, TXD, RTS, CD, RXCLK, RXD, CTS, GND signals, and a control signal to DTXCLX, DTXD, DRTS, DCD, DRXCLK, DRXD, and DCTS control signals of a line driver which influences an external matching in accordance with a communication protocol supplied in the CPU or the controller, and checks an operation status of the line driver.

Description

Loopback test device for interface port {APPARATUS FOR LOOP BACK TEST IN INTERFACE PORT}

The present invention relates to a loopback test apparatus for an interface port. More specifically, the loopback test for testing the transmission / reception status of an interface port in an electronic and communication system can be conveniently and stably tested with a three-phase buffer (TRI-STATE BUFFER). To one loopback test device.

In general, a loopback test on each channel is required at a line interface port of an electronic or communication system. In this case, the apparatus for performing the loopback test is generally hardware-configured, as shown in FIG. 1.

The reason for this is that the implementation of the loopback test device is as simple and inexpensive as possible.

The hardware-configured loopback test apparatus includes a header in which the signal lines TXCLK, TXD, RTS, CD, RXCLK, RXD, CTS, and GND, which control interface ports, are disposed on the board or the back board of the communication device. The loopback test of the interface port is performed by inserting or removing the shunt into a header by configuring a shunt connecting the signal lines, respectively.

Therefore, during the loopback test, should the tester always remove the corresponding board from the device and insert a shunt, or do the boards other than the board stop working because power must be turned off when removing the board? In this case, since the shunt is used only for the loopback test, there is a risk of loss if the test is not performed.

In addition, since the length of the pins of the control lines of the header is longer than the height of other components, each pin is bent due to carelessness during transportation or movement, thereby failing to perform an operation required for the actual test.

Accordingly, an object of the present invention is to enable a loopback test while simply opening and shorting control signals to be looped back when performing an interface port loopback test in an electronic or communication system.

In order to realize the above object, according to the present invention, an input is output as it is or according to a control signal applied by a predetermined program from the inside or the outside to an interface port of an electronic or communication system, or any signal is output by maintaining a high impedance state. It is characterized in that the three-phase buffer that is not configured to loop back and test the transmission and reception data.

1 is a block diagram of a loopback test apparatus of a conventional interface port

Figure 2 is a block diagram of a loopback test apparatus of the present invention interface port

3 is a circuit diagram of a loopback test apparatus of an interface port of the present invention;

* Explanation of symbols for the main parts of the drawings *

CONTROLLER; Controller LINE DRIVER; Line driver

20; Internal loopback device 21; 3 phase buffer

30; External loopback device 31; 3 phase buffer

INV1, INV2; Inverter BUF1-BUF3; buffer

Hereinafter, described in detail with reference to the accompanying drawings, preferred embodiments of the present invention.

2 is a block diagram of a loopback test apparatus of an interface port of the present invention, and FIG. 3 is a circuit diagram of a loopback test apparatus of an interface port of the present invention, and is controlled according to a communication protocol provided by a CPU or a controller. An internal loopback device (20) which is a three-phase buffer (21) which loops through the TXCLK, TXD, RTS, CD, RXCLK, RXD, CTS, and GND signals of the controller and checks the operation state; A line driver that affects external matching of TXCLK, TXD, RTS, CD, RXCLK, RXD, CTS, GND signals and control signals according to the communication protocol provided by the CPU or controller. The loopback of the DTXCLK, DTXD, DRTS, DCD, DRXCLK, DRXD, and DCTS control signals is used to separate the external loopback device 30, which is a three-phase buffer 31 that checks the operation status of the line driver. .

An inverter INV1 for controlling a control signal CONTROL1 for selectively activating and deactivating the inner loopback device 20 and the outer loopback device 30; The external loopback device 30 includes an inverter INV2 for inverting a control signal CONTROL2 for selecting whether to use an internal transmission clock DITXCLK or an externally input transmission clock DOTXCLK, and the internal or external inverter. The buffer BUF1, BUF2, and BUF3 buffer the transmission clock DOTXCLK.

According to the present invention configured as described above, the transmission data TXD, the request control signal RTS, and the transmission clock signal TXCLK of the controller in the interface board composed of a controller and a line driver. And a three-phase buffer 21 which is an internal loopback 20 to which ground CD and receive data RXD, release control signal CTS, receive clock signal RXCLK, and ground GND are connected. Driver transmission data (DTXD), driver request control signal (DRTS), driver transmission clock (DTXCLK), and driver ground (DCD) of the line driver that influence the control signal level and external matching through the controller. And a three-phase buffer 31 that is an external loopback 30 to which the driver reception data DRXD, the driver release control signal DCTS, the driver reception clock DRXCLK, and the driver ground GND are connected.

As such, when the internal loopback device 20 and the external loopback device 30 are mounted in the controller and the line driver, the control signal CONTROL1 is' '0' is applied to the output enable (OE1, OE2) of the three-phase buffer 21 to activate the three-phase buffer 21, while the '0' is Inverted '1' through the inverter INV1 to the three-phase buffer 31 of the external loopback device 30 is applied to the output enable terminals OE1 and OE2 so that the external loopback device 30 is deactivated. .

Therefore, only the inner loopback device 20 is activated, so that the transmit data TXD, the request control signal RTS, the transmit clock signal TXCLK, the ground CD and the receive data RXD, and release of the controller CONTROLLER are released. The control signal CTS, the receive clock signal RXCLK, and the ground GND are connected to each other.

Therefore, the transmission data TXD of the controller is received as the reception data RXD through the three-phase buffer 21, and in the controller CONTROLLER compares whether the received data is the same as the transmission data. The loopback is determined to be normal.

In this case, data transmission and reception is performed by an internal transmission clock signal TXCLK and a reception clock signal RXCLK. The request control signal RTS, which is the communication port control signal, informs the receiving end when transmission data TX is generated. Informs the data transmission, and in the release control signal (CTS) to notify the transmitting end when the receiving end is completed to send and receive data.

On the other hand, when the external loopback device 30 is to be tested, the control signal CONTROL1 is applied with '1', and the '1' signal is enabled for the output of the three-phase buffer 21 (OE1 and OE2). Is applied to deactivate the three-phase buffer 21, whereas the '1' is the output '0' inverted through the inverter INV1 to the three-phase buffer 31 of the external loopback device 30. The external loopback device 30 is activated by being applied to the enable terminals OE1 and OE2.

Therefore, only the external loopback device 30 is activated so that the transmission data TXD, the request control signal RTS, the transmission clock signal TXCLK, and the ground CD of the controller are connected to the line driver. Driver transmission data (DTXD), driver reception data (DRXD), driver transmission clock (DTXCLK), driver reception clock (DRXCLK), driver request control signal (DRTS), driver release control signal (DCTS), driver ground (DCD), Ground (GND) is connected to each other.

Accordingly, if the driver transmission data DTXD of the controller is equal to the transmission data by comparing the driver reception data RXD received through the three-phase buffer 31 with each other, it is determined that the loopback is normal.

At this time, the line driver data transmission and reception is performed by the internal transmission clock signal DITXCLK and the external transmission clock signal DOTXCLK.

Accordingly, the internal transmission clock signal DITXCLK is a clock provided from the CPU or the controller, and the external transmission clock signal DOTXCLK is from the CPU or the controller. This is achieved by a clock provided by an external oscillator.

Therefore, when the control signal CONTROL2 is 'O' during the loopback test of the line driver, the 'O' signal activates the buffers BUF2 and BUF3 while the buffer BUF1 is the inverter INV2. Since the inverted signal '1' is applied and inactivated, an external transmission clock signal DOTXCLK is applied to the three-phase buffer 31 and the external transmission clock signal DOTXCLK is connected to the driver reception clock DRXCLK. It will connect and test the loopback.

Meanwhile, when the control signal CONTROL2 is '1', the '1' signal is a buffer BUF2.

While the buffer BUF3 is inactivated, the buffer BUF1 is activated because the signal '0' inverted by the inverter INV2 is applied. The internal transmission clock signal DITXCLK is applied to the three-phase buffer 31, and the internal transmission clock signal DITXCLK is connected to the driver reception clock DRXCLK to test the loopback.

As described above, according to the present invention, the input is output as it is or according to a control signal applied by a preset program from the inside or the outside to the interface transmission / reception port of the electronic or communication system, or no signal is output by maintaining the high impedance state. By configuring a three-phase buffer that is not configured to loop back and test the transmitted / received data, a loopback test can be performed while the signals are easily open shorted by software instead of the loopback test by the hardware.

Claims (5)

A loopback test apparatus for loopback testing an interface port of an electronic or communication system, wherein the signal input to the interface port is output as it is or a high-impedance state is configured to configure a three-phase buffer in which no signal is output. Loopback tester on the interface port. The apparatus of claim 1, wherein the three-phase buffer comprises: an inner loop back device for looping back transmission data of a controller; A loopback test device for an interface port, characterized in that the transmission data from the controller is separated into an external loopback device that loops back the driver transmission data output through the line driver. The apparatus of claim 2, wherein the inner loopback device and the outer loopback device are configured to be selectively activated by a control signal. 4. The loopback test apparatus of claim 3, wherein the selective activation of the inner loopback device and the outer loopback device is configured to be invertedly driven by an inverter. 3. The loopback test apparatus of claim 2, wherein the external loopback device is configured such that transmission data is selectively looped back by an internal clock signal and an external clock signal.