KR20020068801A - A MOSFET and a method for manufacturing the same - Google Patents
A MOSFET and a method for manufacturing the same Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 230000005669 field effect Effects 0.000 claims abstract description 28
- 239000000463 material Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 6
- 229920005591 polysilicon Polymers 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract 4
- 238000005468 ion implantation Methods 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 22
- 230000004888 barrier function Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Abstract
Description
본 발명은 전계효과 트랜지스터와 그 제조방법, 보다 상세하게는 전계효과에 의해 여기된 전자층을 소스/드레인 영역으로 이용하도록 절연막 측벽공정을 이용한 새로운 구조의 실리콘 전계효과 트랜지스터와 그 제조방법에 관한 것이다.The present invention relates to a field effect transistor, a method for manufacturing the same, and more particularly, to a silicon field effect transistor having a novel structure using an insulating film sidewall process so as to use an electron layer excited by the field effect as a source / drain region. .
종래의 실리콘 전계효과 트랜지스터(Si MOSFET)는 불순물의 이온주입(implantation)에 의해 소스/드레인(source/drain) 영역을 형성했다. 그러나, 소자의 크기가 스케일다운(scale-down)되어 게이트 크기가 수 10 나노미터(nm)인 극 미세 소자를 구현하려 할 경우에는 이론적으로 수 나노미터 이하의 접합 깊이가 필요하게 되어 이온주입을 이용한 소스/드레인 형성 방법은 소자의 정상적인 동작에 한계점을 가지게 된다. 이온 주입을 이용하여 10 나노미터 이하의 소스/드레인을 형성하는 것이 어렵기 때문이다. 소자의 게이트 길이에 비하여 소스/드레인 접합의 깊이가 충분히 얕지 않을 경우에 소자의 문턱전압이 감소하는 동시에 DIBL(drain induced barrier lowering)이 증가하여 바이어스 조건에 따라 불안정한 소자 동작특성을 보이게 된다(단채널 현상 : short channel effect). 이러한 문제점을 개선하기 위하여 초미세 전계효과 트랜지스터의 소스/드레인 영역을 이온주입 방법으로 형성하는 것이 아니라 전계효과를 이용하여 얇은 전자층을 여기시켜서 이것을 소스/드레인 영역으로 이용하는 연구가 진행되고 있다(특허출원 제1999-9442호 참조). 실제로 전계에 의해 형성되는 전자층은 수 나노미터의 아주 얕은 깊이를 가지므로 이온주입을 통한 접합과는 비교할 수 없을 만큼 얕은 LDD(lightly doped drain) 영역을 구현할 수 있게 된다. 이러한 얕은 접합을 이용하면 나노-스테일(nano-scale)의 초미세 소자에서의 단채널 현상을 극복한 안정적인 동작특성을 확보할 수 있다.Conventional silicon field effect transistors (Si MOSFETs) form source / drain regions by ion implantation of impurities. However, if the size of the device is scaled down to realize an ultra-fine device with a gate size of several ten nanometers (nm), a theoretical junction depth of several nanometers or less is required. The source / drain formation method used has a limitation in the normal operation of the device. This is because it is difficult to form a source / drain of 10 nanometers or less using ion implantation. If the source / drain junction depth is not sufficiently shallow compared to the gate length of the device, the threshold voltage of the device decreases and the drain induced barrier lowering (DIBL) increases, resulting in unstable device operation characteristics according to the bias conditions (short channel). Phenomenon: short channel effect). In order to improve this problem, studies are being conducted to excite a thin electron layer using a field effect and use it as a source / drain region instead of forming a source / drain region of an ultrafine field effect transistor by an ion implantation method (patent) See application 1999-9442). In fact, the electron layer formed by the electric field has a very shallow depth of several nanometers, thereby enabling a lightly doped drain (LDD) region that is incomparably shallow compared to the junction through ion implantation. By using such a shallow junction, it is possible to secure stable operation characteristics that overcome the short channel phenomenon in nano-scale ultrafine devices.
본 발명은 전계효과를 이용하여 얇은 전자층을 여기시켜서 이것을 소스/드레인 영역으로 이용할 수 있는 새로운 구조의 전계효과 트랜지스터를 제공하는 것을 목적으로 한다.An object of the present invention is to provide a field effect transistor having a novel structure in which a thin electron layer can be excited using a field effect and used as a source / drain region.
본 발명은 또한 절연막 측벽 공정을 이용한 미세구조의 전계효과 트랜지스터를 제공하는 것을 목적으로 한다.It is another object of the present invention to provide a microstructured field effect transistor using an insulating film sidewall process.
위와 같은 목적을 달성하기 위하여 본 발명은 이온주입으로 형성된 소스/드레인 확산층을 가지는 반도체 기판에 형성된 게이트 절연막 위에, 채널을 형성하도록 중앙에 형성된 메인 게이트와, 소스 드레인 확산층으로 전자를 여기하도록 메인게이트를 둘러싼, 한쌍의 사이드 게이트로 구성된 전계효과 트랜지스터와, 측벽에 의해 형성된 스페이서를 이용하여 위의 메인 게이트의 크기를 축소하는 전계효과 트랜지스터의 제조방법을 제공한다.In order to achieve the above object, the present invention provides a main gate formed at the center to form a channel and a main gate to excite electrons into the source drain diffusion layer on a gate insulating film formed on a semiconductor substrate having a source / drain diffusion layer formed by ion implantation. A field effect transistor comprising a pair of side gates surrounding and a spacer formed by sidewalls is provided to reduce the size of the main gate.
도 1은 본 발명의 실시예의 전계효과 트랜지스터의 단면도,1 is a cross-sectional view of a field effect transistor of an embodiment of the present invention;
도 2는 종래의 전계효과 트랜지스터의 하나의 예의 단면도,2 is a cross-sectional view of one example of a conventional field effect transistor;
도 3a ~ 도 3f는 본 발명의 실시예에 의한 전계효과 트랜지스터 제조공정을 보여주는 단면도,3A to 3F are cross-sectional views illustrating a field effect transistor manufacturing process according to an embodiment of the present invention;
도 4는 본 발명과 종래기술의 전계기술의 전계효과 트랜지스터의 문턱전압 특성을 나타낸 그래프,Figure 4 is a graph showing the threshold voltage characteristics of the field effect transistor of the field technology of the present invention and the prior art,
도 5는 본 발명과 종래기술의 전계효과 트랜지스터의 DIBL(drain induced barrier lowering)을 비교한 그래프이다.5 is a graph comparing drain induced barrier lowering (DIBL) of the field effect transistor of the present invention and the prior art.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
2 : 게이트 절연막 3 : 사이드 게이트2: gate insulating film 3: side gate
4 : 소스/드레인 접합 5', 6 : 측벽4 source / drain junction 5 ', 6 sidewall
7 : 메인 게이트7: main gate
이러한 본 발명은 전계에 의해 형성되는 전자층을 이용하여 LDD층을 구현함과 동시에 메인 게이트의 길이를 리소그래피의 한계보다 줄일 수 있다.The present invention can realize the LDD layer using the electronic layer formed by the electric field and at the same time reduce the length of the main gate than the limit of lithography.
이하 본 발명을 그 실시예에 의해 첨부도면을 참고로 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명의 실시예의 전계효과 트랜지스터의 구조를 보여주는 단면도로서, 이온주입으로 형성된 깊은 소스/드레인 접합(4)을 가지는 반도체 기판(1)과, 반도체 기판(1) 위에 형성된 게이트 절연막(2)과, 게이트 절연막(2) 위에 형성된한쌍의 사이드 게이트(3)와, 사이드 게이트(3)에 둘러싸인 메인 게이트(7)와, 메인 게이트(7)의 크기를 정의하는 산화막 측벽(6)과, 실리콘 산화막 측벽(6)을 형성하기 위한 실리콘 질화막(5)으로 구성된 전계효과 트랜지스터가 도시되어 있다.1 is a cross-sectional view showing a structure of a field effect transistor according to an embodiment of the present invention, in which a semiconductor substrate 1 having a deep source / drain junction 4 formed by ion implantation and a gate insulating film 2 formed on the semiconductor substrate 1 are shown in FIG. ), A pair of side gates 3 formed on the gate insulating film 2, a main gate 7 surrounded by the side gate 3, an oxide film sidewall 6 defining the size of the main gate 7, A field effect transistor composed of a silicon nitride film 5 for forming the silicon oxide film sidewall 6 is shown.
도 3e ~ 도 3f는 도 1의 전계효과 트랜지스터의 제조공정을 보여주는 단면도이다.3E to 3F are cross-sectional views illustrating a manufacturing process of the field effect transistor of FIG. 1.
본 발명에 있어서, 소자간의 분리는 공지의 LOCOS(local oxidation) 또는 STI(shallow trench isolation) 공정을 이용하며, 분리 공정후의 제조공정은 아래와 같이 진행된다.In the present invention, separation between devices uses a known local oxidation (LOCOS) or shallow trench isolation (STI) process, and the manufacturing process after the separation process proceeds as follows.
반도체 기판(1)에 산화막을 성장시켜 게이트 절연막(2)을 만들고 폴리 실리콘을 증착 및 도핑하여 사이드 게이트 물질층(3')을 형성한다( 도 3a).An oxide film is grown on the semiconductor substrate 1 to form a gate insulating film 2, and polysilicon is deposited and doped to form a side gate material layer 3 '(FIG. 3A).
사진 식각 공정을 이용하여 사이드 게이트 물질층(3')을 패터닝하고, 그 양단과 정렬된 위치의 반도체 기판(1)에 이온주입에 의해 소스/드레인 확산층(4)을 형성한다(도 3b).The side gate material layer 3 'is patterned using a photolithography process, and a source / drain diffusion layer 4 is formed by ion implantation into the semiconductor substrate 1 at a position aligned with both ends (FIG. 3B).
패터닝된 사이드 게이트 물질층(3') 위에 실리콘 질화막(5)을 증착하고 사진 식각 공정을 이용하여 측벽(5')과 함께 메인 게이트를 만들 부분을 형성한 후, 사이드 게이트 물질층(3')과 실리콘 질화막(5) 위에 실리콘 산화막층(6')을 형성한다(도 3c).After depositing a silicon nitride film 5 on the patterned side gate material layer 3 'and forming a portion to form the main gate together with the sidewall 5' using a photolithography process, the side gate material layer 3 ' And silicon oxide film layer 6 'is formed on silicon nitride film 5 (FIG. 3C).
실리콘 산화막층(6')을 이방성 식각하여 실리콘 산화막 측벽(6)을 실리콘 질화막(5) 사이에 형성하여 메인 게이트가 정의될 부분의 폭을 축소시킨다(도 3d).The silicon oxide layer 6 'is anisotropically etched to form the silicon oxide sidewall 6 between the silicon nitride layers 5 to reduce the width of the portion where the main gate is to be defined (FIG. 3D).
실리콘 산화막 측벽(6)을 마스크로 하여 사이드 게이트 물질층(3')을 식각하여 한쌍의 사이드 게이트(3)를 형성한다(도 3e).The side gate material layer 3 'is etched using the silicon oxide sidewall 6 as a mask to form a pair of side gates 3 (FIG. 3E).
노출된 사이드 게이트(3) 측면에 빗금부분과 같이 성장시키고, 폴리 실리콘 증착 및 도핑에 의해 메인 게이트(7)를 형성한다(도 3f).It grows like a hatched part on the exposed side gate 3 side, and forms the main gate 7 by polysilicon deposition and doping (FIG. 3F).
위와 같이 본 발명의 실시예의 전계효과 트랜지스터를 제조한 후 ILD(inter-layer dielectric)층을 형성하고 콘택트 작업 및 금속화 공정을 행한다.After manufacturing the field effect transistor of the embodiment of the present invention as described above to form an inter-layer dielectric (ILD) layer, and to perform the contact operation and metallization process.
위에서는 실리콘 산화막층(6')을 형성하고, 이를 식각하여 실리콘 산화막 측벽(6)을 형성하였으나, 이를 생략하고 실리콘 질화막(5)의 측벽(5')에 의해 메인 게이트(7)를 정의할 수도 있다.Although the silicon oxide layer 6 'is formed and etched to form the silicon oxide sidewall 6 above, the main gate 7 may be defined by the sidewall 5' of the silicon nitride layer 5. It may be.
본 발명의 위의 실시예의 전계효과 트랜지스터의 성능을 도 2의 종래의 LDD 구조의 MOSFET와 비교하여 실험한 결과를 도 4, 도 5에 나타내었다.4 and 5 show the results of an experiment comparing the performance of the field effect transistor of the above embodiment of the present invention with the MOSFET of the conventional LDD structure of FIG. 2.
본 발명의 n-채널 전계효과 트랜지스터는 p-형 반도체 기판(1)의 사이드 게이트(3)의 길이를 100nm, 깊은 소스/드레인 접합(4)의 이온주입 조건을 As 30keV, SE 15로 하였고, 메인 게이트(7)와 사이드 게이트(3)를 나누는 유전층, 즉 질화실리콘 측벽(5)의 두께는 50nm였다. p-형 반도체 기판(1)에 산화막(12)을 형성하여 만들어진 종래의 MOSFET는 측벽(16)의 폭이 100nm, LDD층(19)의 이온주입 조건은 AS 10keB, 1E 14, 깊은 소스/드레인(14)의 이온주입 조건은 본 발명의 전계효과 트랜지스터와 동일한 As 30keV, SE 15로 하였다.In the n-channel field effect transistor of the present invention, the length of the side gate 3 of the p-type semiconductor substrate 1 is 100 nm, and the ion implantation conditions of the deep source / drain junction 4 are As 30 keV and SE 15. The thickness of the dielectric layer dividing the main gate 7 and the side gate 3, ie, the silicon nitride sidewall 5, was 50 nm. In the conventional MOSFET formed by forming the oxide film 12 on the p-type semiconductor substrate 1, the width of the sidewall 16 is 100 nm, and the ion implantation conditions of the LDD layer 19 are AS 10 keB, 1E 14, and deep source / drain. The ion implantation conditions of (14) were set to As 30 keV and SE 15 which are the same as those of the field effect transistor of the present invention.
양자의 메인 게이트(7, 17)의 길이는 0.2 nm 에서 0.02 nm 까지 변경하여, MEDICI를 사용하여 특성을 실험하였다.The lengths of both main gates 7 and 17 were changed from 0.2 nm to 0.02 nm, and characteristics were tested using MEDICI.
도 4는 위의 실험을 통한 두 가지 소자의 문턱전압의 게이트 길이에 따른롤-오프(roll-off) 특성을 보여준다. 본 발명의 소자의 경우, 기존의 LDD 구조의 소자에 비하여 짧은 채널 길이로 갈수록 단채널 현상(SCE)에 기인한 문턱전압 감소현상이 현저히 억제되는 것을 보여주어 극소 채널 MOSFET를 구현하는데 적합한 구조임을 알 수 있다. 도 5는 드레인 전압이 0.05V 일 때의 문턱전압과 1V 일 때의 문턱전압의 차이로 나타낸 DIBL(drain induced barrier lowering) 특성을 보여주고 있다. 드레인(drain)에 인가된 전압의 변화에 따라서 본 발명의 소자는 기존의 LDD 구조의 소자보다 안정적인 동작특성을 보여줌을 알 수 있다.Figure 4 shows the roll-off (roll-off) characteristics according to the gate length of the threshold voltage of the two devices through the above experiment. The device of the present invention shows that the threshold voltage reduction caused by the short channel phenomenon (SCE) is significantly suppressed as the channel length is shorter than that of the conventional LDD structure device. Can be. FIG. 5 shows a drain induced barrier lowering (DIBL) characteristic as a difference between a threshold voltage when the drain voltage is 0.05V and a threshold voltage when 1V. According to the change of the voltage applied to the drain, it can be seen that the device of the present invention exhibits more stable operation characteristics than the device of the conventional LDD structure.
본 발명의 전계효과 트랜지스터는 전자를 여기시키는 역할을 수행하는 두 개의 사이드 게이트는 각각 다른 전압을 인가할 수 있으므로 짧은 채널에서의 소자특성을 다양하게 분석할 수 있게 된다. 또한, 본 발명은 제조공정이 간단하고 특히 마지막 메인 게이트 형성시에 측벽형성 공정을 이용하여 메인 채널의 크기를 보다 더 짧은 길이로 축소할 수 있어서 극미세 게이트를 형성할 수 있다. 그리고 메인 게이트를 형성하기 전에 채널 영역만을 부분적으로 도핑을 조절 할 수 있는 장점을 가진다.In the field effect transistor of the present invention, the two side gates, which serve to excite electrons, may apply different voltages, and thus, various device characteristics in a short channel may be analyzed. In addition, the present invention can simplify the manufacturing process, and in particular, can reduce the size of the main channel to a shorter length by using a sidewall forming process at the last main gate formation, thereby forming an ultrafine gate. And before forming the main gate has the advantage that only partially doping can be adjusted in the channel region.
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