KR20020068620A - Bit line sense amp - Google Patents

Abstract

PURPOSE: A bit line sense amp is provided to improve an initial sensing speed by using a transistor bulk bias voltage of a bit line sense amp as a sense amp driving signal. CONSTITUTION: A pull-up transistor driving unit(21) is composed of a plurality of PMOS(P-type Metal Oxide Semiconductor) transistors. A pull-down transistor driving unit(22) is composed of a plurality of NMOS(N-type Metal Oxide Semiconductor) transistors. A bit line equalizing unit(23) is composed of a plurality of NMOS transistors. A first control unit(24) receives a first switch signal, supplies a well bias voltage of an NMOS transistor into a bulk tap of the NMOS transistor in the pull-down transistor driving unit(22) and the bit line equalizing unit(23), and controls a pull-down bias signal for driving the pull-down transistor driving unit(22). A second control unit(25) receives a second switch signal, controls the pull-down bias signal of the pull-up transistor driving unit(21), and supplies a well bias voltage of the PMOS transistor.

Description

Bit line sense amp

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to bit line sense amplifiers suitable for improving sensing speed.

As DRAMs become more integrated and larger in capacities, the size of a cell based on one transistor and one capacitor becomes smaller and smaller, and scaling down of the size is an internal operating voltage to ensure reliability. Simultaneously bringing down the scaling.

The data held by a cell is in the form of a charge on the storage node of the cell, depending on whether the data is "1" or "0", unless the cell's capacitance is dramatically increased and the bit is selected. Forming the voltage difference between the line and bit varine and the bit line and bit varine after charge sharing is affected by the operating voltage.

Therefore, scaling down the operating voltage requires better sensitivity of the bit line sense amplifier.

However, as transistors shrink in size, it becomes more difficult to maintain the symmetry of the flip-flop circuits that make up the bitline sense amplifier.

When the sense amplifier breaks the symmetry, the sensitivity is sharply dropped. Therefore, a solution for this problem is being sought.

In addition, as the channel length of the transistor decreases, the degree of deviation in which the channel length of the transistor deviates from the originally determined value increases, and as the division of the channel length increases, the threshold voltage becomes larger. The division of is also increased.

Therefore, in the case of a bit line sense amplifier that requires precise symmetry for good sensitivity, the sudden decrease in the sensitivity due to the mismatch of threshold voltages dramatically increases the time taken by the sensing time in the operation of the DRAM, thereby reducing the overall execution speed.

This is a problem that must be solved in light of the current trend of demanding fast DRAM.

On the other hand, the power consumption is increased during the sensing operation of the bit line sense amplifier of the semiconductor memory device, and the power noise is increased by the charge movement according to the sensing operation.

In order to reduce such power noise, a method of charging one of the bit line pairs at a level slightly lower than the power supply voltage level and the other at a level slightly higher than the ground voltage level has been proposed during sensing operation of the bit line sense amplifier.

However, this method reduces the signal margin during the restore operation.

Therefore, in order to reduce power consumption of current high density DRAM, a method of reducing supply voltage is used.

Hereinafter, a conventional bit line sense amplifier will be described with reference to the accompanying drawings.

1 is a circuit diagram illustrating a conventional bit line sense amplifier.

As shown in FIG. 1, a pull-down transistor driver 11, a pull-up transistor driver 12, and a bit line equalizer 13 connected to the bit line BL and the bit varine BLB are included.

The pull-down transistor driver 11 receives a pull-down bias signal SB to drive a sense amplifier, and the pull-up transistor driver 12 receives a pull-up drive bias signal RTO. The bit line equalizer 13 receives the precharge control signal BLP and the precharge voltage VBLP to maintain the bit line BL and the bit varine / BL at the same voltage.

Meanwhile, the pull-down transistor driver 11 includes two NMOS transistors N1 and N2 connected in series between a bit line BL and a bit varine / BL, and the pull-up transistor driver 12, two PMOS transistors P1 and P2 are connected in series between a bit line BL and a bit varine (/ BL).

In the bit line equalizing unit 13, a precharge control signal BLP is commonly applied to the gates of three NMOS transistors N3, N4, and N5.

However, the conventional bit line sense amplifier as described above has the following problems.

First, as the sensing speed of the device is reduced, the stored data level is smaller, the sensing signal is smaller, and the precharged bit line voltage is reduced, which reduces the gate-source voltage of the transistor, thereby reducing the current stability.

Second, even though the device scales down, the bitline loading does not decrease in proportion to the current stability, thus increasing the sensing and storage time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. By connecting the bulk bias of the transistor to the sense amplifier driving line, the body effect is reduced to reduce the transconductance of the sensing transistor. The objective is to provide a bitline sense amplifier that increases the initial sensing speed by increasing current stability.

1 is a circuit diagram illustrating a conventional bit line sense amplifier.

2 is a circuit diagram illustrating a bit line sense amplifier according to the present invention.

Explanation of symbols for the main parts of the drawings

21: pull-up transistor driver 22: pull-down transistor driver

23: bit line equalizing unit 24: first control unit

25: second control unit

The bit line sense amplifier according to the present invention for achieving the above object is a pull-up transistor driver consisting of a plurality of PMOS transistors connected in series between the bit line and the bit varine and a pull composed of a plurality of NMOS transistors A bit line sense amplifier comprising a down transistor driving unit and a bit line equalizing unit including a plurality of NMOS transistors, the NMOS transistor being received at a bulk end of the NMOS transistor of the pull-down transistor driving unit and the bit line equalizing unit by receiving an external first switch signal. A first control unit configured to apply a well bias voltage of and to control a pull-down bias signal for driving the pull-down transistor driver, and to receive a second switch signal that is out of phase with the first switch signal; Pull-down bias signal And a second controller for adjusting and applying a well bias voltage of the PMOS transistor.

Hereinafter, a bit line sense amplifier according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram illustrating a bit line sense amplifier according to the present invention.

As shown in FIG. 2, a pull-up transistor driver 21 and a plurality of PMOS transistors P1 and P2 connected in series between a bit line BL and a bit varine (/ BL) are provided. A bit line sense amplifier comprising a pull-down transistor driver 22 composed of NMOS transistors N1 and N2 and a bit line equalizer 23 composed of a plurality of NMOS transistors N3, N4 and N5. The well bias voltage of the NMOS transistor at the bulk terminals of the NMOS transistors N1, N2. N3, N4, N5 of the pull-down transistor driver 22 and the bit line equalizer 23 by receiving the first switch signal SW The first control unit 24 for applying (VBB) and adjusting the pull-down bias signal SB for driving the pull-down transistor driver 22 and the phase of the first switch signal SW are opposite to each other. A pull-up transistor driver 2 receiving the second switch signal SWB And a second controller 25 for adjusting the pull-down bias signal STO of 1) and applying the PMOS transistor well bias voltage to the bulk terminals of the PMOS transistors P1 and P2.

Here, the first control unit 24 has a first NMOS transistor having a gate connected to an external first switch signal SW, a pull-down transistor driver 22 connected to a drain, and a ground voltage VSS connected to a source. 24a, a first delay unit 24b for delaying and outputting the first switch signal SW by a predetermined time, and an output signal of the first switch signal SW and the first delay unit 24b. A NAND gate 24c that is received as an input and is logically operated and output, a drain is connected to the drain of the first NMOS transistor 24a, a bulk bias voltage VBB of the NMOS transistor is connected to the source, and a NAND gate 24c is connected to the gate. Is composed of a second NMOS transistor 24d to which an output signal is connected.

The second controller 25 has a gate connected to the second switch signal SWB having a phase opposite to that of the first switch signal SW, a pull-up transistor driver 21 connected to a drain, and a power source supplied to the source. A first PMOS transistor 25a connected to a voltage VDD, a second delay unit 25b delaying and outputting the second switch signal SWB by a predetermined time, the second switch signal SWB, and A NOR gate 25c that receives the output signal of the second delay unit 25b as an input and performs a logic operation and outputs the same; a drain is connected to a drain of the first PMOS transistor 25a, and a bulk bias voltage of the PMOS transistor VPP) is connected to the gate and the second PMOS transistor 25d is connected to the output signal of the NOR gate (25c).

The pull-down and pull-up bias signals SB and RTO applied to the pull-down transistor driver 22 and the pull-up transistor driver 21 for driving the bit line sense amplifier of the present invention configured as described above are The source terminal of each MOS transistor is connected to the NMOS transistor well bias voltage (VBB) at SB and to the PMOS transistor well bulk bias voltage (VPP) at RTO to reduce the threshold voltage increase due to the body effect.

Specifically, at the start of sensing the bit line sense amplifier, the first switch signal SW is applied as "L" to connect the NMOS transistor well bulk bias voltage VBB to SB, and the first switch signal SW is again applied after a predetermined time. It is applied as "H" to disconnect the VBB after a certain delay and connect to the VSS.

At the start of sensing of the bit line sense amplifier, the second switch signal SWB is also applied as "H" to connect the PMOS transistor well bias voltage VPP to the RTO, and after a predetermined time, the SWB is applied again as "L" for a constant delay. Later, it disconnects from VPP and connects to VDD to speed up the initial sensing speed of the sense amplifier.

As described above, the bit line sense amplifier according to the present invention has the following effects.

In other words, by using the transistor bulk bias voltage of the bit line sense amplifier as the sense amplifier driving signal, the initial sensing speed can be improved by increasing the transconductance of the sensing transistor and improving the current stability of the sense amplifier while reducing the body effect.

Claims (3)

A pull-up transistor driver consisting of a plurality of PMOS transistors connected in series between the bit line and bit barine, a pull-down transistor driver consisting of a plurality of NMOS transistors, and a bit line equalizing part consisting of a plurality of NMOS transistors In the bit line sense amplifier, In response to an external first switch signal, a well bias voltage of an NMOS transistor is applied to a bulk terminal of an NMOS transistor of a pull-down transistor driver and a bit line equalizer, and a pull-down bias signal for driving the pull-down transistor driver is adjusted. The first control unit And a second controller configured to receive a second switch signal having a phase opposite to that of the first switch signal, to adjust a pull-down bias signal of a pull-up transistor driver, and to apply a well bias voltage of a PMOS transistor. Bitline Sense Amplifier. The method of claim 1, wherein the first control unit A first NMOS transistor having a gate connected to an external first switch signal, a source connected to a ground voltage, and a drain connected to a driving part of a pull-down transistor; A first delay unit delaying and outputting the first switch signal; A NAND gate that receives the first switch signal and the output signal of the first delay unit and performs logic operation on the first switch signal; And a second NMOS transistor having a drain connected to a drain of the first NMOS transistor, a source connected to a bulk bias voltage, and an output signal of a NAND gate applied to a gate thereof. The method of claim 1, wherein the second control unit A first PMOS transistor having a gate connected to the second switch signal, a source connected to a power supply voltage, and a drain connected to a driving unit of a pull-up transistor; A second delay unit delaying and outputting the second switch signal; A NOR gate receiving the output signal of the second switch signal and the second delay unit and performing logic operation on the output signal; And a second PMOS transistor having a drain connected to a drain of the first PMOS transistor, a source connected to a bulk bias voltage, and an output signal of a NOR gate applied to a gate thereof.