KR20020067788A - Apparatus for testing single chip having multiple peripheral blocks - Google Patents

Abstract

PURPOSE: A single chip test apparatus having plural peripheral blocks is provided to diversify test conditions, reduce a time for debugging, and perform a concentrated test for a particular block. CONSTITUTION: The first logic block(26) outputs the first selection signal(C3) by calculating a control signal(C4) and the first port block drive signal(C1). The first port block(18) receives or transmits data from or to the first input/output pin(160) according to a logic level of the first selection signal(C3). The second logic block(28) outputs the second selection signal(C6) by calculating the control signal(C4) and the second port block drive signal(C2). The second port block(20) receives or transmits data from or to the second input/output pin(170) according to a logic level of the second selection signal(C6). A multiplexer(22) outputs selectively predetermined signals(N3,N1) according to a logic level of the control signal(C4). A peripheral block(16) performs a predetermined test process according to an output signal of the multiplexer(22). A demultiplexer(24) outputs a test result to a CPU(14) or the second port block(20) according to the logic level of the control signal(C4). The CPU(14) output a predetermined signal(N1) in response to command signals applied from external command ports(100,110,120) and a signal(N2) of the demultiplexer(24) to data pins(130,140,150).

Description

Apparatus for testing single chip having multiple peripheral blocks

The present invention relates to a single chip test apparatus and method, and more particularly, to a single chip test apparatus and method having a plurality of peripheral blocks associated with a central processing unit.

Currently, the concept of a single chip that embeds peripheral blocks that perform various functions in a central processing unit, such as a microcontroller unit (MCU), on a single chip is becoming common, and this SOC concept is expected to continue in the future.

Therefore, circuit designers are more than ever required to take measures to prevent malfunctions of internal components resulting from high integration of the system. Chip testing is intended to improve fault coverage by eliminating malfunctions of these devices due to manufacturing process errors. There are various test methods. Figure 1 shows one of them, which shows a conventional test scheme for a single chip.

Referring to FIG. 1, the peripheral block 16 present in the test block 12 in the single chip 10 is tested through a control signal generated from the central processing unit 14.

1 shows a test procedure for one peripheral block 16. The single chip 10 may have a plurality of peripheral blocks, and a circuit designer should examine all of the plurality of peripheral blocks through a diagnostic process. That is, although FIG. 1 only shows one peripheral block as an example, it is noted that there may be a plurality of peripheral blocks.

Referring to FIG. 1, a single chip 10 includes one central processing unit, one peripheral block, and two port blocks.

That is, the single chip 10 is connected to the test block 12, the input / output pins 160 and 170, the test pin 180, and the test block 12 to execute external instructions in the test mode. Ports 100, 110, 120 for receiving, data output pins 130, 140, 150 connected to the test block 12 and outputting a test result signal N2 to the outside; A first port block 18 and an input / output pin (PB) 170 connected between the / output pin (PA) 160 and the test block 12 to form an input / output path of data. And a second port block 20 connected therebetween to form an input / output path for data.

The test block 12 is driven by commands input to the ports 100, 110, and 120 to generate a control signal N1, and the test result signal N2 from the peripheral block 16. A central processing unit 14 that performs the function of receiving and outputting the data output pins 130, 140, 150 and the test signal in response to the control signal N1, and as a result the signal N2 is subjected to the central processing A peripheral block 16 is output to the device 14.

In the single chip 10 having the above-described configuration, the test operation on the peripheral block 16 is as follows.

First, the single chip 10 enters the test mode when "logic high" is input through the test pin 180.

In this case, the CPU 14 is driven by commands input to the external command ports 100, 110, and 120 to generate the control signal N1. The peripheral block 16 generates a predetermined output signal N2 in response to this control signal N1. The CPU 12 receives the signal N2 and outputs a final test result to the data output pins 130, 140, and 150.

As described above, the conventional single chip test mechanism assigns external specific ports to apply external command signals. The central processing unit is driven by these command signals and generates signals to control the test block. The peripheral blocks are tested by control signals generated by the CPU, and the result is transmitted to the outside through the data output pins.

This test method has a limited understanding of the many instructions for driving the CPU and the test conditions, and the system designer has a lot to analyze in which peripheral block an error occurs when debugging a plurality of peripheral blocks. It is time consuming and difficult to intensively test specific blocks.

SUMMARY OF THE INVENTION An object of the present invention is to provide a single chip test apparatus capable of diversifying test conditions, reducing the time required for debugging, and intensive testing of specific blocks.

1 is a conventional embodiment showing a test mechanism of one peripheral block using a central processing unit in a single chip having a plurality of peripheral blocks; And

2 is a preferred embodiment of the present invention showing a test mechanism of one peripheral block using a central processing unit and input / output pins in a single chip having a plurality of peripheral blocks.

Explanation of symbols on the main parts of the drawings

10: single chip 12: test block

14: CPU 16: Peripheral Block

18: first port block 20: second port block

22: multiplexer 24: demultiplexer

26: first logical block 28: second logical block

100, 110, 120: External command port 130, 140, 150: Data output pin

180: test pins 160, 170 ,: input / output pins

190: control pin C1: first port block drive signal

C2: second port block driving signal C3: first selection signal

C6: second selection signal C4: control signal

(Configuration)

In order to solve the drawbacks of the prior art, the present invention provides a single chip test apparatus capable of diversifying test conditions, reducing debugging time, and intensive testing of specific blocks.

The apparatus having a plurality of peripheral blocks associated with the central processing unit includes first logical blocks, first port blocks, multiplexers, peripheral blocks, demultiplexers, second logical blocks, and second port blocks. do.

The first logic blocks output a first select signal of logic low when the logic level of the control signal input to the control pin is logic low, and output the first select signal of logic high when the logic level of the control signal is logic high. Perform the function of printing.

The first port blocks receive data from a first input / output pin or output data to the first input / output pin according to a logic level of the first selection signal.

The multiplexers select / output data signals output from the first port blocks when the logic level of the control signal is logic high, and output data signals from the CPU when the logic level of the control signal is logic low. Perform the function of selecting / outputting.

The peripheral blocks are tested by the data signals output from the first port blocks when the logic level of the control signal is logic high, and the data signals output from the CPU when the logic level of the control signal is logic low. Is tested by

The demultiplexers output the test results of the peripheral blocks to second port blocks when the logic level of the control signal is logic high, and output the test results of the peripheral blocks when the logic level of the control signal is logic low. Outputs to the processing device.

The second logic blocks output a logic high second selection signal when the logic level of the control signal input to the control pin is logic low, and output the second selection signal of logic low when the logic level of the control signal is logic high. Perform the function of printing. And

The second port blocks receive data from a second input / output pin or output data to the second input / output pin according to a logic level of the second selection signal.

(Action)

With this device, the circuit designer can selectively apply the logic level of the control signal input to the control pin to test each peripheral block by driving the central processing unit or by directly using the input / output pins without driving the central processing unit. Test is possible.

(Example)

Hereinafter, a detailed description of the present invention related to the claims will be described in detail by way of examples.

The accompanying drawings are included to provide a further understanding of the invention and are part of this specification.

2 is a preferred embodiment of the present invention showing a test mechanism of one peripheral block using a central processing unit and input / output pins in a single chip having a plurality of peripheral blocks.

Referring to FIG. 2, the embodiment of the present invention outputs a first selection signal C3 by performing a logic operation on the control signal C4 and the first port block driving signal C1 input to the control pin PC. According to the first logic block 26 and the logic level of the first selection signal C3, data is received from the first input / output pin 160 (PA) or the first input / output pin 160. A second logic for outputting a second selection signal C6 by performing a logic operation on the first port block 18 for outputting data to the PA and the control signal C4 and the second port block driving signal C2. According to the block 28 and the logic level of the second selection signal C6, data may be input from the second input / output pin 170 (PB) or may be input to the second input / output pin 170 (PB). From the second port block 20 for outputting data and the predetermined signal N3 or the central processing unit 14 output from the first port block 18 according to the logic level of the control signal C4. A multiplexer 22 that selects / outputs a predetermined signal N1 to be output, a peripheral block 16 that performs a predetermined test process in response to an output signal of the multiplexer 22, and the control signal C4. The demultiplexer 24 and the external command ports 100, 110, and 120 outputting the test result of the peripheral block 16 to the CPU 14 or the second port block 20 according to the logic level of the circuit. Central processing for outputting the predetermined signal N1 in response to the command signals applied and finally outputting the predetermined signal N2 output from the demultiplexer 24 to the data output pins 130, 140, and 150. Apparatus 14 is provided.

The first logic block 26 has an OR gate.

The second logic block 28 has an inverter and an end gate.

For reference, there may be a plurality of peripheral blocks associated with the central processing unit in a single chip, and the embodiment of the present invention reveals that one peripheral block is taken as an example for convenience of description.

Operation of the embodiment of the present invention having the above configuration is as follows.

First, when logic high is input to the test pin 180 (TEST), the single chip enters the test mode.

In this condition, when the logic level of the control signal C4 is logic low, the first selection signal C3, which is an output of the first logic block 26, depends on the logic level of the first port block driving signal C1. That is, when the logic level of the first port block driving signal C1 is logic low, the first selection signal C3 becomes logic low, and the first selection when the logic level of the first port block driving signal C1 is logic high. Signal C3 is logic high. In the present invention, when the logic level of the first port block driving signal C1 and the second port block driving signal C2 is logic low, the first port block 18 and the second port block 20 are output pins. When the logic level of the first port block driving signal C1 and the second port block driving signal C2 is logic high, the first port block 18 and the second port block 20 are set as input pins. Accordingly, the first select signal C3 becomes logic low and the first port block 18 operates as a data output pin. Similarly, the second selection signal C6, which is the output of the second logic block 28, depends on the logic level of the second port block driving signal C2 since the logic level of the control signal C4 is logic low. As described above, since the logic level of the second port block driving signal C2 is logic high at this time, the logic level of the second selection signal C6 is logic high, and thus the second port block 20 is connected to the input pin. It works.

On the other hand, the multiplexer 22 forms a pass between the central processing unit 14 and the peripheral block 16 when the logic level of the control signal C4 is logic low. Accordingly, the multiplexer 22 transmits a predetermined output signal N1 of the CPU in response to the command signals applied to the external command ports 100, 110, and 120 to the peripheral block 16.

The demultiplexer 24 forms a pass between the central processing unit 14 and the peripheral block 16 as well when the logic level of the control signal C4 is logic low. The demultiplexer 24 thus delivers the results tested in the peripheral block 16 to the central processing unit 14.

The central processing unit 14 finally completes the test operation by finally outputting the data transmitted through the demultiplexer 24 to the data output pins 130, 140 and 150.

In summary, in the single chip test apparatus according to the embodiment of the present invention, when the logic level of the control signal C4 is logic low, the test operation is performed through a path including a central processing unit, a multiplexer, a peripheral block, and a demultiplexer.

Next, when the logic level of the control signal C4 is logic high, the first selection signal C3, which is an output of the first logic block 26, is always logic high regardless of the logic level of the first port block driving signal C1. to be. Accordingly, the first port block 18 operates as an input pin.

Similarly, when the logic level of the control signal C4 is logic high, the logic level of the second selection signal C6, which is the output of the second logic block 28, is independent of the logic level of the second port block driving signal C2. It is always logic low. Accordingly, the second port block 20 operates as an output pin.

Meanwhile, the multiplexer 22 connects the first port block 18 and the peripheral block 16 when the logic level of the control signal C4 is logic high. In other words, it is turned off between the central processing unit 14 and the peripheral block 16.

Similarly, the demultiplexer 24 performs a function of connecting the peripheral block 16 and the second port block 20 when the logic level of the control signal C4 is logic high. In other words, it is turned off between the central processing unit 14 and the peripheral block 16.

Accordingly, the peripheral block 16 is tested by the data signal transmitted through the first port block 18 and the multiplexer 22, and the test result is passed through the demultiplexer 24 and the second port block 20. It has a mechanism that is output to the outside.

In summary, in the single chip test apparatus according to the embodiment of the present invention, when the logic level of the control signal is logic high, the test operation is performed through a path formed through the first port blur, the multiplexer, the peripheral device, the demultiplexer, and the second port block. . That is, a mechanism for testing each peripheral block using input / output pins, rather than a mechanism for testing each peripheral block through a driving signal generated by driving the CPU, is used.

As described above, in the present invention, a system designer applies a variable control signal through a control pin to test a single chip including a plurality of peripheral devices, thereby testing each peripheral block through a central processing unit as necessary. Or have a mechanism to test each peripheral block using input / output pins.

As mentioned above, the present invention has the advantage of allowing system designers to test a single chip, reducing test time and cost, and diversifying test conditions.

Claims (6)

In a single chip test apparatus having a plurality of peripheral blocks associated with a central processing unit, A first logic block outputting a first select signal of logic low when the logic level of the control signal input to the control pin is logic low, and outputting the first select signal of logic high when the logic level of the control signal is logic high With; First port blocks receiving data from a first input / output pin or outputting data to the first input / output pin according to a logic level of the first selection signal; Selecting / outputting a data signal output from the first port block when the logic level of the control signal is logic high, and selecting / outputting a data signal output from the central processing unit when the logic level of the control signal is logic low Multiplexers; The test signal is output from the first port blocks when the logic level of the control signal is logic high, and the test signal is output by the data signal output from the CPU when the logic level of the control signal is logic low. Surrounding blocks; When the logic level of the control signal is logic high, the test results of the peripheral blocks are output to the second port blocks to be performed. When the logic level of the control signal is logic low, the test results of the peripheral blocks are sent to the CPU. Output demultiplexers; A second logic block outputting a second logic high selection signal when the logic level of the control signal input to the control pin is logic low and outputting the second logic signal of the logic low when the logic level of the control signal is logic high field; And And second port blocks receiving data from a second input / output pin or outputting data to the second input / output pin according to a logic level of the second selection signal. The method of claim 1, The CPU outputs the data signal to the multiplexers in response to external command signals applied to external ports when the logic level of the control signal is logic low, and outputs a data signal input from the demultiplexers. Single chip test device, characterized in that output to the pins. The method of claim 1, And the first logic blocks comprise an OR gate. The method of claim 1, And the second logic blocks comprise an inverter and an end gate. According to claim 1, When the logic level of the first selection signal is logic high, the first port blocks receive a data signal from the first input / output pins and output the data signal to the multiplexers, and when the logic level of the first selection signal is logic low. And outputting a data signal to the first input / output pins. The method of claim 1, The second port blocks receive data from the second input / output pins when the logic level of the second select signal is logic high, and input the output signals of the demultiplexers when the logic level of the second select signal is logic low. Single chip test device, characterized in that for outputting to the second input / output pins.