KR20020067169A - Apparatus for processing instruction - Google Patents

Abstract

PURPOSE: A device for processing a command is provided to add an effective second cache to the first cache horizontally in an electric power satisfied with almost command demand at a microprocessor. CONSTITUTION: The first program counter(100) supplies a command address to be performed in a microprocessor to a cache access control unit(120), the first cache(130), and the second cache(140). The second program counter(110) supplies a command address to be performed in the next cycle of the command address supplied in the first program counter(100) to the cache access control unit(120) based on a branch address calculated in the microprocessor. A command searched in the first cache(130) and the second cache(140) is transmitted to a register(150) and stored temporarily. A command selection unit(160) selects one out of commands stored in the register(150). A multiplex unit(170) receives a command selection signal output by the command selection unit(160) out of commands of the first cache(130) and the second cache(140) received from the register(150) and transmits a corresponding command to a control unit(180). The control unit(180) decodes the command output in the multiplex unit(170) and supplies a sleeping control signal of the first cache(130). A flip-flop(190) supplies an input value to a logic unit(200) by a control signal output by the control unit(180), and an output value of the flip-flop(190) decides an operation or not of the cache access control unit(120).

Description

Command Processing Unit {APPARATUS FOR PROCESSING INSTRUCTION}

The present invention relates to an instruction processing apparatus, and more particularly, to an instruction processing apparatus in which a cache for processing instructions of a microprocessor is additionally added to the first cache.

With the development of information and communication technology, the importance of mobile systems such as mobile phones, personal digital assistants (PDAs), and video mobile phones is increasing day by day. Continuous operating time, which indicates how long a battery can be charged once, is one of the most important performance metrics for commercial mobile systems, and reducing the power consumption of mobile systems is an important factor in system design.

Even in non-mobile systems, power consumption is an important design goal. This is because high power dissipation generates a lot of heat inside the system, causing the semiconductor to degrade, malfunction, or even fail. Due to these problems, various low power techniques are recently required in terms of software and hardware.

In particular, high performance embedded processors require large on-chip instruction caches for fast instruction access. In this case, it is effective in terms of performance, but inefficient in terms of power.

In fact, studies on power efficiency have been discussed for many years. However, existing methods did not meet both goals of efficiency and power efficiency. Power was sacrificed for efficiency in terms of performance, and performance was reduced for efficiency in terms of power.

In summary, previous studies focusing on low-power caches can be divided into two types: changing the structure of the cache and adding more efficient cache in terms of power without changing the structure of the cache. have,

The way to change the internal structure of the cache is to divide the cache and specify only the necessary parts as the active state and the unnecessary parts as the inactive state to save power.

The first is an optional cache way method, in which only some of the multiple ways in a set of caches are designated as active, and the remaining ways are idle. It is a method of eliminating unnecessary consumption in terms of power by specifying an inactive state. In a similar approach, only some of the banks in the cache are designated as active to take power efficiency.

Secondly, the method of adding a power-efficient cache is to reduce power consumption by adding another power-efficient cache to an existing memory hierarchy. By using this small capacity-and thus power efficiency-for most of the instruction demands-an approach that reduces the power consumed in the overall memory structure. In addition, depending on how the additional cache is configured in the memory hierarchy, it is divided into two methods, vertically and horizontally.

First, a method of adding in a long way is to add a second cache between the processor and the first cache. This method allows a second power efficient cache to satisfy most of the instruction requirements, thereby minimizing power consumption in other memory layers, thereby reducing power consumption in the overall memory structure.

However, if the second cache does not satisfy the instruction request, it causes a big problem of performance degradation due to unnecessary cycle consumption which does not occur in the existing system. This is a fatal problem for modern applications that require high performance processors. The loop cache method proposed to solve this problem in terms of performance degradation solves the problem in terms of performance by improving the existing methods in hardware and software, but the scope of application is limited. There is a problem that its use is limited.

The horizontally adding method is a method of adding another cache in the same layer as the first cache. This includes adding small buffers (e.g., victim caches) to use power efficient caches only for specific purposes.

However, the method of adding horizontally has a problem in that the application frequency of the added hardware is limited and its application range is limited.

An object of the present invention is to solve the problems of the prior art, and to provide an instruction processing apparatus which adds a second cache to the first cache in terms of power that satisfies most instruction requirements of the microprocessor. .

In order to achieve the above object, the present invention provides an instruction processing apparatus including an instruction address to be executed in a microprocessor and a first cache in which instructions corresponding to the instruction address are stored. An address providing means for providing an address of the first cache; and instructions stored in the first cache, dependent on the first cache, and horizontally added to perform an instruction request of the microprocessor, and an instruction corresponding to the instruction address. A second cache for providing hit information by determining the presence or absence of the second cache; a storage means for temporarily storing the hit information and the instructions stored in the first cache and the second cache; and the stored instruction by the stored hit information of the storage means. Command selection means for selecting one of the First control means for generating a control signal according to whether or not the instruction address and the instruction address performed in the next cycle are the same set; and decoding the instruction selected by the instruction selecting means to provide a control signal. And second logic means and logic means for outputting a control signal for determining whether the first cache is dormant by performing a logic operation on the control signals output from the first control means and the second control means. Command processing device.

1 is a block diagram illustrating a low power instruction cache apparatus which is an instruction processing apparatus according to an embodiment of the present invention;

2 is a flowchart illustrating an operation of a low power command cache apparatus according to an embodiment of the present invention.

<Description of the code | symbol about the principal part of drawing>

100: first program counter 110: second program counter

120: cache access control unit 130: first cache

140: second cache 150: register

160: command selection unit 170: multiplex unit

180 control unit 190 flip-flop

200: logic means

There may be a plurality of embodiments of the present invention, hereinafter with reference to the accompanying drawings will be described in detail a preferred embodiment. Through this embodiment, it is possible to better understand the objects, features and advantages of the present invention.

1 is a block diagram of a low power instruction cache device according to an embodiment of the present invention.

As shown in FIG. 1, the low power command cache device includes a first program counter 100, a second program counter 110, a cache access control unit 120, a first cache 130, and a second cache. 140, a register 150, an instruction selector 160, a multiplexer 170, a controller 180, a flip-flop 190, and a logic means 200.

The first program counter 100 provides an instruction address to be executed in the current microprocessor to the cache access controller 120, the first cache 130, and the second cache 140, and the second program counter 110. The cache provides the cache access control unit 120 with an instruction address to be executed in the next cycle of the instruction address provided by the first program counter 100 based on the branch address calculated by the microprocessor.

The cache access controller 120 is a first control means for providing the logic means 200 with a control signal for dominating the first cache 130. The first program counter 100 and the second program counter 110 may be used. It is determined whether or not the same set is compared by comparing the instruction addresses provided by &lt; RTI ID = 0.0 &gt; and &lt; / RTI &gt; Regardless of the output value of the flop 190, the first cache 130 is dynamically dormant (that is, the first cache 130 is dormant by a hardware control method). In addition, when the determination result is not the same set, the cache access control unit 120 sets the value of the control line 1 to "0", and the dormant of the first cache 130 is dormant by the output value of the flip-flop 190. It is decided whether or not to

The first cache 130 and the second cache 140 retrieve the instructions stored in the first cache 130 and the second cache 140 corresponding to the instruction address received from the first program counter 100. .

Instructions retrieved from the first cache 130 and the second cache 140 are transferred to register 1 151 and register 2 152 of the register 150 and temporarily stored.

In this case, whether the first cache 130 is dormant is determined by the output of the logic means 200, and the second cache 140 is a cache horizontally added to the first cache 130, the first cache ( The command corresponding to the address input by the first program counter 100 is executed according to whether or not 130 is dormant.

In addition, the second cache 140 is a cache in which some of the instructions stored in the first cache 130 are stored and efficiently added in terms of power for executing the instructions requested by the microprocessor, and the dormant of the first cache 130 is dormant. Once in the busy state, the microprocessor's instruction request can be fulfilled.

The register 150 is a storage means for temporarily storing instructions retrieved from the first cache 130 and the second cache 140. The register 150 temporarily stores instructions received from the first cache 130. ), A register 2 152 for temporarily storing instructions received from the second cache 140, and a command corresponding to an address provided by the first program counter 100 in the second cache 140. Register 3 (153), which receives the hit information of the second cache 140 from the second cache 140, and register 4 (154) that stores the presence or absence of the first cache 130 dormant. .

The instruction selector 160 is a means for selecting one of the instructions stored in the register 150. The instruction selector 160 stores the first cache stored in the register 1 151 based on the information stored in the register 3 153 and the register 4 154. An instruction to be performed is selected from the instructions provided at 130 and those provided by the second cache 140, and the selected instructions are provided to the multiplex unit 170.

In other words, when the command selector 160 receives the sleep information of the first cache 130 stored in the register 3 153 and the hit information of the second cache 140 stored in the register 4 154. , To provide the signal to the multiplexer 170 to perform the instructions provided to the second cache 140.

The multiplex unit 170 selects an instruction output by the instruction selector 160 from among instructions of the first cache 130 and the second cache 140 received from the register 1 151 and the register 2 152. The signal is transmitted and the corresponding command is transmitted to the controller 180.

At this time, the instruction stored in the register 150 provided to the multiplex unit 170 has a special instruction "first cache dormancy instruction" or "cache access control operation instruction" inserted by the compiler.

Special instructions inserted by the compiler are inserted using cache trace information.

First, the compiler classifies a set of basic blocks requiring hardware control and a set of basic blocks requiring software control.

The compiler analyzes the cache trace information for the base block, and if the analysis results indicate that the software control of the base block is less than the hardware control, the value of the energy delay product is lower than that of the base block. Are classified as basic blocks to be controlled in hardware.

As a result of classification, the basic block to be controlled by software is inserted by the compiler at the beginning of the basic block, and the "first cache dormancy instruction" is inserted by the compiler. Access control operation instruction ”is inserted.

The controller 180 is a second control means for decoding a command output from the multiplex unit 170 and providing a dormancy control signal of the first cache 130, and the command transmitted by the multiplex unit 170. Decoded instructions inserted by the compiler in the processor included in the and transmitted to the flip-flop 190 through the control line (2) or (3).

When the command decoded by the controller 180 is the “first cache sleep instruction”, the control line 3 is set to “1” to be transmitted to the flip-flop 190, and the “cache access control operation command” is In the case of decryption, the control line 3 is set to "1" and transmitted to the flip-flop 190.

The flip flop 190 provides an input value to the logic means 200 by a control signal output by the controller 180, and the output value of the flip flop 190 determines whether the cache access controller 120 operates. do.

In this case, when the output value of the flip flop 190 is "1", the first cache 120 outputs the logic means 200 regardless of the output value of the cache access control unit 120 by a software control method. When the value becomes "1", the first cache 130 is dormant and the cache access controller 120 flips the flip flop 190 by decrypting the "cache access control operation command" as a result of the basic block decryption of the controller 180. It does not operate until the output value of "0" is reached.

In contrast, when the output value of the flip flop 190 is "0", it is determined whether the first cache 130 is dormant by the output value of the cache access control unit 120.

The logic unit 200 outputs a control signal for determining whether to sleep the first cache 130 according to a control signal output from the flip flop 200 and the cache access control unit 120 as a logic sum gate.

When the output value of the logic means 200 is "1", the first cache 130 enters a sleep state, and the sleep signal of the first cache 130 is registered in register 3 (153) of the register 150. )

When the output value of the logic means 200 is "0", the first cache 130 is not dormant.

An operation of the low power command cache device having the above configuration will be described with reference to FIG. 2.

2 is a flowchart illustrating a process of operating a low power instruction cache apparatus which is an instruction processing apparatus according to an embodiment of the present invention.

Control of the first cache 140 is performed by a hardware method and a software method.

First, the hardware method is entirely performed by the cache access controller 120. The cache access controller 120 determines whether the instruction executed in the microprocessor and the instruction executed in the next cycle are included in the same cache set. Is determined based on the addresses input by the first program counter 100 and the second program counter 110 (S201 and S202).

In the case of the same set as the result of the determination in step 202, the cache access control unit 120 sets the control line 1 to "1" so that the first through the logic means 200 regardless of the output value of the flip-flop 190. The cache 130 is dormant. Instructions to be performed are performed by instructions stored in the second cache 140 (S203 and S204).

Next, in the software control method, when the command corresponding to the address input by the first program counter 100 and the second program counter 110 is not the same set, the cache access control unit ( 120 sets the control line 1 to "0" and provides it to the logic means 200 (S205).

The logic means 200 that receives the control value “0” from the cache access controller 120 through the control line 1 controls the first cache 130 based on the control value output from the flop flop 190.

The output value in the flip flop 190 provided to the logic means 200 is described by the operation as follows.

Instructions corresponding to the addresses input to the first program counter 100 stored in the first cache 130 and the second cache 140 are temporarily stored in the register 1 151 and the register 2 152 and at the same time. Cache hit information provided from the cache 140 is stored in the register 4 154, and information about whether the first cache 130 is operated according to a value output from the logic means 200 is stored in the register 3 153. Stored.

The hit information of the second cache 140 and the operation information of the first cache 130 stored in the register 4 154 are provided to the command selector 160.

The command selector 160 receives a value from the register 4 154 in which the hit information of the second cache 140 is stored and the register 3 153 in which the operation information of the first cache 130 is stored. The signal reads the hit information of the 140 and selects one of the instructions stored in the register 1 151 and the register 2 152 to the multiplex unit 170 (S206).

The multiplexer 170 selects one of the instructions stored in the register 1 151 or the register 2 152 and transmits it to the controller 180 based on the transmitted command selection signal, and the controller 180 is a multiplexer ( Information contained in the command transmitted from 170 is decoded (S207 and S208).

As a result of the decoding in step 208, when the first cache 130 dormancy command is decoded by the controller 180, the controller 180 sets the control line 3 to "1" and at the same time controls the control line 2. Is set to "0", and the flip-flop 190 transmits the value of "1" to the logic means 200 by the set control line 2 and the control line 3 (S209).

The cache access control unit 120 does not operate due to the output value “1” of the flip flop 190, and the output value of the logic unit 200 becomes “1” so that the first cache 130 transitions to the dormant state. (S204).

Instructions to be currently performed by the first cache 130 dormancy are performed by the second cache 140.

As a result of the decryption of step 208, when the operation command of the cache access control unit 120 is decoded by the control unit 180, the control unit 180 sets the control line 3 to “0” and simultaneously controls the control line 2. Is set to "1" and the flip-flop 190 transmits the value of "0" to the logic means 200 by the set control line 2 and the control line 3 (S210).

The output value of the logic means 200 becomes “0” by the output value “0” of the flip flop 190 so that the first cache 130 does not sleep and executes the current command, and the cache access control unit 120. In step S202, the process returns to step 202 to control the cache in a hardware manner (S211).

As described above, the present invention transversely adds a low-capacity second cache dependent on the first cache between the microprocessor and the first cache to perform instruction requests of most microprocessors and dormate the first cache. By doing so, it is possible to meet the efficiency requirements in terms of performance as well as the low power requirements of high performance embedded processors.

On the other hand, the present invention is not limited to the above-described embodiment, but various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims below.

Claims (4)

An instruction processing apparatus having an instruction address to be executed in a microprocessor and a first cache storing an instruction corresponding to the instruction address, Address providing means for providing an address of an instruction to be performed in a next cycle of the instruction address; A second cache that is dependent on the first cache and is laterally added to perform an instruction request of the microprocessor, determine whether there is an instruction corresponding to the instruction address, and provide hit information; Storage means for temporarily storing the hit information and instructions stored in the first cache and the second cache; Instruction selecting means for selecting one of the stored instructions by the stored hit information of the storage means; First control means for generating a control signal according to whether the instruction address and the instruction corresponding to the instruction address executed in the next cycle are the same set; Second control means for decoding a command selected by the command selecting means and providing a control signal; And logic means for performing a logic operation on the control signals output from the first control means and the second control means to output a control signal for determining whether the first cache is to be dormant. The method of claim 1, The address providing means, And a program counter for providing an instruction address signal to be executed in the next cycle. The method of claim 1, The control signal of the logic means, And a command stored in the first cache is dormant. The method of claim 1, The control signal of the first control means, And instructing the first cache to sleep the first cache irrespective of the control signal when the instruction address performed in the next cycle provided by the providing means and the instruction address are the same set. .