KR20020062432A - Smart card protection device - Google Patents

Abstract

PURPOSE: A smart card protection device is provided to protect a decryption of instruction cycles via a power pin by generating a wait signal with infrequent clock pulses and varying a CPU drive clock with a regular instruction cycle so that it can safely protect encryption data against access of unauthorized users. CONSTITUTION: The device comprises a memory(400), an IO register(100), a random wait signal generator(300), and a CPU(200). The memory(400) stores prescribed encryption data, i.e. a password. The IO register(100) receives an input password, and outputs a comparison result between the input password and the stored password. The random wait signal generator(300) outputs wait signals(nWAIT) for varying an instruction cycle of the CPU(200) according to a logic level of an input enable signal. The CPU(200) forms interface lines with the memory(400) and the random wait signal generator(300) via system buses, i.e. an address bus, a data bus and a control bus, compares the input password with the stored password, and outputs the password comparison result to the IO register(300) by being synchronized with the varied instruction cycle.

Description

Smart card protection device

The present invention relates to a smart card protection device, and more particularly, to a smart card protection device that prevents password decryption through a power pin.

In general, smart cards are credit cards with a built-in microchip that can modify or create data in response to some external stimulus. A microchip is a single chip integrated on one wafer. Smart cards are themselves like a data processor that can be used for multiple purposes. Thus, smart cards have the ability to verify whether they match a stored password stored on the storage device off-line without connecting to a computer.

On the other hand, smart card chips are first and foremost required to secure the encryption code from access by unauthorized users or electronic devices.

Typically, a smart card chip performs a series of operations in synchronization with an instruction cycle having a constant clock pulse when accessing encryption information stored in a storage device or executing instructions of a central processing unit. Since the smart card is operated in synchronization with such a certain instruction cycle, it is difficult to secure the Des Key from an unauthorized user or an electronic device. In other words, an unauthorized user can monitor external power pins to decode certain command cycles and find the Des Key (encryption information) of the smart card.

An object of the present invention is to provide a smart card prevention apparatus that prevents password decryption through a power pin by generating a weight signal having a random clock pulse to vary an instruction cycle.

1 is a block diagram of a smart card chip according to an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of the random weight generator shown in FIG. 1. FIG.

3 is an output waveform of the random clock weight generator shown in FIG.

4 is an operation timing diagram of FIG. 1 during no wait operation.

5 is an operation timing diagram of FIG. 1 during a one wait operation.

6 is an operation timing diagram of FIG. 1 during an n wait operation.

Explanation of symbols on the main parts of the drawings

100: input / output register

200: central processing unit

300: random weight generator

400: memory

(Configuration)

In order to solve the conventional drawbacks, the present invention provides a smart card prevention apparatus for varying the instruction cycle by generating a weight signal having a random clock pulse.

The smart card protection device includes a storage device, an input / output register, a central processing unit, and a random weight generator.

The storage device includes performing a function of storing predetermined encryption information; The input / output register includes a function of outputting a reception and storage password of an input password and a result of comparing the input password with the input password; The random weight generator includes a function of outputting a weight signal for varying an instruction cycle in accordance with a logic level of an input enable signal; And the central processing unit performs a function of instructing to output a comparison result of a storage password and an input password to the input / output register in synchronization with an instruction cycle varied by the weight signal.

The random weight generator includes a random clock weight generator for generating a random clock pulse; And a logic gate that inverts the random clock pulse when the input enable signal is logic high and fixes the logic level of the random clock pulse high when the input enable signal is logic high.

The logic gate is characterized in that it comprises a NAND gate.

The random weight generator generates a no-weight signal when the enable signal is logic low to operate an instruction cycle normally, and generates a 1 to n weight signal when the enable signal is logic high to N the instruction cycle. Performs a function to vary up to +1.

(Action)

According to such an apparatus, not only can the normal operation be performed while maintaining the frequency speed, but also the instruction cycle can be varied as much as the encryption operation.

(Example)

Hereinafter, the detailed description of the present invention related to the claims will be described in detail by way of examples.

The accompanying drawings are included to provide a further understanding of the invention and are part of this specification.

1 is a block diagram of a smart card prevention apparatus according to an embodiment of the present invention.

Referring to FIG. 1, the smart card prevention apparatus outputs a storage device 400 which performs a function of storing predetermined encryption information (storage password), and a result of receiving and storing an input password and comparing the input password with the input password. A random weight generator 300 that performs a function of outputting an input / output register 100 that performs a function, a weight signal nWAIT that varies an instruction cycle according to a logic level of an input enable signal, and a system bus An interface line with the storage device 400 and the input / output register 100 through the address bus, the data bus, and the control bus, and is stored in synchronization with an instruction cycle that is varied by the weight signal nWAIT. A central processing unit that performs a series of command operations, such as comparing input passwords and outputting comparison results to the input / output register 100. Tooth 200 is provided.

FIG. 2 is a detailed circuit diagram of the random weight generator 300 shown in FIG. 1.

Referring to FIG. 2, the random weight generator 300 logics a random clock weight generator for generating the aperiodic clock pulse shown in FIG. 3 with an output signal and an enable signal of the random clock weight generator. And a NAND gate for calculating and outputting the weight signal nWAIT.

The random clock weight generator shown in FIG. 2 is an already generalized clock generator, and can be implemented using an 8-bit, 16-bit and n-bit counter as a non-linearly increasing counter.

In addition, the random weight generator 300 generally controls the CPU 200 because the memory access of the memory device 400 is relatively slow in the interface operation between the CPU 200 and the memory device 400. Used for the purpose.

The present invention uses a wait state for supporting such a slow memory interface. Hereinafter, the operation of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is an operation timing diagram illustrating a data processing relationship without considering a slow memory interface as a normal operation that is not an encryption operation.

In this case, the random weight generator 300 generates a weight signal nWAIT having a constant potential level of logic high regardless of time. Thus, the central processing unit 200 completes data access and output according to the instruction cycle without weight. That is, as shown in FIG. 4, the address and output operation of data proceeds in one cycle of the clock.

FIG. 5 is an operation timing diagram illustrating a process of processing one weight and two cycle data when a slow memory interface is considered as a normal operation instead of an encryption operation.

In this case, the random weight generator 300 temporarily generates a logic high weight signal nWAIT in order to secure an access time of the memory, thereby disabling the instruction cycle one cycle.

That is, as shown in FIG. 5, the clock pulse corresponding to the logic low weight signal nWAIT is disabled so that data is output in two cycles.

6 is an operation timing diagram illustrating a process of processing n weight n + 1 cycle data during an encryption operation.

In this case, the logic low section of the weight signal nWAIT is taken for n cycles as an example. Data output is performed in n + 1 cycles.

For reference, the instruction cycle of the central processing unit 200 may occur anywhere in the 1 to n weight interval during the encryption operation. This is because the weight signal nWAIT output from the random weight generator 300 has an aperiodic clock pulse.

As shown in FIG. 2, the weight signal is always logic high regardless of the output signal of the random clock weight generator when the logic level of the enable signal is low. This shows that the instruction cycle of the central processing unit is normally done without weight. When the logic level of the enable signal Enable is high, the weight signal is a clock whose phase is inverted from the aperiodic clock shown in FIG. 3. After all, this aperiodic clock is supplied to the central processing unit to control the instruction cycle, so the central processing unit performs the instruction cycle irregularly during the encryption operation.

As described above, in the present invention, since the instruction cycle does not occur with a certain rule, even if the same instruction is executed, the number of instruction cycles is different and the power consumption is also different.

Therefore, it is almost impossible for an unauthorized user to find repeated commands and correctly decipher KEY values through power analysis through external power pins.

In addition, the present invention proposes a control mechanism of a weight signal through an enable signal (Enable) in order to prevent the operation speed of the central processing unit from being reduced due to frequent weight states.

That is, the user makes the enable signal logic high during the encryption operation to prevent power analysis, and makes the enable signal logic low so that the weight state does not occur during normal operation.

In summary, the present invention randomizes the command cycle of the central processing unit to secure the encryption information of the smart card from monitoring through the power pin.

As described above, when the mechanism proposed in the present invention is applied to a smart card, even if an unauthorized user monitors an instruction cycle through a power pin, there is an advantage of stably securing encryption information of the smart card.

Claims (4)

A storage device for storing a predetermined password; An input / output register for outputting a reception and storage password of the input password and a comparison result of the input password; A random weight generator configured to output a weight signal for varying an instruction cycle according to a logic level of the input enable signal; And a central processing unit for instructing a comparison of a stored password and an input password and outputting a comparison result to the input / output register in synchronization with an instruction cycle varied by the weight signal. The method of claim 1, The random weight generator includes a random clock weight generator for generating a random clock pulse; And And a logic gate that inverts the random clock pulse when the input enable signal is logic high and fixes the logic level of the random clock pulse high when the input enable signal is logic high. The method of claim 2, And the logic gate comprises a NAND gate. The method according to claim 1 or 2, The random weight generator generates a no-weight signal when the enable signal is logic low to operate an instruction cycle normally, and generates a 1 to n weight signal when the enable signal is logic high to vary the instruction cycle. Smart card prevention device, characterized in that.