KR20020060340A - Method for testing a rambus memory - Google Patents

Abstract

PURPOSE: A method for testing a Rambus memory is provided, which realizes an environment causing noise to a channel, and realizes a specific memory signal under a mounted environment at will, and calculates an accurate memory position and memory access automatically when there is a fail. CONSTITUTION: According to the method for testing a Rambus memory device having a channel of a packet constituted in 8-burst type of 2 byte, 32-bit data of an equal pattern is written/read repetitively to/from all memories of the Rambus memory device. And upper 16 bits and lower 16 bits are exchanged complementarily, to be toggled as "01010101" on a time axis as to one data output pad.

Description

How to test rambus memory {METHOD FOR TESTING A RAMBUS MEMORY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a test method capable of testing a rambus memory according to a mounting environment.

There are many programs around the world that determine the performance of a system in the system environment. However, not many programs have been developed to suit their characteristics for memory-only testing. In particular, it is very difficult to fully test the characteristics of Rambus memory using memory test programs used in existing EDO / SDRAM. That is, development of a test program dedicated to Rambus is required. Rambus memory is implemented in the system in parallel with the Rambus channel. Since the sensitivity of the Rambus memory is very high, tools are needed to test the quality of the channel and the characteristics of the memory cell at the same time.

It is an object of the present invention to provide a test method that can implement an environment in which a lot of noise is caused on a channel.

Another object of the present invention is to provide a test method capable of freely implementing a specific memory signal in a mounting environment for determining memory characteristics.

It is yet another object of the present invention to provide a test method that can automatically calculate the correct memory location and memory access when a failure occurs.

1 shows a simultaneous switching noise signal implemented in accordance with the present invention; And

2 is a view showing a pattern input and output implemented according to the present invention.

(Configuration)

According to a feature of the present invention for achieving the above objects, a method of testing a Rambus memory device having a channel of packets configured in a 2-byte 8-burst form is identical to / from all memories of the Rambus memory device. Repeatedly writing / reading 32-bit data of the pattern; Complementarily swapping the upper 16 bits and the lower 16 bits so as to toggle to "01010101" on the time axis for one data output pad.

(Action)

According to this method, first, since an environment in which a lot of noise is caused to a channel can be implemented, a signal capable of applying sufficient stress to the Rambus channel can be implemented.

(Example)

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the drawings.

According to the novel test method of the present invention, since an environment in which a lot of noise is caused on a channel can be implemented first, a signal capable of applying sufficient stress to a Rambus channel can be implemented. Then, since a specific memory signal can be freely implemented in a mounting environment for determining memory characteristics, various patterns can be accurately implemented in a memory channel for memory testing. Finally, since the correct memory location and memory access can be calculated automatically when a failure occurs, the correct memory address and location can be automatically converted when a failure occurs for failure analysis. This will be described in detail on the basis of the reference drawings below.

First, the stress on the Rambus channel is as follows. Implementing a signal that can cause simultaneous simultaneous switching noise (SSN) can put enough stress on the channel and memory. The Rambus channel consists of one packet, and one packet consists of 16 bytes. It consists of 8 bursts of 2 bytes.

Accordingly, the signal capable of effectively determining the characteristics of the Rambus channel is implemented in that the signal is toggled in the form of “01010101”, thereby implementing a function pattern capable of driving the signal in a simultaneous switching noise environment. The input pattern is 32 bits and repeats reading / writing with the same pattern in all memories. At this time, it toggles to 01010101 on the time axis for one DQ by changing the upper 16 bits and the lower 16 bits complementarily. The test effect can be maximized by applying the extracted pattern complementarity function to the input pattern of the test function.

The method of implementing the intention pattern signal for the memory test is as follows. By analyzing the packets of the RAM bus memory by address, it generates a pattern corresponding to each address continuously to provide a useful environment for evaluating memory characteristics. The Rambus 1 packet consists of (32 bits * 4) the data pattern of the central processing unit. As a result of analyzing the address mapping of the central processing unit, the same output is displayed at the position corresponding to the unique address. That is, in one packet, the first column has a CPU address of -00h, the second column of -02h, and the third column of -04h, showing constant output in the order of the CPU addresses.

At this time, when a combination of addresses and patterns of one packet is calculated to operate a repetitive pattern when driving a CPU command, a constant pattern of a predetermined position can always be obtained from the memory. The CPU writes a predetermined area (larger than the cache size) into the memory in a desired pattern and reads the constant area (larger than the cache size) again to obtain a repetitive read cycle from the memory.

Here, since the input pattern can be precisely controlled for each position, a desired pattern can be obtained continuously. These tools can be used to accurately determine Rambus memory characteristics in the system and to selectively drive specific devices in the system by adjusting the CPU address area. By utilizing this, it provides an environment where the system can understand all the characteristics of each configuration.

The following is the method for automatic conversion when a failure occurs.

When a system fails during memory testing, it only outputs the address and pattern of the central processing unit, which does not know the exact device and location. Analysis of the address mapping of the central processing unit revealed that the memory area in the Rambus channel consists of a sequential sequence of Rambus configurations. When the address of the central processing unit is generated, the configuration information stored in the chipset (CHIPSET) In other words, the automatic conversion of the size and type as a memory address of the CPU address is implemented. The memory map is configured uniformly for each chipset, and is developed by developing and adding the following code that is converted into software.

0000 99-01-19 04:45:11 [Start] long run test

0500 99-01-19 04:47:51 Adjacent column Disturbance test: Error!

Error physical address = 057D9288h

Expected pattern data = EFEFEFEFh

Actual pattern data = EFEFEDEFh

Actual Group ID = 02h

Actual Device ID = 02h

Actual Bank address = 03h

Actual Row address = 006Fh

Actual Column Address = 0028h

0001 99-01-19 05:03:16 [End] long run test

As can be seen from this code, the CPU address indication and the exact location of the memory and the translation into the memory address can be implemented.

As described above, since an environment in which a lot of noise is caused to the channel can be implemented first, a signal capable of applying sufficient stress to the Rambus channel can be implemented. Then, since a specific memory signal can be freely implemented in a mounting environment for determining memory characteristics, various patterns can be accurately implemented in a memory channel for memory testing. Finally, since the correct memory location and memory access can be calculated automatically when a failure occurs, the correct memory address and location can be automatically converted when a failure occurs for failure analysis.

Claims (1)

A method of testing a Rambus memory device having a channel of packets configured in 2-byte 8-burst form: Repeatedly writing / reading 32-bit data of the same pattern into / from all memories of the Rambus memory device; Complementarily swapping the upper 16 bits and the lower 16 bits such that the one 16 data pads toggle on the time axis to "01010101".