KR20020058408A - Method for fabricating metal electrode with ruthenium - Google Patents
Method for fabricating metal electrode with ruthenium Download PDFInfo
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- KR20020058408A KR20020058408A KR1020000086512A KR20000086512A KR20020058408A KR 20020058408 A KR20020058408 A KR 20020058408A KR 1020000086512 A KR1020000086512 A KR 1020000086512A KR 20000086512 A KR20000086512 A KR 20000086512A KR 20020058408 A KR20020058408 A KR 20020058408A
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- thin film
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- 238000000034 method Methods 0.000 title claims abstract description 73
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 48
- 239000002184 metal Substances 0.000 title claims abstract description 48
- 229910052707 ruthenium Inorganic materials 0.000 title description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 title description 2
- 238000000151 deposition Methods 0.000 claims abstract description 31
- 230000008021 deposition Effects 0.000 claims abstract description 21
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 13
- 239000003990 capacitor Substances 0.000 claims abstract description 12
- 239000002243 precursor Substances 0.000 claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 10
- 239000007789 gas Substances 0.000 claims abstract description 9
- 239000006200 vaporizer Substances 0.000 claims abstract description 7
- 239000010409 thin film Substances 0.000 claims description 32
- 239000012495 reaction gas Substances 0.000 claims description 5
- 239000010408 film Substances 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 claims description 3
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000011065 in-situ storage Methods 0.000 abstract description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 230000003746 surface roughness Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000011534 incubation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
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- H01L28/65—
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H01L28/55—
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- General Chemical & Material Sciences (AREA)
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- Materials Engineering (AREA)
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- Manufacturing & Machinery (AREA)
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- Chemical Vapour Deposition (AREA)
Abstract
Description
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 DRAM 커패시터의 루테늄(Ru) 금속전극의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a ruthenium (Ru) metal electrode of a DRAM capacitor.
반도체소자의 고집적화에 따라 정보전하를 저장할 기억소자를 효율적으로 축소시키는 문제가 제기되었다. 그러나 커패시터가 차지하는 영역의 축소는 기억된정보의 유지를 위한 충분한 정전용량을 확보하는데 제약요소가 되며, α입자에 의한 소프트에러 및 잡음에 의한 정보전하를 유지하기 위해 기억소자의 축소에 관계없이 적정한 커패시터 정전용량을 확보해야 한다.The high integration of semiconductor devices has raised the problem of efficiently reducing the memory devices that store information charges. However, the reduction of the area occupied by the capacitor is a limiting factor in securing sufficient capacitance to maintain the stored information, and is appropriate regardless of the reduction of the memory element to maintain the information charge due to soft errors and noise by α particles. Capacitor capacitance must be ensured.
이를 실현하기 위해 C=εAs/d(ε:유전율, As:표면적, d:유전체 두께)와 같이 커패시터 유전체의 박막화로 전극간 거리(d)를 최소화하고, 커패시터구조를 3차원구조로 변화시켜 표면적(As) 증대를 추구하였다. 그러나 반도체 제조공정의 초미세화에 의해 커패시터의 구조적 개선을 통한 축소는 공정상의 한계에 이르러 더 이상의 축소가 불가능해져 이제는 기존 실리콘계열의 유전막이 아닌 Ta2O5, STO, BST, PZT등과 같은 고유전체막에 대한 개발의 필요성이 대두되게 되었고 현재 활발히 연구중이다. 이러한 고유전체물질은 전극으로 반도체 대신에 대부분 금속을 사용하는데 3차원 구조에서의 금속전극은 Ru, Ir, Pt 등과 같은 귀금속을 일반적인 열CVD공정을 이용하여 증착한다. 이러한 금속을 증착하는데 있어 금속박막의 두께 증가에 따른 증착특성의 변화 및 초기 잠복시간(Incubation time)에 의한 기판에 따른 증착특성의 변화로 도1과 같이 종래기술의 증착변수 연속성으로는 도2 내지 도11의 실험적 결과에서 보이는 바와 같이 항상 배치되는 특성을 가지고 있기 때문에 커패시터의 전극으로서 요구되는 조건인 증착속도가 높고, 결함 및 보이드가 없고 표면 거칠기가 양호하고 비저항율이 낮으며, 박막내에 산소함량이 적고 스텝커버리지가 양호한 특성을 충족시키지 못하는 문제점을 안고 있다.To realize this, thinning of the capacitor dielectric such as C = εAs / d (ε: dielectric constant, As: surface area, d: dielectric thickness) minimizes the distance between electrodes (d) and changes the capacitor structure to a three-dimensional structure. (As) sought to increase. However, due to the ultra miniaturization of the semiconductor manufacturing process, shrinkage through structural improvement of capacitors has reached the limit of the process and no further reduction is possible, and now it is not possible to reduce the shrinkage due to high dielectric films such as Ta2O5, STO, BST, and PZT. The need for development has emerged and is currently being actively researched. The high-k dielectric material uses most metals instead of semiconductors as electrodes, and metal electrodes in three-dimensional structures deposit precious metals such as Ru, Ir, Pt, etc. using a general thermal CVD process. In the deposition of such metals, the deposition characteristics of the substrate according to the change of the deposition characteristics according to the increase of the thickness of the metal thin film and the initial incubation time (Incubation time) as shown in FIG. As shown in the experimental results of FIG. 11, since it has a property of being always arranged, the deposition rate, which is a condition required for the electrode of the capacitor, is high, there are no defects and voids, the surface roughness is good, the resistivity is low, and the oxygen content in the thin film. There is a problem that there is little and step coverage does not satisfy a favorable characteristic.
본 발명은 상기 문제점을 해결하기 위한 것으로써, 반도체소자의 고집적화에 따라 요구되는 적당한 커패시턴스를 확보하기 위하여 높은 유전상수를 가지는 Ta2O5, STO, BST, PZT와 같은 물질을 사용하는데 있어서 이들 고유전체가 전극으로 사용하는 금속박막으로서 Ru박막을 ISSC(In-situ step changing) CVD방식으로 증착하여 금속전극을 형성함으로써 증착속도가 높고 결함 및 보이드가 없으며 표면거칠기가 양호하고 비저항율이 낮으며 박막내에 산소함유량이 적고 스텝커버리지가 양호한 특성의 금속전극을 얻을 수 있는 방법을 제공하는데 목적이 있다.The present invention is to solve the above problems, in order to secure the appropriate capacitance required by the high integration of semiconductor devices, in order to use a material such as Ta2O5, STO, BST, PZT having a high dielectric constant, these high dielectric constant electrode As a metal thin film, Ru thin film is deposited by ISSC (In-situ step changing) CVD method to form metal electrode, so that the deposition rate is high, there are no defects and voids, the surface roughness is good, the resistivity is low, and the oxygen content in the thin film It is an object of the present invention to provide a method for obtaining a metal electrode having a low step coverage and good characteristics.
도1은 종래기술에 의한 금속전극 증착방법을 도시한 도면.1 is a view showing a metal electrode deposition method according to the prior art.
도2 내지 도11은 종래기술에 의해 증착된 금속전극의 특성을 나타낸 도면.2 to 11 is a view showing the characteristics of the metal electrode deposited by the prior art.
도12는 본 발명에 의한 금속전극 증착방법을 도시한 도면.12 is a view showing a metal electrode deposition method according to the present invention.
도13은 본 발명의 구체적인 실시예에 의한 금속전극 증착방법을 도시한 도면.13 is a view showing a metal electrode deposition method according to a specific embodiment of the present invention.
도14는 본 발명의 금속전극 증착방법의 실험결과를 도시한 도면.14 shows experimental results of the metal electrode deposition method of the present invention.
상기 목적을 달성하기 위한 본 발명은, 유전막으로 고유전체를 사용하는 커패시터의 하부전극으로서 Ru금속박막을 형성하는 방법에 있어서, 공정변수의 크기를 단계적으로 변화시키는 CVD방식에 의해 Ru전구체를 사용하여 Ru금속박막을 증착하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a Ru metal thin film as a lower electrode of a capacitor using a high dielectric material as a dielectric film, using a Ru precursor by a CVD method to change the size of process variables step by step. It is characterized by depositing a Ru metal thin film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
본 발명은 유기금속 전구체인 Ru(od)3 및 Ru(etcp)2를 사용하여 커패시터의 전극으로 Ru금속박막을 증착하는 방법으로서, 도12에 나타낸 바와 같이 공정변수를 금속박막이 증착되는 시간동안 변화시키는 것으로, 이것을 ISSC CVD방식이라고 명명하기로 한다.The present invention is a method of depositing a thin Ru metal film to the electrode of the capacitor by using the organic metal precursors Ru (od) 3 and Ru (etcp) 2, as shown in Figure 12 during the time the metal thin film is deposited process parameters By changing, this is called ISSC CVD method.
도12의 a)스텝다운(step-down) 방식은 공정변수의 크기를 단계적으로 감소시키면서 증착하는 방법으로, 여기서 공정변수는 온도, 압력, 가스유량, 유기금속 전구체의 유량, 베이포라이저(vaporizer)의 온도, 반응가스 분압 등으로 이들 공정변수 중에 하나 이상을 사용한다.12 a) the step-down method is a method of depositing step by step while reducing the size of the process variable, where the process variables are temperature, pressure, gas flow rate, organometallic precursor flow rate, vaporizer (vaporizer) Temperature, reaction gas partial pressure, etc., one or more of these process variables are used.
b)스텝업(step-up)방식은 공정변수의 크기를 단계적으로 감소시키는 방법이고, c)스텝업/다운 방식은 금속전극 증착시 공정변수의 크기를 단계적으로 증가시킨 다음 감소시키는 방법이며, d)스텝다운/업 방식은 공정변수의 크기를 감소시킨 다음 증가시키는 방법으로 이들 방법을 선정하는 기준은 증착하고자 하는 금속박막에 요구되는 특성에 따라 변경될 수 있다.b) The step-up method is a method of gradually reducing the size of the process variable, c) The step-up / down method is a method of gradually increasing the size of the process variable and then decreasing it during metal electrode deposition. d) The step-down / up method is to reduce the size of process variables and then increase them. The criteria for selecting these methods can be changed according to the characteristics required for the metal thin film to be deposited.
금속박막에 요구되는 특성으로는 비저항율, 표면거칠기, 스텝커버리지, 산소함유량, 증착속도, 스트레스 등이다. 이들 특성이 양호한 금속박막을 얻기 위해서는 금속박막이 증착되는 기판의 종류에 따라 적용되는 가스의 종류 및 온도에 따라서 상기한 ISSC-CVD 방법 중의 한가지 방식을 적용해야 한다.Characteristics required for the metal thin film include resistivity, surface roughness, step coverage, oxygen content, deposition rate and stress. In order to obtain a metal thin film having good characteristics, one of the above-described ISSC-CVD methods should be applied according to the type and temperature of the gas applied according to the type of substrate on which the metal thin film is deposited.
Ru(od)3의 Ru전구체를 사용하여 Ru금속전극을 증착하는 방법으로 ISSC-CVD방법을 설명한다.The ISSC-CVD method is described by depositing a Ru metal electrode using a Ru precursor of Ru (od) 3.
증착온도 및 공정압력을 일정하게 유지하고 공정변수로서 반응가스인 O2/Ar+O2에 있어서의 O2의 비율을 조정하여 Ru금속박막을 증착한다. 도12의 b)스텝업 방식을 적용할 경우, 공정변수인 O2/Ar+O2에 있어서의 O2의 비율을 일정단계로 증가시키면서 증착하면(각 단계의 시간도 다르게 설정 가능함) 초기 Ru금속박막의산소함유량을 낮게 할 수 있어 하부기판의 산화정도를 줄일 수 있으며, 후에 O2비율의 증가에 따른 금소박막의 양호한 표면거칠기 및 스텝커버리지 특성을 얻을 수 있다. 다른 ISSC-CVD방식도 기판의 종류 및 요구되는 금속박막의 특성에 따라 적용될 수 있다.The Ru metal thin film is deposited by keeping the deposition temperature and the process pressure constant and adjusting the ratio of O2 in the reaction gas O2 / Ar + O2 as the process variable. In the case of applying the step-up method of FIG. 12, when the ratio of O2 in the process variable O2 / Ar + O2 is increased in a constant step (deposition can be set differently), The oxygen content can be lowered to reduce the degree of oxidation of the lower substrate, and the surface roughness and step coverage characteristics of the gold thin film can be obtained later by increasing the O2 ratio. Other ISSC-CVD methods may be applied depending on the type of substrate and the characteristics of the metal thin film required.
Ru금속박막을 ISSC-CVD방식에 의해 증착함에 있어서, 상기 공정변수들중 공정압력은 0.1Torr-10Torr 범위에서 사용하고, 증착온도는 200-500℃로 하는 것이 바람직하며, 공정가스로는 O2,N2O, NH3, Ar,N2, H2,He를 사용하되, 공정가스의 유량을 10sccm-3000sccm의 범위로 하는 것이 바람직하다. 또한 상기 베이포라이저의 온도는 50-350℃ 범위에서 사용하고, Ru전구체의 유량을 0.01ml/min-10ml/min 범위에서 사용하며, 반응가스의 분압은 5-90% 범위에서 사용하는 것이 바람직하다.In the deposition of Ru metal thin film by ISSC-CVD method, the process pressure among the above process variables is used in the range of 0.1 Torr-10 Torr, and the deposition temperature is preferably 200-500 ° C., and the process gas is O2, N2O. , NH3, Ar, N2, H2, He is used, but the flow rate of the process gas is preferably in the range of 10sccm-3000sccm. In addition, the temperature of the vaporizer is used in the range of 50-350 ℃, the flow rate of the Ru precursor is used in the range of 0.01ml / min-10ml / min, the partial pressure of the reaction gas is preferably used in the range of 5-90%. Do.
본 발명의 Ru금속전극 형성방법을 구체적인 실시예를 도13을 참조하여 설명하면 다음과 같다.A detailed embodiment of the Ru metal electrode formation method of the present invention will be described with reference to FIG.
ISSC-CVD방식중 스텝업방식으로 이용하여 Ru금속박막을 증착하는바, 공정변수중에서 증착온도를 스텝업 방식으로 증가시키면서 증착한다. 이 경우 단계별 조건을 다음과 같다.The Ru metal thin film is deposited using the step-up method of the ISSC-CVD method, and is deposited while increasing the deposition temperature in the step-up method among the process variables. In this case, the conditions are as follows.
1단계 : 260℃에서 5분간 증착Step 1: Deposit for 5 minutes at 260 ℃
2단계 : 280℃에서 10분간 증착Stage 2: Deposition at 280 ℃ for 10 minutes
3단계 : 340℃에서 5분간 증착Step 3: Deposit for 5 minutes at 340 ℃
공정압력 : 1Torr, O2 비율 : 10%, Ru소오스 : 0.2M Ru(od)3,4, 소오스유량 : 0.1mi/min, 베이포라이저 온도 : 225℃로 설정하였다.Process pressure: 1 Torr, O2 ratio: 10%, Ru source: 0.2M Ru (od) 3, 4, source flow rate: 0.1 mi / min, vaporizer temperature: 225 ℃ was set.
상기 공정에 의한 증착결과는 도14의 실험 데이타에서 보는 바와 같이 1단계에서 산소함유량이 낮고 표면거칠기가 양호한 박막을 형성한 후, 2단계에서 산소함유량이 상대적으로 높으나 증착속도가 빠르므로 원하는 박막두께를 증착한다. 3단계에서는 산소함유량을 줄이고 표면거칠기를 양호하게 한다.As shown in the experimental data of FIG. 14, the deposition result by the above process was carried out to form a thin film having a low oxygen content and a good surface roughness in the first step, and a desired thin film thickness because the oxygen content was relatively high in the second step but the deposition rate was fast. Deposit. In step 3, oxygen content is reduced and surface roughness is good.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 종래의 CVD기술과 달리 증착변수를 변경할 수 있는 ISSC-CVD방식으로 유기금속의 전구체인 Ru(od)3를 사용하여 Ru금속박막을 형성하는 방법으로, 전극으로서 요구되는 증착속도가 높으며 결함 및 보이드가 없고 표면거칠기가 양호하며, 비저항율이 낮고 박막내에 산소함유량이 적고 스텝커버리지가 양호한 특성을 얻을 수 있어 커패시터의 양호한 누설전류특성 및 높은 정전용량을 확보할 수 있다.The present invention is a method of forming a Ru metal thin film using Ru (od) 3, which is a precursor of an organic metal, in an ISSC-CVD method that can change deposition parameters, unlike a conventional CVD technique, and requires a high deposition rate as an electrode. It is free from defects and voids, has good surface roughness, low resistivity, low oxygen content in the thin film, and good step coverage, thereby ensuring good leakage current characteristics and high capacitance of the capacitor.
Claims (12)
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| KR1020000086512A KR20020058408A (en) | 2000-12-30 | 2000-12-30 | Method for fabricating metal electrode with ruthenium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100434489B1 (en) * | 2001-03-22 | 2004-06-05 | 삼성전자주식회사 | Method for depositing ruthenium layer having Ru02 seeding layer |
| KR100744664B1 (en) * | 2001-06-28 | 2007-08-02 | 주식회사 하이닉스반도체 | Method for forming of ruthenium by chemical vapor deposition |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR980006341A (en) * | 1996-06-27 | 1998-03-30 | 김주용 | Method for manufacturing capacitor of semiconductor device |
| KR19990057881A (en) * | 1997-12-30 | 1999-07-15 | 김영환 | Capacitor Formation Method of Semiconductor Device |
| JPH11238861A (en) * | 1998-02-23 | 1999-08-31 | Nec Corp | Thin film capacitor and manufacture thereof |
| KR100389913B1 (en) * | 1999-12-23 | 2003-07-04 | 삼성전자주식회사 | Forming method of Ru film using chemical vapor deposition with changing process conditions and Ru film formed thereby |
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2000
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR980006341A (en) * | 1996-06-27 | 1998-03-30 | 김주용 | Method for manufacturing capacitor of semiconductor device |
| KR19990057881A (en) * | 1997-12-30 | 1999-07-15 | 김영환 | Capacitor Formation Method of Semiconductor Device |
| JPH11238861A (en) * | 1998-02-23 | 1999-08-31 | Nec Corp | Thin film capacitor and manufacture thereof |
| KR100389913B1 (en) * | 1999-12-23 | 2003-07-04 | 삼성전자주식회사 | Forming method of Ru film using chemical vapor deposition with changing process conditions and Ru film formed thereby |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100434489B1 (en) * | 2001-03-22 | 2004-06-05 | 삼성전자주식회사 | Method for depositing ruthenium layer having Ru02 seeding layer |
| KR100744664B1 (en) * | 2001-06-28 | 2007-08-02 | 주식회사 하이닉스반도체 | Method for forming of ruthenium by chemical vapor deposition |
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