KR20020056204A - Post program verify circuit for flash memory device - Google Patents

Abstract

PURPOSE: A circuit for verifying a post program of a flash memory device is provided to obtain uniform distribution of threshold voltage of cells by switching a reference cell. CONSTITUTION: A sense amplifier(23) compares main cell voltage according to main cell current(Imain) with reference cell voltage(Vref) according to reference cell current(Iref) and outputs a compared result. The main cell current(Imain) flows into a main cell(21) through the first NMOS transistor(N21). The first NMOS transistor(N21) is driven by the first resistance(R21) and supply voltage(Vcc). The reference cell current(Iref) flows into a reference cell(22) through the second NMOS transistor(N22). The second NMOS transistor(N22) is driven by the second resistance(R22) and voltage(Vg) changed according to temperature of a thermal compensation circuit(24).

Description

Post program verify circuit for flash memory devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a post program verification circuit of a flash memory device. In particular, a post of a flash memory device capable of having a constant cell threshold voltage distribution regardless of a change in temperature after erasing by switching a reference cell using a temperature compensation circuit. It relates to a program verification circuit.

To erase the flash memory cells, pre-programming, erasing, and post-programming processes are performed. After each process, a verification process is performed. After the flash memory cell is erased, a post program is performed to raise a cell that has been erased in the erase process, that is, a cell whose erase threshold voltage is lowered to 0V or lower to a desired threshold voltage. That is, as a process of preventing current from flowing when the gate voltage is 0V or more, the threshold voltages of all cells are maintained at a constant level of about 2V.

In the conventional chip structure, a NOR cell structure is used to improve read speed, and a column structure in which 512 cells are connected is used. At this time, even if the gate voltage of all cells is applied to 0V after the post program is performed on the strings in which 512 cells are connected, the leakage current components of each cell are increased. This current increases further at high temperatures and causes a variety of problems due to the increase in current caused by the threshold voltage falling at high temperatures.

As shown in FIG. 1, the post-program verification circuit currently used includes a main cell voltage Vmain according to the main cell current Imain and a reference cell voltage Vref according to the reference cell current Iref. The output is compared with (Vout). The main cell current Imain is a current flowing to the main cell 11 through the first NMOS transistor N11 to which the power supply voltage Vcc is applied and driven by the first resistor R11 and the power supply voltage Vcc. The reference cell current Iref is a current flowing to the reference cell 12 through the second NMOS transistor N12 driven by the power supply voltage Vcc and driven by the second resistor R12 and the pumped constant voltage Vg. to be.

If the main voltage Vmain is greater than the reference voltage Vref, that is, if the main current Imain is less than the reference current Iref, it is determined that the post program is successful. For example, if the reference current Iref is 10 mA, the post program operation stops when a current of 10 mA or less flows in a column in which 512 cells are commonly bound.

However, since the reference cell current is increased at low temperatures when the pumped constant voltage Vg is applied, the post program threshold voltage at low temperatures is lower. This increases the leakage current and decreases the threshold voltage at high temperatures, resulting in a change in cell read margin and reduced program efficiency.

It is an object of the present invention to provide a post program verification circuit of a flash memory device in which a cell read margin does not change regardless of a change in temperature.

Another object of the present invention is to provide a post program verification circuit of a flash memory device capable of preventing a reduction of a read threshold voltage by changing a voltage for switching a reference cell according to a change in temperature.

1 is a post program verification circuit diagram of a conventional flash memory device.

2 is a post program verification circuit diagram of a flash memory device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

11 and 21: main cell 12 and 22: reference cell

13 and 23: sense amplifier 24: temperature compensation circuit

The present invention provides a first switching means for driving a first voltage to form a current path to a main cell, a second switching means for driving a second voltage to form a current path to a reference cell, and the main cell. A post program verification circuit of a flash memory device comprising a sense amplifier for comparing a main cell voltage by a current and a reference cell voltage by a reference cell current, wherein the second voltage is connected between a power supply terminal and a first node. A first PMOS transistor connected between a first diode and the power supply terminal and a second node and driven according to a potential of the first node, a second diode connected in parallel with the first PMOS transistor, and the power supply terminal; A second PMOS transistor connected between a third node and driven according to a potential of the first node, and between the first node and a ground terminal A third NMOS transistor driven according to the potential of the second node and a first resistor connected in series thereto, a third diode connected between the second node and the ground terminal, and between the third node and the ground terminal And a second resistor connected to the output circuit, and output from a temperature compensation circuit for outputting a voltage that changes with temperature.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

FIG. 2 is a circuit diagram of a post program verification circuit of a flash memory device according to an exemplary embodiment of the present invention, and outputs a voltage Vg for switching a reference cell to a general post program verification circuit from a temperature compensation circuit in which the voltage changes with a change in temperature. .

The main cell voltage Vmain according to the main cell current Imain and the reference cell voltage Vref according to the reference cell current Iref are compared in the sense amplifier 23 to output Vout. The main cell current Imain is a current flowing to the main cell 21 through the first NMOS transistor N21 to which the power supply voltage Vcc is applied and driven by the first resistor R21 and the power supply voltage Vcc. The reference cell current Iref is a second NMOS transistor N22 driven by a voltage Vg applied with a power supply voltage Vcc and changing according to a temperature output from the second resistor R22 and the temperature compensation circuit 24. Current flowing through the reference cell 22.

The configuration of the temperature compensation circuit 24 is as follows.

The first PMOS transistor P21, which operates as a diode, is connected between the power supply terminal Vcc and the first node Q21. A second PMOS transistor P22 driven according to the potential of the first node Q21 is connected between the power supply terminal Vcc and the second node Q22, and a third PMOS transistor P23 operated by a diode is connected. do. A fourth PMOS transistor P24 driven according to the potential of the first node Q21 is connected between the power supply terminal Vcc and the third node Q23. A third NMOS transistor N23 and a third resistor R23 are connected in series between the first node Q21 and the ground terminal Vss according to the potential of the second node Q22. A fourth NMOS transistor N24 operated by a diode is connected between the second node Q22 and the ground terminal Vss. The fourth resistor R24 is connected between the third node Q23 and the ground terminal Vss.

The temperature compensation circuit configured as described above increases the output voltage as the temperature increases. The mobility of the current flowing through the fourth PMOS transistor P24 becomes a function of 1 / μ, which increases the voltage as the temperature increases.

The temperature compensation circuit operates only when performing a post program verification operation to generate an appropriate voltage Vg according to the temperature to generate a reference voltage of the sense amplifier. That is, when the temperature decreases by using a circuit that increases the voltage for switching the reference cell according to the temperature, the reference cell current is decreased to increase the threshold voltage of the main cell where post program verification is successful at low temperature. have.

As a result, the threshold voltage of the main cell is raised so that the threshold voltage does not become 0V or less at high temperatures, thereby improving read margins at high temperatures and increasing program efficiency.

As described above, according to the present invention, a post program verification operation of a flash memory device is performed by correcting temperature characteristics to improve cell distribution according to temperature, thereby improving read efficiency and program efficiency at high temperature, thereby improving device efficiency. have.

Claims (1)

First switching means for driving a first voltage to form a current path to the main cell, second switching means for driving a second voltage to form a current path to the reference cell, and the main cell current A post program verification circuit of a flash memory device comprising a sense amplifier for comparing a main cell voltage and a reference cell voltage by the reference cell current, The second voltage includes a first diode connected between a power supply terminal and a first node; A first PMOS transistor connected between the power supply terminal and a second node and driven according to a potential of the first node; A second diode connected in parallel with the first PMOS transistor; A second PMOS transistor connected between the power supply terminal and a third node and driven according to a potential of the first node; A third NMOS transistor driven according to the potential of the second node between the first node and the ground terminal and a first resistor connected in series thereto; A third diode connected between the second node and the ground terminal; And a second resistor connected between the third node and the ground terminal to be output from a temperature compensating circuit for generating a voltage that varies with temperature.