KR20020056153A - Electrostatic discharge device - Google Patents

Electrostatic discharge device Download PDF

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KR20020056153A
KR20020056153A KR1020000085462A KR20000085462A KR20020056153A KR 20020056153 A KR20020056153 A KR 20020056153A KR 1020000085462 A KR1020000085462 A KR 1020000085462A KR 20000085462 A KR20000085462 A KR 20000085462A KR 20020056153 A KR20020056153 A KR 20020056153A
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South Korea
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field oxide
well region
junction part
gate
source junction
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KR1020000085462A
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Korean (ko)
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심성보
유영선
장윤수
이문화
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박종섭
주식회사 하이닉스반도체
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Priority to KR1020000085462A priority Critical patent/KR20020056153A/en
Publication of KR20020056153A publication Critical patent/KR20020056153A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/762—Charge transfer devices
    • H01L29/765—Charge-coupled devices
    • H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
    • H01L29/76866—Surface Channel CCD
    • H01L29/76891—Four-Phase CCD

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: An electrostatic discharge(ESD) protection device is provided to improve a characteristic of an ESD input circuit, by forming a poly gate of a field transistor structure so that the threshold voltage of a field transistor is reduced to decrease the breakdown voltage of a drain junction part and a snap-back voltage. CONSTITUTION: The first and second field oxide layers(12A,12B) are formed in a semiconductor substrate having a P-well region(11). The first source junction part(13A) and the first drain junction part(14A) are formed in the P-well region at both sides of the first field oxide layer. The second source junction part(13B) and the second drain junction part(14B) are formed in the P-well region at both sides of the second field oxide layer. The first pickup region(15A) is formed in the P-well region adjacent to the first source junction part. The second pickup region(15B) is formed in the P-well region adjacent to the second source junction part. The first gate(16A) is formed on the first field oxide layer and the second gate(16B) is formed on the second field oxide layer.

Description

정전기 방지소자{Electrostatic discharge device}Electrostatic Discharge Device

본 발명은 정전기 방지소자에 관한 것으로서, 특히 필드 트랜지스터구조에 폴리 게이트를 형성함으로써, 필드 트랜지스터의 문턱전압(Vt)을 낮추어 드레인접합부의 항복전압을 낮춤과 아울러 스냅-백 전압이 낮아져 ESD 입력 회로의 특성을 개선할 수 있는 정전기 방지소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an antistatic device, and in particular, by forming a poly gate in a field transistor structure, the threshold voltage (Vt) of the field transistor is lowered, the breakdown voltage of the drain junction portion is lowered, and the snap-back voltage is lowered. The present invention relates to an antistatic device capable of improving characteristics.

일반적으로 메모리 소자의 특성을 결정할 때 중요한 것 중 하나가 정전기 방지(Electrostatic Discharge; 이하 "ESD"라 함)소자이다. 정전기 보호능력의 시험 방법은 인체에서 발생되는 정전기를 모델(Model)화한 인체 모델(Human body model)과 반도체 소자가 머신(Machine)에 장착되었을 때 발생되는 정전기를 모델화한 머신 모델(Machine model)로 구분되게 된다. 이는 측정 방법에 따라 전원전압 모드(Vcc mode), 접지전압 모드(Vss mode) 및 핀 간 모드(Pin to pin mode)로 세분되게 된다.In general, one of the important things in determining the characteristics of a memory device is an electrostatic discharge (hereinafter referred to as "ESD"). The test method of the electrostatic protection capability is a human body model that models the static electricity generated in the human body and a machine model that models the static electricity generated when the semiconductor device is mounted in the machine. Will be distinguished. This is subdivided into a power supply mode (Vcc mode), a ground voltage mode (Vss mode) and a pin to pin mode according to the measurement method.

이러한 각 모드에 의해 발생되는 정전기를 해소하기 위해 종래의 ESD 입력 구조에는 스트레스(stress)에 따라 VCC+ 재핑모드(zapping mode), VCC- 재핑모드, VSS+ 재핑모드 및 VSS- 재핑모드와 같이 4가지 모드(mode)가 있다.To eliminate the static electricity generated by each of these modes, the conventional ESD input structure has four modes, such as VCC + zapping mode, VCC- zapping mode, VSS + zapping mode, and VSS- zapping mode, depending on stress. There is (mode).

VCC+ 재핑모드는 개별 입력 패드(input pad)에 포지티브(+) 바이어스(positive bias)가 재핑됨과 아울러 VCC 단자에 접지(GND) 전원이 인가된다. VCC- 재핑모드는 개별 입력 패드에 네가티브(-)(negative) 바이어스가 재핑됨과 아울러 VCC 단자에 접지전원이 인가된다. VSS+ 재핑모드는 개별 입력 패드에 포지티브(+) 바이어스가 재핑됨과 아울러 VSS 단자에 접지전원이 인가된다. VSS- 재핑모드는 개별 입력 패드에 네가티브(-) 바이어스가 재핑됨과 아울러 VSS 단자에 접지전원이 인가된다.In the VCC + zapping mode, a positive bias is zaped to an individual input pad and a ground (GND) power is applied to the VCC terminal. In the VCC-zapping mode, negative bias is zaped to individual input pads, and ground power is applied to the VCC terminal. In the VSS + zapping mode, a positive bias is zaped on individual input pads, and a ground supply is applied to the VSS terminal. In the VSS-zapping mode, negative bias is zaped on individual input pads, and ground supply is applied to the VSS terminal.

이중, VCC+ 재핑모드의 구동특성을 도 1을 결부하여 설명하면, 도 1과 같다. 여기서, 도 1은 VCC+ 재핑모드를 적용한 필드 트랜지스터(field transistor)의 단면도이다.Among these, the driving characteristics of the VCC + zapping mode will be described with reference to FIG. 1. 1 is a cross-sectional view of a field transistor to which the VCC + zapping mode is applied.

도 1을 참조하면, 필드 트랜지스터는 반도체 기판 상부에 형성된 P-웰(1)영역과, P-웰(1) 상에 게이트로 동작되기 위해 형성된 제 1 및 제 2 필드산화막(2A,2B)와, 제 1 필드산화막(2A)를 경계로 P-웰(1) 상에 형성되는 제 1 소스접합부(3A) 및 제 2 드레인접합부(4A)와, 제 2 필드산화막(2B)를 경계로 P-웰영역 상에 형성되는 제 2 소스접합부(3B) 및 제 2 드레인접합부(4B)와, 제 1 소스접합부(3A)와 인접한 P-웰(1) 상에 형성되는 제 1 픽업영역(VSS pick-up; 5A)과, 제 2 소스접합부(3B)와 인접한 P-웰(1) 상에 형성되는 제 2 픽업영역(5B)으로 구성된다.Referring to FIG. 1, a field transistor includes a P-well 1 region formed on a semiconductor substrate, first and second field oxide films 2A and 2B formed to operate as a gate on the P-well 1, and And the first source junction 3A and the second drain junction 4A formed on the P-well 1 on the basis of the first field oxide film 2A and the second field oxide film 2B on the P-well 1. The second source junction 3B and the second drain junction 4B formed on the well region, and the first pick-up region VSS pick-up formed on the P-well 1 adjacent to the first source junction 3A. up 5A and a second pickup region 5B formed on the P-well 1 adjacent to the second source junction 3B.

제 1 및 제 2 소스접합부(3A,3B) 및 제 1 및 제 2 드레인접합부(4A,4B)은 N+불순물 이온 주입 공정에 의해 이온 도핑되어 형성됨과 아울러 제 1 및 제 2 픽업영역(5A,5B)는 P+불순물 이온 주입 공정으로 이온 도핑되어 형성된다.The first and second source junctions 3A and 3B and the first and second drain junctions 4A and 4B are ion-doped by an N + impurity ion implantation process, and the first and second pickup regions 5A, 5B) is formed by ion doping in a P + impurity ion implantation process.

또한, 제 1 소스접합부(3A) 및 제 1 픽업영역(5A)은 VSS 단자에 접속되고, 제 1 및 제 2 드레인접합부(4A,4B)는 패드(PAD)와 접속됨과 아울러 제 2 소스접합부(3A)는 VCC 단자와 접속된다.Further, the first source junction 3A and the first pick-up region 5A are connected to the VSS terminal, and the first and second drain junction portions 4A and 4B are connected to the pad PAD and the second source junction portion (A). 3A) is connected to the VCC terminal.

이와 같이 구성된 필드 트랜지스터에 VCC+ 재핑모드를 적용한 구동 특성을 설명하면, 우선, 패드(PAD)에 소정의 하이(high) 포지티브 바이어스가 재핑되면, 패드(PAD)를 경유하여 제 2 드레인접합부(4B)에 하이 포지티브 바이어스가 인가된다. 이 하이 포지티브 바이어스에 의해 제 2 드레인접합부(4B)에 항복(break down)현상이 일어남과 아울러 제 2 소스접합부(3B)에서 제 2 드레인접합부(4B)쪽으로 스냅-백(snap-back)이 일어나 도시된 점선방향으로 전자가 이동하여 방전(discharge)하게 된다.Referring to the driving characteristics in which the VCC + zapping mode is applied to the field transistor configured as described above, first, when a predetermined high positive bias is zaped to the pad PAD, the second drain junction 4B is passed through the pad PAD. A high positive bias is applied to the. This high positive bias causes break down in the second drain junction 4B and snap-back from the second source junction 3B toward the second drain junction 4B. The electrons move and discharge in the dotted line.

전술한 바와 같이, 종래 기술에 따른 VCC+ 재핑모드를 적용한 필드 트랜지스터는 정전기에 의해 발생된 소정의 전자를 방전하기 위해 드레인접합부의 항복현상을 이용한 스냅-백에 의해 전자를 방전하게 된다.As described above, the field transistor applying the VCC + zapping mode according to the related art discharges electrons by snap-back using the breakdown phenomenon of the drain junction to discharge predetermined electrons generated by static electricity.

그러나, 드레인접합부에 항복현상을 일으키기 위해서는 충분히 큰 항복전압이 걸려야 한다. 이런 큰 항복전압으로 인해 드레인접합부가 손상되게 되는 문제가 발생하게 된다.However, in order to cause breakdown in the drain junction, a sufficiently large breakdown voltage must be applied. This large breakdown voltage causes a problem that the drain junction is damaged.

또한, 패드부로 인가되는 정전 전류가 드레인접합부의 항복전압 이하로 인가될 경우에는 드레인접합부의 항복 현상이 일어나지 않아 트렌지스터의 방전이 일어나지 않는 문제가 발생하게 된다.In addition, when the electrostatic current applied to the pad portion is applied below the breakdown voltage of the drain junction portion, a breakdown phenomenon of the drain junction portion does not occur, thereby causing a problem in that the discharge of the transistor does not occur.

따라서, 본 발명은 필드 트랜지스터구조의 ESD 입력 회로의 특성을 개선하기 위한 정전기 방지소자를 제공함에 있다.Accordingly, the present invention provides an antistatic device for improving the characteristics of an ESD input circuit of a field transistor structure.

본 발명의 또 다른 목적은 필드 트랜지스터구조에 폴리 게이트(poly gate)를 형성함으로써, 필드 트랜지스터의 문턱전압(Vt)을 낮추어 드레인접합부의 항복전압을 낮춤과 아울러 스냅-백 전압이 낮아져 ESD 입력 회로의 특성을 개선할 수 있는 정전기 방지소자를 제공함에 있다.Another object of the present invention is to form a poly gate in the field transistor structure, thereby lowering the threshold voltage (Vt) of the field transistor to lower the breakdown voltage of the drain junction portion and lower the snap-back voltage of the ESD input circuit. It is to provide an antistatic device that can improve the characteristics.

도 1은 종래 기술에 따른 정전기 방지소자를 설명하기 위해 도시한 반도체 소자의 단면도.1 is a cross-sectional view of a semiconductor device shown for explaining the antistatic device according to the prior art.

도 2는 본 발명의 일 실시예에 따른 정전기 방지소자를 설명하기 위해 도시한 반도체 소자의 단면도.Figure 2 is a cross-sectional view of a semiconductor device shown for explaining an antistatic device according to an embodiment of the present invention.

도 3은 본 발명의 또 다른 실시예에 따른 정전기 방지소자를 설명하기 위해 도시한 반도체 소자의 단면도.Figure 3 is a cross-sectional view of a semiconductor device shown for explaining an antistatic device according to another embodiment of the present invention.

도 4는 종래 기술과 본 발명의 정전기 방지소자를 비교하기 위한 스냅-백 전압을 도시한 특성 그래프.4 is a characteristic graph showing a snap-back voltage for comparing the antistatic element of the prior art with the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

1,11 : P-웰 영역 2A,12A : 제 1 필드산화막1,11: P-well region 2A, 12A: first field oxide film

2B,12B: 제 2 필드산화막 3A,13A : 제 1 소스접합부2B, 12B: second field oxide film 3A, 13A: first source junction

3B,13B : 제 2 소스접합부 4A,14A : 제 1 드레인접합부3B, 13B: second source junction 4A, 14A: first drain junction

4B,14B : 제 2 드레인접합부 5A,15A : 제 1 픽업영역4B, 14B: second drain junction 5A, 15A: first pick-up area

5B,15B : 제 2 픽업영역 16A : 제 1 게이트부5B, 15B: second pickup area 16A: first gate portion

16B : 제 2 게이트부16B: second gate portion

본 발명은 P-웰 영역이 형성된 반도체 기판에 형성되는 제 1 및 제 2 필드산화막과; 상기 제 1 필드산화막을 경계로 상기 P-웰 영역에 형성되는 제 1 소스접합부 및 제 2 드레인접합부와; 상기 제 2 필드산화막을 경계로 상기 P-웰 영역에 형성되는 제 2 소스접합부 및 제 2 드레인접합부와; 상기 제 1 소스접합부와 인접한 상기 P-웰 영역에 형성되는 제 1 픽업영역 및 상기 제 2 소스접합부와 인접한 상기 P-웰 영역에 형성되는 제 2 픽업영역과; 상기 제 1 필드산화막 상부에 형성되는 제 1 게이트부 및 상기 제 2 필드산화막 상부에 형성되는 제 2 게이트부를 구비한다.The present invention provides a semiconductor device comprising: first and second field oxide films formed on a semiconductor substrate on which a P-well region is formed; A first source junction and a second drain junction formed in the P-well region bordering the first field oxide film; A second source junction part and a second drain junction part formed in the P-well region with the second field oxide layer as a boundary; A first pickup region formed in the P-well region adjacent to the first source junction and a second pickup region formed in the P-well region adjacent to the second source junction; And a first gate portion formed on the first field oxide layer and a second gate portion formed on the second field oxide layer.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2은 본 발명의 일 실시예에 따른 정전기 방지소자를 설명하기 위해 순서적으로 도시한 반도체 소자의 단면도이다.2 is a cross-sectional view of a semiconductor device sequentially illustrated to illustrate an antistatic device according to an embodiment of the present invention.

도 2를 참조하면, 우선, 필드 트랜지스터는 반도체 기판 상부에 형성된 P-웰(11)영역과, P-웰(11)영역에 형성된 제 1 및 제 2 필드산화막(12A,12B)과, 제 1 필드산화막(12A)를 경계로 P-웰(11)영역에 형성되는 제 1 소스접합부(13A) 및 제 2 드레인접합부(14A)와, 제 2 필드산화막(12B)를 경계로 P-웰(11)영역에 형성되는 제 2 소스접합부(13B) 및 제 2 드레인접합부(14B)와, 제 1 소스접합부(13A)와 인접한 P-웰(11)영역에 형성되는 제 1 픽업영역(VSS pick-up; 15A)과, 제 2 소스접합부(13B)와 인접한 P-웰(1)영역에 형성되는 제 2 픽업영역(15B)와, 제 1 필드산화막(12A) 상부에 형성되는 제 1 게이트부(16A)와, 제 2 필드산화막(12B) 상부에 형성되는 제 2 게이트부(16B)로 구성된다.Referring to FIG. 2, first, a field transistor includes a P-well 11 region formed on an upper surface of a semiconductor substrate, first and second field oxide films 12A and 12B formed in the P-well 11 region, and a first P-well 11 bordering the field oxide film 12A and the first source junction 13A and the second drain junction 14A formed in the region of the P-well 11 and the second field oxide film 12B. First pick-up area VSS pick-up formed in the second source junction 13B and second drain junction 14B formed in the region, and the P-well 11 region adjacent to the first source junction 13A. 15A, the second pick-up region 15B formed in the P-well 1 region adjacent to the second source junction 13B, and the first gate portion 16A formed on the first field oxide film 12A. ) And a second gate portion 16B formed over the second field oxide film 12B.

제 1 및 제 2 소스접합부(13A,13B) 및 제 1 및 제 2 드레인접합부(14A,14B)는 N+불순물 이온 주입 공정에 의해 이온 도핑되어 형성됨과 아울러 제 1 및 제 2 픽업영역(15A,15B)는 P+불순물 이온 주입 공정으로 이온 도핑되어 형성된다.The first and second source junctions 13A and 13B and the first and second drain junctions 14A and 14B are formed by ion doping by an N + impurity ion implantation process and the first and second pickup regions 15A and 13A. 15B) is formed by ion doping in a P + impurity ion implantation process.

제 1 및 2 게이트부(16A,16B)는 셀 영역에 형성되는 2개의 폴리층과 함께 동시에 형성된다. 일반적으로, 스택 게이트 플래쉬 EEPROM의 경우 보통 2개의 폴리층이 형성되는데, 그 중, 제 1 폴리층은 플로팅 게이트로 사용되고 제 2 폴리층은 컨트롤 게이트로 사용된다. 즉, 제 1 및 2 게이트부(16A,16B)는 전술한 플로팅 게이트로 동작되기 위한 제 1 폴리층 형성공정시 함께 형성되거나, 컨트롤 게이트로 동작되기 위한 제 2 폴리층 형성공정시 함께 형성된다.The first and second gate portions 16A and 16B are formed simultaneously with two poly layers formed in the cell region. In general, in the case of a stack gate flash EEPROM, two poly layers are usually formed, wherein a first poly layer is used as a floating gate and a second poly layer is used as a control gate. That is, the first and second gate portions 16A and 16B are formed together in the first polylayer forming process for operating as the above-described floating gate or together in the second polylayer forming process for operating as the control gate.

여기서, 제 1 및 제 2 게이트부(16A,16B)는 도 3에 도시된 바와 같이, 제 1 및 2 필드산화막(12A,12B)의 소정 영역을 식각하여 그 부위를 메우도록 형성될 수 도 있다.Here, the first and second gate portions 16A and 16B may be formed to etch predetermined regions of the first and second field oxide films 12A and 12B to fill the portions, as shown in FIG. 3. .

또한, 제 1 소스접합부(13A) 및 제 1 픽업영역(15A)은 VSS 단자에 접속되고, 제 1 및 제 2 드레인접합부(14A,14B)와 제 1 및 제 2 게이트부(16A,16B)는 패드(PAD)와 접속됨과 아울러 제 2 소스접합부(13B)는 VCC 단자와 접속된다.In addition, the first source junction 13A and the first pickup region 15A are connected to the VSS terminal, and the first and second drain junction portions 14A and 14B and the first and second gate portions 16A and 16B are connected to each other. In addition to being connected to the pad PAD, the second source junction 13B is connected to the VCC terminal.

이와 같이 구성된 필드 트랜지스터에 VCC+ 재핑모드를 적용한 구동 특성을 설명하면, 우선, 패드(PAD)에 소정의 하이(high) 포지티브 바이어스가 재핑되면, 패드(PAD)를 경유하여 제 2 드레인접합부(14B) 및 제 2 게이트부(16B)에 하이 포지티브 바이어스가 인가된다. 이 하이 포지티브 바이어스에 의해 제 2 드레인접합부(14B)에 소정의 전하가 충전(charge)됨과 아울러 제 2 게이트부(16B)의 하부에 형성된 제 2 필드산화막(12B)에 소정의 전하가 충전된다. 즉, 하이 포지티브 바이어스에 의해 제 2 드레인접합부(14B)에 소정 이상의 전하가 충전됨과 아울러 제 2 필드산화막(12B)의 소정 영역에 충전된 전하에 의해 제 2 드레인접합부(14B)와 제 2 소스접합부(13B)간에 채널이 형성된다. 이어서, 제 2 드레인접합부(14B)에 충전된 전하에 의해 제 2 드레인접합부(14B)에서 항복현상이 일어남과 아울러 스냅-백이 발생하여 제 2 소스접합부(14B)와 제 2 드레인접합부(14A)간에 형성된채널을 따라 전자가 점선 방향으로 방전을 하게 된다.Referring to the driving characteristics in which the VCC + zapping mode is applied to the field transistor configured as described above, first, when a predetermined high positive bias is zaped to the pad PAD, the second drain junction 14B is passed through the pad PAD. And a high positive bias is applied to the second gate portion 16B. Due to this high positive bias, a predetermined charge is charged in the second drain junction portion 14B, and a predetermined charge is charged in the second field oxide film 12B formed under the second gate portion 16B. That is, the second drain junction 14B and the second source junction part are charged with a predetermined or more charge in the second drain junction 14B by the high positive bias and charged in a predetermined region of the second field oxide film 12B. A channel is formed between the 13Bs. Subsequently, a yield phenomenon occurs in the second drain junction 14B and a snap-back occurs due to the charge charged in the second drain junction 14B, so that the second source junction 14B and the second drain junction 14A are separated. The electrons discharge along the formed channel in the dotted line direction.

전술한 바와 같이, 본 발명은 제 1 및 제 2 필드산화막 상부에 제 1 및 제 2 게이트부를 형성함으로써, 트랜지스터의 방전율을 개선할 수 있다.As described above, the present invention can improve the discharge rate of the transistor by forming the first and second gate portions on the first and second field oxide films.

즉, 도 4에 도시된 바와 같이, 종래 기술에 따른 정전기 방지회로를 사용할 경우에는 "V1"이 스냅-백 전압이 되고, 본 발명에 따른 필드 트랜지스터를 사용할 경우에는 스냅-백 전압이 "V2"로 낮아져 방전이 용이하게 되고 결과적으로 입력 패드의 특성을 강화시키게 된다.That is, as shown in FIG. 4, when using the antistatic circuit according to the prior art, "V1" becomes the snap-back voltage, and when using the field transistor according to the present invention, the snap-back voltage is "V2". It is lowered to facilitate discharge and consequently to enhance the characteristics of the input pad.

상술한 바와 같이, 본 발명은 필드 트랜지스터구조에 폴리 게이트를 형성함으로써, 필드 트랜지스터의 문턱전압(Vt)을 낮추어 드레인접합부의 항복전압을 낮춤과 아울러 스냅-백 전압이 낮아져 ESD 입력 회로의 특성을 개선할 수 있다.As described above, the present invention forms a poly gate in the field transistor structure, thereby lowering the threshold voltage (Vt) of the field transistor, thereby lowering the breakdown voltage of the drain junction portion, and lowering the snap-back voltage, thereby improving the characteristics of the ESD input circuit. can do.

Claims (2)

P-웰 영역이 형성된 반도체 기판에 형성되는 제 1 및 제 2 필드산화막과;First and second field oxide films formed on the semiconductor substrate on which the P-well region is formed; 상기 제 1 필드산화막을 경계로 상기 P-웰 영역에 형성되는 제 1 소스접합부 및 제 2 드레인접합부와;A first source junction and a second drain junction formed in the P-well region bordering the first field oxide film; 상기 제 2 필드산화막을 경계로 상기 P-웰 영역에 형성되는 제 2 소스접합부 및 제 2 드레인접합부와;A second source junction part and a second drain junction part formed in the P-well region with the second field oxide layer as a boundary; 상기 제 1 소스접합부와 인접한 상기 P-웰 영역에 형성되는 제 1 픽업영역 및 상기 제 2 소스접합부와 인접한 상기 P-웰 영역에 형성되는 제 2 픽업영역과;A first pickup region formed in the P-well region adjacent to the first source junction and a second pickup region formed in the P-well region adjacent to the second source junction; 상기 제 1 필드산화막 상부에 형성되는 제 1 게이트부 및 상기 제 2 필드산화막 상부에 형성되는 제 2 게이트부를 구비하는 것을 특징으로 하는 정전기 방지소자.And a second gate portion formed over the first field oxide layer and a second gate portion formed over the second field oxide layer. 제 1 항에 있어서,The method of claim 1, 상기 제 1 게이트부는 상기 제 1 필드산화막의 소정 부위가 식각된 후, 그 부위를 덮도록 형성됨과 아울러 제 2 게이트부는 상기 제 2 필드산화막의 소정 부위가 식각된 후, 그 부위를 덮도록 형성되는 것을 특징으로 하는 정전기 방지소자.The first gate portion is formed to cover the portion after the predetermined portion of the first field oxide film is etched, and the second gate portion is formed to cover the portion after the predetermined portion of the second field oxide film is etched. Antistatic element, characterized in that.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100781487B1 (en) * 2006-07-18 2007-12-03 문학범 Over-voltage chip protector with high surge capability and fast response time

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100781487B1 (en) * 2006-07-18 2007-12-03 문학범 Over-voltage chip protector with high surge capability and fast response time

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