KR20020055990A - Method for Fabricating Thin Film Transistor of Poly Silicon Type - Google Patents
Method for Fabricating Thin Film Transistor of Poly Silicon Type Download PDFInfo
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- KR20020055990A KR20020055990A KR1020000085269A KR20000085269A KR20020055990A KR 20020055990 A KR20020055990 A KR 20020055990A KR 1020000085269 A KR1020000085269 A KR 1020000085269A KR 20000085269 A KR20000085269 A KR 20000085269A KR 20020055990 A KR20020055990 A KR 20020055990A
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- 239000010409 thin film Substances 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims description 19
- 229920005591 polysilicon Polymers 0.000 title claims description 16
- 239000010410 layer Substances 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims description 48
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 238000001312 dry etching Methods 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 8
- 239000007769 metal material Substances 0.000 claims description 5
- 238000009413 insulation Methods 0.000 abstract 6
- 239000004973 liquid crystal related substance Substances 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 239000011810 insulating material Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000002950 deficient Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 210000002858 crystal cell Anatomy 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Abstract
Description
본 발명은 폴리실리콘형 박막트랜지스터 제조방법에 관한 것이다. 특히, 게이트전극 패턴 시 발생하는 스텝 커버리지 불량으로 인해 그 상에 형성되는 금속물질의 단선 불량을 제거하여 불량율을 최소화하는 폴리실리콘형 박막트랜지스터 제조방법에 관한 것이다.The present invention relates to a polysilicon thin film transistor manufacturing method. In particular, the present invention relates to a method for manufacturing a polysilicon thin film transistor which minimizes a defective rate by removing a disconnection defect of a metal material formed thereon due to poor step coverage that occurs during a gate electrode pattern.
통상, 박막트랜지스터는 집적화 및 제조가 용이하여 반도체 메모리 및 액정표시장치 등에 주로 사용되고 있다. 이 박막트랜지스터는 사용될 회로장치에 따라 고온 또는 저온에서 제조된다. 예를 들어, 반도체 메모리에 사용될 경우 박막트랜지스터는 고온에서 제조되고 액정표시장치에 사용될 경우에는 저온에서 제조된다. 액정표시장치에 사용되는 박막트랜지스터가 저온에서 제조되는 이유는 유리기판이 주위온도에 의해 쉽게 변형되기 때문이다. 비디오신호에 따라 액정셀들의 광투과율을 조절함으로써 화상을 표시하는 액정표시소자는 액정셀들을 스위칭하는 소자로 박막트랜지스터를 이용하고 있다.In general, thin film transistors are used in semiconductor memories, liquid crystal displays, etc. because they are easy to integrate and manufacture. This thin film transistor is manufactured at high or low temperature depending on the circuit arrangement to be used. For example, thin film transistors are used at high temperatures when used in semiconductor memories and at low temperatures when used in liquid crystal displays. The reason why the thin film transistor used in the liquid crystal display device is manufactured at low temperature is that the glass substrate is easily deformed by the ambient temperature. A liquid crystal display device for displaying an image by adjusting light transmittance of liquid crystal cells according to a video signal uses a thin film transistor as a device for switching liquid crystal cells.
박막트랜지스터는 반도체층으로서 아몰퍼스(Amorphous) 실리콘과 폴리(Poly) 실리콘을 사용하는가에 따라 아몰퍼스실리콘형과 폴리실리콘형으로 구분된다. 아몰퍼스실리콘형 박막트랜지스터는 아몰퍼스실리콘막이 비교적 균일성이 좋고 특성이 안정된 장점을 가지고 있으나 전하이동도가 비교적 작아 화소밀도를 향상시키는 경우에는 적용이 어려운 단점이 있다. 또한, 아몰퍼스실리콘형 박막트랜지스터를 사용하는 경우 주변 구동회로를 별도로 제작하여 액정패널에 실장시켜야 하므로LCD의 제조비용이 높다는 단점이 있다. 반면에, 폴리실리콘형 박막트랜지스터는 전하이동도가 높음에 따라 화소밀도 증가에 어려움이 없을 뿐만 아니라 주변 구동회로를 액정패널 상에 일체화하여 실장하게 되므로 제조단가를 낮출 수 있는 장점을 가지고 있다. 폴리실리콘형 박막트랜지스터로는 도 1에 도시된 바와 같이 폴리실리콘으로 이루어진 활성층의 상부에 게이트전극이 형성된 코플래너(Coplana) 구조가 대표적이다.Thin film transistors are classified into an amorphous silicon type and a polysilicon type depending on whether amorphous silicon and poly silicon are used as semiconductor layers. The amorphous silicon thin film transistor has an advantage that the amorphous silicon film has a relatively uniformity and stable characteristics, but it is difficult to apply when the pixel density is improved because the charge mobility is relatively small. In addition, in the case of using an amorphous silicon type thin film transistor, a peripheral driving circuit has to be manufactured separately and mounted on a liquid crystal panel, which has a disadvantage of high LCD manufacturing cost. On the other hand, as the polysilicon thin film transistor has a high charge mobility, it is not only difficult to increase pixel density, but also has a merit of lowering manufacturing cost since the peripheral driving circuit is integrated and mounted on the liquid crystal panel. As a polysilicon thin film transistor, as shown in FIG. 1, a coplanar structure in which a gate electrode is formed on an active layer made of polysilicon is representative.
도 1을 참조하면, 종래의 액정표시소자에서 박막트랜지스터 기판은 투명기판(10) 상에 형성된 버퍼절연막(12)과 층간절연막(20) 사이에 적층된 활성층(14), 게이트절연막(16) 및 게이트전극(18)과, 층간절연막(20) 위에 컨택홀을 통해 활성층(14)과 전기적으로 연결되게 형성된 소오스 및 드레인 전극(22, 24)을 구비하는 코플래너 구조의 박막트랜지스터를 구비한다. 소오스 및 드레인 전극(22, 24) 및 층간절연막(20) 위에는 보호막(26)이 형성된다. 보호막(26) 표면에는 컨택홀을 통해 소오스 및 드레인 전극(22, 24)과 게이트전극(18)에 전기적으로 연결되도록 투명전극들(28)이 형성된다. 게이트전극(18)은 Mo(또는 Cr)이 습식에칭방법에 의해 형성된다. 그런데, 이 Mo층을 습식에칭방법에 의해 에칭할 시, Mo층과 게이트 절연막(16)이 접촉되는 부분이 안쪽으로 침식되어 오버에칭(over etching)이 발생한다. 이로 인해, 게이트전극(18) 측면의 경사도 조절이 어려워 후속 증착공정에 불리한 형태를 가지게 됨으로써 그 위에 도포되는 층간절연막(20)의 스텝 커버리지(Step Coverage) 불량으로 소오스 및 드레인 전극(22, 24)이 단선되는 문제가 발생하게 된다.Referring to FIG. 1, in a conventional liquid crystal display device, a thin film transistor substrate includes an active layer 14, a gate insulating layer 16, and a stacked layer between a buffer insulating layer 12 and an interlayer insulating layer 20 formed on a transparent substrate 10. A thin film transistor having a coplanar structure having a gate electrode 18 and source and drain electrodes 22 and 24 formed on the interlayer insulating layer 20 to be electrically connected to the active layer 14 through a contact hole. The passivation layer 26 is formed on the source and drain electrodes 22 and 24 and the interlayer insulating layer 20. Transparent electrodes 28 are formed on the surface of the passivation layer 26 to be electrically connected to the source and drain electrodes 22 and 24 and the gate electrode 18 through contact holes. The gate electrode 18 is formed of Mo (or Cr) by a wet etching method. By the way, when this Mo layer is etched by the wet etching method, the part where the Mo layer and the gate insulating film 16 contact is eroded inward, resulting in over etching. As a result, it is difficult to control the inclination of the side surface of the gate electrode 18 and thus have a form unfavorable for the subsequent deposition process, so that the source and drain electrodes 22 and 24 are poor due to the poor step coverage of the interlayer insulating film 20 applied thereon. This disconnection problem occurs.
이를 도 2a 내지 도 2c를 참조하여 상세히 설명하면 다음과 같다.This will be described in detail with reference to FIGS. 2A to 2C.
도 2a를 참조하면, 투명기판(10) 위에 버퍼절연막(12)이 형성되고 그 버퍼절연막(12) 위에 활성층(14)이 형성된다. 버퍼절연막(12)은 투명기판(10) 상에 SiO2등의 절연물질을 증착함으로써 형성하게 된다. 활성층(14)은 다결정실리콘으로 이루어진 것으로 버퍼절연막(12) 위에 비정질실리콘을 균일한 두께로 증착한 후 레이저를 이용하여 소정 부분을 결정화시켜 다결정실리콘막을 형성한 후 패터닝함으로써 형성하게 된다.Referring to FIG. 2A, a buffer insulating film 12 is formed on the transparent substrate 10, and an active layer 14 is formed on the buffer insulating film 12. The buffer insulating film 12 is formed by depositing an insulating material such as SiO 2 on the transparent substrate 10. The active layer 14 is made of polycrystalline silicon, and is formed by depositing amorphous silicon with a uniform thickness on the buffer insulating film 12 and then crystallizing a predetermined portion using a laser to form a polysilicon film, followed by patterning.
활성층(14)이 형성된 버퍼절연막(12)의 상부에는 도 2b에 도시된 바와 같이 게이트절연막(16)과 게이트전극(18)이 형성된다. 버퍼절연막(12) 상에 활성층(14)을 덮도록 SiO2등의 절연물질과 Mo층을 순차적으로 증착한 후 포토레지스터패턴(30)을 이용하여 패터닝함으로써 게이트절연막(16)과 게이트전극(18)을 형성하게 된다. 게이트전극(18)의 형성공정을 상세히 하면, 금속물질을 포토레지스터패턴(30)을 이용하여 습식에칭하는 경우, 게이트 절연막(16)과 접촉되는 Mo층의 끝단부(A)의 안쪽으로 침식되는 오버에칭(over etching)이 발생한다. 이는, 습식에칭에 사용되는 에천트용액이 Mo층의 끝단부(A)의 안쪽으로 스며들어 그 부분의 Mo층을 식각하기 때문이다. 이어서, Mo층을 식각하여 형성된 게이트전극(18)을 마스크로 하여 건식에칭에 의해 게이트 절연막(16)이 형성된다. 이와 아울러, 게이트전극(18)을 마스크로 이용하여 활성층(14)의 노출된 부분에 n형 불순물을 이온주입하고 레이저빔을 조사하여 불순물을 활성화시킴으로써 소오스및 드레인영역으로 이용되는 불순물영역을 형성하게 된다. 이어서, 포토레지스트 스트립공정을 통해 포토레지스트 패턴(30)을 제거한다.A gate insulating film 16 and a gate electrode 18 are formed on the buffer insulating film 12 on which the active layer 14 is formed, as shown in FIG. 2B. The gate insulating film 16 and the gate electrode 18 are deposited by sequentially depositing an insulating material such as SiO 2 and a Mo layer to cover the active layer 14 on the buffer insulating film 12, and then patterning the same by using the photoresist pattern 30. ). When the gate electrode 18 is formed in detail, when the metal material is wet-etched using the photoresist pattern 30, the gate electrode 18 is eroded into the end A of the Mo layer in contact with the gate insulating layer 16. Over etching occurs. This is because the etchant solution used for the wet etching soaks into the inner end A of the Mo layer to etch the Mo layer at that portion. Subsequently, the gate insulating film 16 is formed by dry etching using the gate electrode 18 formed by etching the Mo layer as a mask. In addition, using the gate electrode 18 as a mask, n-type impurities are implanted into the exposed portions of the active layer 14 and irradiated with a laser beam to activate the impurities to form impurity regions used as source and drain regions. do. Subsequently, the photoresist pattern 30 is removed through a photoresist strip process.
그 다음, 도 2c와 같이 게이트 전극(18)이 형성된 투명기판(10) 상에 SiNx와 같은 절연물질을 전면 도포함과 아울러 전면 도포된 절연물질을 마스크패턴을 이용하여 패터닝하므로서 투명기판(10) 상에는 층간절연막(20)이 형성된다. 이때, 투명기판(10) 상에 형성되는 층간절연막(20)중 "B"부분과 같이 Mo층이 오버에칭된 부분에 형성되는 층간절연막(20)은 다른 부분에 비해 두께가 얇게 형성된다. 이는, 오버에칭으로 인해 게이트 전극(18) 및 게이트 절연막(16)이 큰 경사각(90。이상)을 가지게끔 형성되기 때문이다. 즉, 게이트 전극(18) 및 게이트 절연막(16)의 큰 경사각으로 인해 그 상에 도포되는 절연물질이 다른 부분에 비해 얇게 도포되거나 아님 단선되어 스텝 커버리지 불량이 발생하게 된다. 이러한 스텝 커버리지 불량으로 인해 이후 공정에서 형성되는 소오스 및 드레인 전극(22,24)이 단선되는 문제가 발생하게 된다.Next, as shown in FIG. 2C, the transparent substrate 10 is coated on the transparent substrate 10 on which the gate electrode 18 is formed by patterning the entire surface of the insulating material such as SiNx and using the mask pattern. An interlayer insulating film 20 is formed thereon. At this time, the interlayer insulating film 20 formed in the portion where the Mo layer is over-etched, such as the "B" portion of the interlayer insulating film 20 formed on the transparent substrate 10, is thinner than other portions. This is because the gate electrode 18 and the gate insulating film 16 are formed to have a large inclination angle (90 ° or more) due to over etching. That is, due to the large angles of inclination of the gate electrode 18 and the gate insulating film 16, the insulating material applied thereon is applied thinner than other portions or is disconnected, resulting in poor step coverage. Due to such poor step coverage, the source and drain electrodes 22 and 24 formed in a later process may be disconnected.
이와 같이, 종래의 코플래너 구조의 박막트랜지스터에서는 게이트전극(18) 형성을 위한 습식에칭 시, 오버에칭으로 인한 Mo층의 경사도 조절이 어려워 후속 증착공정에 불리한 형태를 가지게 됨으로써 그 위에 도포되는 층간절연막(20)의 단차부에 골이 발생하는 등과 같이 스텝 커버리지 불량이 발생하게 된다. 층간절연막(20)의 스텝 커버리지 불량에 의해 그 위에 형성되는 소오스 및 드레인 전극(22, 24)이 단선되어 박막트랜지스터 및 그를 이용한 액정표시소자의 불량율이 높아지게 된다.As described above, in the conventional coplanar thin film transistor, during the wet etching for forming the gate electrode 18, it is difficult to control the inclination of the Mo layer due to overetching and thus have an unfavorable shape for the subsequent deposition process. Defective step coverage occurs, such as the occurrence of a valley at the stepped portion of 20. Due to poor step coverage of the interlayer insulating film 20, the source and drain electrodes 22 and 24 formed thereon are disconnected to increase the defective rate of the thin film transistor and the liquid crystal display device using the same.
따라서, 본 발명의 목적은 게이트전극 패턴 시 발생하는 스텝 커버리지 불량으로 인해 그 상에 형성되는 금속물질의 단선 불량을 제거하여 불량율을 최소화하는 폴리실리콘형 박막트랜지스터 제조방법을 제공하는 데 있다.Accordingly, an object of the present invention is to provide a polysilicon thin film transistor manufacturing method for minimizing the defective rate by eliminating the disconnection defect of the metal material formed thereon due to the step coverage defect generated during the gate electrode pattern.
도 1은 종래의 액정표시소자에서 폴리실리콘형 박막트랜지스터 기판의 단면도.1 is a cross-sectional view of a polysilicon thin film transistor substrate in a conventional liquid crystal display device.
도 2a 내지 도 2c는 도 1에 도시된 폴리실리콘형 박막트랜지스터 기판의 제조방법을 단계적으로 도시한 단면도.2A to 2C are cross-sectional views illustrating a method of manufacturing the polysilicon thin film transistor substrate shown in FIG.
도 3a 및 도 3c는 본 발명의 실시예에 따른 폴리실리콘형 박막트랜지스터 기판의 제조방법을 단계적으로 도시한 단면도.3A and 3C are cross-sectional views illustrating a method of manufacturing a polysilicon thin film transistor substrate according to an exemplary embodiment of the present invention.
<도면의 주요부분에 대한 부호의 간단한 설명><Brief description of symbols for the main parts of the drawings>
10, 40 : 투명기판 12, 42 : 버퍼절연막10, 40: transparent substrate 12, 42: buffer insulating film
14, 44 : 활성층 16, 46 : 게이트절연막14, 44: active layer 16, 46: gate insulating film
18, 48 : 게이트전극 20, 52 : 층간절연막18, 48: gate electrode 20, 52: interlayer insulating film
22, 56 : 소오스전극 24, 58 : 드레인전극22, 56: source electrode 24, 58: drain electrode
28 : 투명전극 30, 50 : 포토레지스터패턴28: transparent electrode 30, 50: photoresist pattern
상기 목적을 달성하기 위하여, 본 발명에 따른 박막트랜지스터의 제조방법은 임의의 기판 상에 평탄화된 버퍼절연막을 형성하는 단계와, 상기 버퍼절연막의 상부에 활성층을 형성하는 단계와, 상기 활성층 상에 순차적으로 적층되어진 게이트절연막과 금속층으로 이루어진 게이트전극을 건식에칭을 이용하여 동시에 패터닝하는 단계와, 상기 활성층, 게이트절연막, 게이트전극이 적층되어진 버퍼절연막의 상부에 층간절연막을 형성하고 건식에칭하여 컨택홀을 형성하는 단계와, 상기 컨택홀을 통해 상기 활성층과 전기적으로 접속되는 소오스 및 드레인 전극을 형성하는 단계를 포함한다.In order to achieve the above object, a method of manufacturing a thin film transistor according to the present invention comprises the steps of forming a planarized buffer insulating film on an arbitrary substrate, forming an active layer on top of the buffer insulating film, and sequentially on the active layer Simultaneously patterning the gate electrode formed of the gate insulating film and the metal layer by dry etching, and forming an interlayer insulating film on the buffer insulating film on which the active layer, the gate insulating film, and the gate electrode are stacked, and dry etching. And forming source and drain electrodes electrically connected to the active layer through the contact hole.
상기 목적 외에 본 발명의 다른 목적 및 이점들은 첨부 도면을 참조한 본 발명의 바람직한 실시 예에 대한 설명을 통하여 명백하게 드러나게 될 것이다.Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.
이하, 본 발명의 실시 예는 도 3a 내지 도 3c를 참조하여 상세하게 설명하기로 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 3A to 3C.
도 3a 내지 도 3c는 본 발명의 실시 예에 따른 폴리실리콘형 박막트랜지스터 기판의 제조방법을 단계적으로 나타낸 것이다.3A to 3C show step by step a method of manufacturing a polysilicon thin film transistor substrate according to an embodiment of the present invention.
도 3a를 참조하면, 투명기판(40) 위에 버퍼절연막(42)이 형성되고 그 버퍼절연막(42) 위에 활성층(44)이 형성된다. 버퍼절연막(42)은 투명기판(40) 상에 SiO2등의 절연물질을 증착함으로써 형성하게 된다. 활성층(44)은 다결정실리콘으로 이루어진 것으로 버퍼절연막(42) 위에 비정질실리콘을 균일한 두께로 증착한 후 레이저를 이용하여 결정화시켜 다결정실리콘막을 형성한 후 패터닝함으로써 형성하게 된다.Referring to FIG. 3A, a buffer insulating film 42 is formed on the transparent substrate 40, and an active layer 44 is formed on the buffer insulating film 42. The buffer insulating film 42 is formed by depositing an insulating material such as SiO 2 on the transparent substrate 40. The active layer 44 is made of polycrystalline silicon and is formed by depositing amorphous silicon with a uniform thickness on the buffer insulating film 42 and crystallizing by using a laser to form a polycrystalline silicon film and then patterning.
활성층(44)이 형성된 버퍼절연막(42)의 상부에는 도 3b에 도시된 바와 같이 게이트절연막(46)과 게이트전극(48)이 형성된다. 버퍼절연막(42) 상에 활성층(44)을 덮도록 SiO2등의 절연물질과 Mo층을 순차적으로 증착한 후 포토레지스터패턴(50)을 이용하여 패터닝함으로써 게이트절연막(46)과 게이트전극(48)을 형성하게 된다. 이 경우, 게이트전극(48) 및 게이트 절연막(46)은 한 번의 건식에칭에 의해 패터닝되어 투명기판(40) 상에 형성된다. 이때, 게이트전극(48) 및 게이트 절연막(46)은 건식에칭에 의해 "C"와 같이 완만한 경사각(45。이하)을 가지게끔 형성된다. 그리고, 게이트전극(48)을 마스크로 이용하여 활성층(44)의 노출된 부분에 n형 불순물을 이온주입하고 레이저빔을 조사하여 불순물을 활성화시킴으로써 소오스 및 드레인영역으로 이용되는 불순물확산영역을 형성하게 된다. 이어서, 포토레지스트 스트립공정을 통해 포토레지스트 패턴(50)을 제거한다.A gate insulating film 46 and a gate electrode 48 are formed on the buffer insulating film 42 on which the active layer 44 is formed, as shown in FIG. 3B. By sequentially depositing an insulating material such as SiO 2 and an Mo layer to cover the active layer 44 on the buffer insulating layer 42, and patterning the same by using the photoresist pattern 50 to form the gate insulating layer 46 and the gate electrode 48. ). In this case, the gate electrode 48 and the gate insulating film 46 are patterned by one dry etching to be formed on the transparent substrate 40. At this time, the gate electrode 48 and the gate insulating film 46 are formed to have a gentle inclination angle (45 degrees or less), such as "C", by dry etching. Then, using the gate electrode 48 as a mask, ion-implanted n-type impurities into the exposed portion of the active layer 44 and irradiated with a laser beam to activate the impurities to form impurity diffusion regions used as source and drain regions. do. Subsequently, the photoresist pattern 50 is removed through a photoresist strip process.
그 다음, 도 3c와 같이 게이트 전극(48)이 형성된 투명기판(40) 상에 SiNx와같은 절연물질을 전면 도포함과 아울러 전면 도포된 절연물질을 마스크패턴을 이용하여 패터닝함으로써 투명기판(40) 상에는 층간절연막(52)이 형성된다. 층간절연막(52)이 형성된 투명기판(40) 상에 금속물질을 도포하여 패터닝함으로써 소오스 및 드레인전극(56,58)이 형성된다.Next, as shown in FIG. 3C, an insulating material such as SiNx is coated on the transparent substrate 40 on which the gate electrode 48 is formed, and the entire coated material is patterned using a mask pattern to form the transparent substrate 40. An interlayer insulating film 52 is formed thereon. The source and drain electrodes 56 and 58 are formed by coating and patterning a metal material on the transparent substrate 40 on which the interlayer insulating film 52 is formed.
이와 같이, 본 발명에 따른 폴리실리콘형 박막트랜지스터 제조방법은 게이트전극(48) 및 게이트 절연막(46)을 한번의 건식에칭 방법을 이용하여 형성함으로써, 게이트 전극(48) 및 게이트 절연막(46)의 형성 시 측면 경사각의 조절이 용이하여 도 3c의 "D"와 같이 게이트전극(48) 위에 형성되는 층간절연막(52)의 스텝 커버리지가 양호하여 소오스 및 드레인 전극(56, 58)의 단선 문제가 발생하지 않게 된다.As described above, in the method for manufacturing a polysilicon thin film transistor according to the present invention, the gate electrode 48 and the gate insulating film 46 are formed by using a single dry etching method, thereby forming the gate electrode 48 and the gate insulating film 46. When forming, it is easy to adjust the side inclination angle, so that the step coverage of the interlayer insulating film 52 formed on the gate electrode 48 as shown in "D" of FIG. 3C is good, causing a problem of disconnection of the source and drain electrodes 56 and 58. You will not.
상술한 바와 같이, 본 발명에 따른 박막트랜지스터 제조방법에 의하면 게이트전극 및 게이트 절연막을 한번의 건식에칭 방법을 이용함으로써, 게이트전극 형성시 측면 경사도 조절이 용이하여 게이트전극 위에 형성되는 층간절연막의 스텝 커버리지가 양호하여 소오스 및 드레인 전극의 단선 문제가 발생하지 않게 된다.As described above, according to the method of manufacturing the thin film transistor according to the present invention, by using the dry etching method of the gate electrode and the gate insulating film, the step coverage of the interlayer insulating layer formed on the gate electrode is easily controlled by the side slope control when forming the gate electrode. Is satisfactory, so that problems with disconnection of the source and drain electrodes do not occur.
이상 설명한 내용을 통해 당업자라면 본 발명의 기술사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다. 따라서, 본 발명의 기술적 범위는 명세서의 상세한 설명에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의해 정하여져야만 할 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.
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| KR20020055990A true KR20020055990A (en) | 2002-07-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000085269A KR20020055990A (en) | 2000-12-29 | 2000-12-29 | Method for Fabricating Thin Film Transistor of Poly Silicon Type |
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| Country | Link |
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| KR (1) | KR20020055990A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10811522B2 (en) | 2010-11-11 | 2020-10-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
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2000
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10811522B2 (en) | 2010-11-11 | 2020-10-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US11631756B2 (en) | 2010-11-11 | 2023-04-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
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