KR20020055896A - Method of processing for erasing a flash memory cell - Google Patents

Abstract

PURPOSE: A method for erasing a flash memory cell is provided to reduce threshold voltage of a cell and stress of the cell by setting target threshold voltage of each level. CONSTITUTION: The first erase process(210) is performed. The first erase process(210) includes an executing process of an erase operation executing process(S211), a comparing process of threshold voltage of a cell and a predetermined threshold voltage condition(S212), and a comparing process of the number of erase operation and a predetermined erase number(S214). The second erase process(220) is performed. The second erase process includes the executing process of the erase operation(S221), the comparing process of threshold voltage of the cell and a predetermined threshold voltage condition(S222), and the comparing process of the number of erase operation and the predetermined erase number(S224). The third erase process(230) is performed. The third erase process and the fourth erase process include the executing process of the erase operation(S231,S241), the comparing process of threshold voltage of the cell and a predetermined threshold voltage condition(S232,S242), and the comparing process of the number of erase operation and the predetermined erase number(S234,S244).

Description

Method of processing for erasing a flash memory cell}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of erasing a flash memory cell, and more particularly, to a method of erasing a flash memory cell capable of maximally reducing the stress applied to the cell by the erase operation while equalizing the threshold voltage distribution of the cell subjected to the erase operation. It is about.

In the conventional flash memory cell erasing method, the erasing method using a multi-step pulse is constant in the memory for each step regardless of the degree of discharge of the charge stored in the floating gate of the cell. An erase operation is performed a predetermined number of times, which is performed under the condition that the characteristics of each cell are the same.

In general, an erase operation (an operation of emitting a charge stored in a floating gate of a flash memory cell) is performed in units of sectors while dividing cells in sectors. At this time, a voltage of about -9V is applied to the control gate electrode of the cell and a voltage of about + 9V is applied to the bulk region. However, if the voltage applied between both ends (the voltage of the control gate and the bulk region) differs by more than 12V from the beginning, the cells become overwhelmed and stressed. In order to prevent such stress, in the first erasing step, an erase operation is performed while a voltage of about -9 V is applied to the control gate electrode and about +3 V is applied to the bulk region, and then the threshold voltages of the cells are sensed. Compare and verify with the threshold voltage Vt. If the final target threshold voltage is not satisfied, the erase operation is repeatedly performed. Then, when the number of times of erasing reaches the set maximum value, the erase operation and the threshold voltage verification are again performed while applying a bias of about + 4V to the bulk region to increase the potential difference between the control gate and the bulk region. Try again. If the threshold voltage of the cells after the erase operation satisfies the condition of the threshold voltage as the final target, it is determined whether the cell sector in which the erase operation has been performed is the last sector. In the case of the last sector, the erase operation is terminated.

Referring to FIG. 1, the steps of a conventional flash memory cell erase method are described below.

As shown in FIG. 1, in the first erasing step 110, a constant voltage (for example, −9 V) is applied to a control gate of a cell divided into sectors, and an erase voltage (for example, for a bulk region). The erase operation is performed in the state where + 3V) is applied (S111). Thereafter, the threshold voltage of the cell is sensed and compared with the final target threshold voltage to verify it (S112). If the threshold voltage of the cell does not satisfy the final target threshold voltage condition, the erase operation (S111) and the comparison verification step (S112) are repeatedly performed until the maximum number of times the erase operation is repeatedly set, and the maximum number of times of execution. If the threshold voltage of the cell does not satisfy the final target threshold voltage even when the erase operation S111 and the comparison verify step S112 are repeatedly performed, the process proceeds to the secondary erase step 120 (S113).

In the second erasing step 120, a voltage applied to the bulk area is applied higher (eg, + 4V) than the first erasing step 110 in order to improve the erase operation characteristic, so that the potential difference between the control gate and the bulk area is increased. To make it larger. Subsequently, an operation of determining an erase operation (S121), a final target threshold voltage verification (S122), and determining the number of times of erasing (S123) coincides with an operation of the primary erase step 110. If the final target threshold voltage is not satisfied even in the second erase step 120, the above operations are repeated by increasing the potential difference between the control gate and the bulk region in the third erase step 130.

Finally, in the fourth erasing step 140, if the final target threshold voltage is not satisfied after repeating the above operations in a state where the potential difference between the control gate and the bulk region is maximized as large as possible, the process is defective (S144). If any of the final target threshold voltage verification steps S112, S122, S132, and S142 included in the first to fourth erasing steps 110 to 140 is satisfied, then the subsequent erase step is satisfied. Without going through, the next sector is selected (S152) to perform the first to fourth erase steps (110 to 140) again. If the sector in which the current erase operation is performed is the last sector, the erase operation is terminated (S151).

The erase method of the flash memory cell described above rarely satisfies the final target threshold voltage in most primary or secondary erase steps. Therefore, the first or second erase steps are repeatedly performed up to the maximum number of erase operations, which may cause stress on the cell and shorten the life of the device.

Accordingly, in order to solve the above problem, the present invention sets the target threshold voltages for each step, thereby avoiding repeated erase operations up to the maximum number of erase operations, and gradually lowers the threshold voltages of the cells, thereby reducing the stress applied to the cells. It is an object of the present invention to provide a method of erasing a flash memory cell that can be suppressed as much as possible to improve device lifetime and to uniformize the threshold voltage distribution of the cell.

1 is a flowchart illustrating a method of erasing a conventional flash memory cell.

2 is a flowchart illustrating a method of erasing a flash memory cell according to the present invention.

<Description of the symbols for the main parts of the drawings>

110, 210: first erasing step 120, 220: second erasing step

130, 230: third erase step 140, 240: fourth erase step

An erase method of a flash memory cell according to the present invention includes a first step of performing an erase operation by applying a first erase voltage to all cells of a sector; A second step of performing a comparison between the threshold voltage of the cell lowered by the erase operation and the first voltage and a comparison between the number of erase operations performed up to now and the maximum possible number of operations; A third step of performing the erasing step if the threshold voltage of the cell is higher than the first voltage and the number of erase operations performed is less than the maximum possible number of times in the second step; When the threshold voltage of the cell is lower than the first voltage or the number of erase operations performed in the second step coincides with the maximum possible number of times, the erase operation is stopped and the threshold voltage of the cell satisfies the target threshold voltage. Fourth step; A fifth step of determining whether the sector is the last sector when the threshold voltage of the cell is lower than the target voltage as the final target in the fourth step; A sixth step in which the erase operation of the cell is started after the next sector is selected in the fifth step and the erase operation is terminated in the last sector; In the fourth step, if the threshold voltage of the cell is higher than the target voltage as the final target, the first to fifth steps may be repeated, but depending on the number of times, the first erase voltage may be repeatedly applied to the maximum voltage that can be applied to the cell. The first step is to change sequentially each time, and the first voltage is also changed sequentially to the final target threshold voltage every time, and if it does not go down to the final target threshold voltage until the end, the seventh step of performing a fifth step after the failure process Is made of.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

2 is a flowchart illustrating a method of erasing a flash memory cell according to the present invention.

As shown in FIG. 2, in the first erase step 210, a constant voltage (eg, −9 V) is applied to a control gate of a cell divided into sectors, and an erase voltage (eg, is applied to a bulk area). The erase operation is performed while the + 3V) is applied (S211).

Thereafter, the threshold voltage of the cell subjected to the erasing operation is sensed and compared with the threshold voltage condition (for example, the threshold voltage condition in the first erasing step is set to 5 V) to determine whether it is satisfied. (S212). If the threshold voltage of the cell does not satisfy the step-by-step threshold voltage condition, the number of erase operations is compared with the maximum allowable number of erase operations (S214), and the process proceeds to the erase operation (S211) until the erase operation is not exceeded. If the threshold voltage condition is not satisfied even after repeatedly performing the erase operation up to the maximum allowable number, the process simply goes to the second erase step 220 and the erase operation is performed by changing the condition (step threshold voltage condition and the bias condition applied to the bulk region). Rerun. Even if the threshold voltage condition for each step is not satisfied, the next step is to prevent the stress from being applied to the cell. To this end, the maximum allowable number of erase operations must be properly adjusted.

When the threshold voltage of the cell satisfies the step-by-step threshold voltage condition, it is determined whether the final threshold voltage condition (for example, 2.2V) is also satisfied (S213). When the final threshold voltage condition is satisfied, the erase operation does not need to be performed for the current sector any more. Therefore, it is determined whether the current sector is the last sector (S250). If not, the next sector is selected (S252) and then the process proceeds to the first erase step 210 again.

However, due to the erase characteristic of the cell, it is difficult to meet the threshold voltage condition of the final target in the first erase step 210. In this way, when the step threshold voltage condition is satisfied but the final target threshold voltage is not satisfied, the process proceeds to the second erasing step 220.

In the second erasing step 220, the stepped threshold voltage condition is set to a voltage closer to the final target threshold voltage condition (for example, 4V) than in the first erasing step 210, and bulked to improve the erase operation characteristics. The voltage applied to the region is applied higher (e.g., + 5V) than in the first erase step 210 to increase the potential difference between the control gate and the bulk region.

After the erasing operation S221 is performed under the above condition, the performing steps are performed in the same operation as that performed in the primary erasing step 210. The threshold voltage of the cell on which the erase operation is performed is sensed, compared with a threshold voltage condition set in stages, and verified to determine whether it is satisfied (S222). Similarly, when the threshold voltage of the cell does not satisfy the step-by-step threshold voltage condition, the number of erase operations is compared with the maximum allowable number of erase operations (S224), and the process proceeds to the erase operation (S221) until the erase operation is repeated. Even if the erase operation is repeatedly performed up to the maximum allowable number of times, if the threshold voltage condition is not satisfied, the process proceeds to the third erase step 230.

When the threshold voltage of the cell satisfies the step-by-step threshold voltage condition, it is determined once again whether the final threshold voltage condition (for example, 2.2V) is also satisfied (S223). When the final threshold voltage condition is satisfied, it is no longer necessary to perform an erase operation on the current sector. Therefore, it is determined whether the current sector is the last sector (S250). In the case of the last sector, all erase operations are terminated. If not, the next sector is selected (S252) and then the process proceeds to the first erase step 210 again. If the step threshold voltage condition is satisfied but the final target threshold voltage is not satisfied, the process proceeds to the third erasing step 230.

The third and fourth erasing steps 230 and 240 also set the step-by-step threshold voltage increasingly closer to the final target threshold voltage condition (e.g., 3V in the third erasing step and 2V in the fourth erasing step). In order to improve the erase operation characteristics, the voltage applied to the bulk region is applied higher and higher (e.g., + 7V in the 3rd erasing step and + 9V in the 4th erasing step) than before. The potential difference between the gate and the bulk region is made larger. Under these conditions, the erase operation and the verification steps performed in the first and second erase steps 210 and 220 are performed in the same manner to determine whether the threshold voltage and the final target threshold voltage are satisfied.

In the process of performing the final fourth erasing step 240, if the final target threshold voltage is satisfied, it is determined whether the current sector is the last sector (S251), and even if the erase operation is performed to the maximum allowable number of times, If the final target threshold voltage is not satisfied, after a bad process (S245), it is determined whether the current sector is the last sector (S251) to select the next sector (S252) or the erase operation is terminated.

As described above, the erase method of the flash memory cell according to the present invention is different from the conventional erase method, so that the target threshold voltage is not set excessively for each erase step. Since the voltage can be lowered, it is possible to prevent the stress of the cell and to extend the lifespan, thereby improving the reliability of the device.

Claims (1)

A first step of performing an erase operation by applying a first erase voltage to all cells of a sector; A second step of comparing a threshold voltage of the cell lowered by the erase operation with a first voltage and comparing the number of erase operations performed to date and the maximum possible number of operations; A third step of performing the erasing step if the threshold voltage of the cell is higher than the first voltage and the number of erase operations performed is less than the maximum possible number of times in the second step; If the threshold voltage of the cell is lower than the first voltage or the number of erase operations performed in the second step coincides with the maximum possible number of times, the erase operation is stopped and the threshold voltage of the cell is set as the final target voltage. A fourth step of determining whether to satisfy; A fifth step of determining whether the sector is the last sector when the threshold voltage of the cell is lower than the target voltage as a final target in the fourth step; A sixth step in which the erase operation of the cell is started after selecting the next sector if the last sector is not the last sector in the fifth step, and the erase operation is terminated in the last sector; If the threshold voltage of the cell is higher than the target voltage as the final target in the fourth step, the first to fifth steps are repeated, but the maximum voltage that can apply the first erase voltage to the cell according to the number of times of execution. Change the sequence sequentially every time the repeating operation is performed, and sequentially change the first voltage every time the repeating execution is performed until the final target threshold voltage. And a seventh step of erasing the flash memory cell.