KR20020055885A - Method of manufacturing a transistor in a semiconductor device - Google Patents
Method of manufacturing a transistor in a semiconductor device Download PDFInfo
- Publication number
- KR20020055885A KR20020055885A KR1020000085138A KR20000085138A KR20020055885A KR 20020055885 A KR20020055885 A KR 20020055885A KR 1020000085138 A KR1020000085138 A KR 1020000085138A KR 20000085138 A KR20000085138 A KR 20000085138A KR 20020055885 A KR20020055885 A KR 20020055885A
- Authority
- KR
- South Korea
- Prior art keywords
- region
- tanx
- nitrogen
- precursor
- film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 113
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 59
- 229910004156 TaNx Inorganic materials 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000000203 mixture Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000002243 precursor Substances 0.000 claims description 23
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- MNWRORMXBIWXCI-UHFFFAOYSA-N tetrakis(dimethylamido)titanium Chemical compound CN(C)[Ti](N(C)C)(N(C)C)N(C)C MNWRORMXBIWXCI-UHFFFAOYSA-N 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims 4
- 229910044991 metal oxide Inorganic materials 0.000 abstract 3
- 150000004706 metal oxides Chemical class 0.000 abstract 3
- 238000009413 insulation Methods 0.000 abstract 2
- 230000000295 complement effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 64
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000011160 research Methods 0.000 description 4
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 3
- 238000005086 pumping Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910004479 Ta2N Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000005546 reactive sputtering Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 특히 NMOS 영역에는 게이트 절연막 상부에 일함수가 4.0∼4.4eV가 되도록 질소의 조성(x)이 0.45∼0.55인 제 1 TaNx막을 형성하고, PMOS 영역에는 게이트 절연막 상부에 일함수가 4.8∼5.2eV가 되도록 질소의 조성(x)이 0.6∼1.4인 제 2 TaNx막을 형성함으로써 NMOS 영역 및 PMOS 영역 모두에서 표면 채널(surface channel) CMOS 소자를 구현하여 문턱 전압을 낮출 수 있는 반도체 소자의 트랜지스터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor manufacturing method of a semiconductor device. In particular, in the NMOS region, a first TaNx film having a composition (x) of 0.45 to 0.55 is formed on the gate insulating film so as to have a work function of 4.0 to 4.4 eV. By forming a second TaNx film having a composition (x) of 0.6 to 1.4 in nitrogen so as to have a work function of 4.8 to 5.2 eV above the gate insulating film, a surface channel CMOS device is implemented in both the NMOS region and the PMOS region. The present invention relates to a transistor manufacturing method of a semiconductor device capable of lowering a voltage.
반도체 소자에서 현재 양산중인 DRAM 및 논리 소자의 게이트 절연막으로는 실리콘 산화막(SiO2)이 주로 사용되고 있으며, 디자인룰이 축소됨에 따라 실리콘 산화막의 두께는 터널링 한계인 25∼30Å 이하로 줄어드는 추세에 있다.Silicon oxide film (SiO 2 ) is mainly used as a gate insulating film for DRAM and logic devices currently in mass production in semiconductor devices. As the design rule is reduced, the thickness of the silicon oxide film is decreasing to less than or equal to 25-30 dB, which is a tunneling limit.
0.1㎛ 이하 DRAM의 경우 게이트 절연막의 두께는 30∼35Å 정도로 예상되며, 논리 소자의 경우 게이트 유전체막의 두께는 13∼15Å 정도로 예상된다. 그러나, 폴리실리콘으로 게이트 전극을 형성할 때 폴리실리콘의 공핍(depletion) 현상에 의하여 전기적으로 증가되는 게이트 절연막의 두께가 3∼8Å 정도되기 때문에 15∼30Å 정도로 유효 게이트 절연막 두께(Teff)를 감소시키는데 큰 장애가 되고 있다. 따라서, 최근 이를 극복하기 위한 노력의 일환으로 고유전 물질을 게이트 절연막으로 사용하는 연구가 진행되고 있다. 한편으로는 폴리실리콘 대신에 금속으로 게이트 전극을 형성함으로써 폴리실리콘의 공핍 현상을 최소화하는 방향으로 연구가 진행되고 있다. 뿐만 아니라 폴리실리콘으로 게이트 전극을 형성하고, p형 불순물, 예를들어 붕소를 이용하여 접합 영역을 형성하는 경우에 발생되는 붕소 침투(boron penetration)와 같은 문제 또한 금속으로 게이트 전극을 형성함으로써 방지할 수 있기 때문에 최근 많은 연구가 집중되고 있다.In the case of DRAMs of 0.1 mu m or less, the thickness of the gate insulating film is expected to be about 30 to 35 GPa, and in the case of logic devices, the thickness of the gate dielectric film is expected to be about 13 to 15 GPa. However, when the gate electrode is formed of polysilicon, the thickness of the gate insulating film electrically increased due to depletion of polysilicon is about 3 to 8 microseconds, so the effective gate insulating film thickness T eff is reduced to about 15 to 30 microseconds. It is becoming a big obstacle. Therefore, recently, as part of efforts to overcome this problem, researches on using a high dielectric material as a gate insulating film have been conducted. On the other hand, research is being conducted to minimize the depletion phenomenon of polysilicon by forming gate electrodes made of metal instead of polysilicon. In addition, problems such as boron penetration generated when the gate electrode is formed of polysilicon and the junction region is formed using p-type impurities such as boron can also be prevented by forming the gate electrode with metal. Recently, a lot of research has been concentrated.
금속으로 게이트 전극을 형성하기 위해 TiN 또는 WN을 중심으로 많은 연구가 진행되어 왔다, 그러나, 이들은 일함수(work function)가 4.75∼4.85eV 정도이기 때문에 미드갭(midgap) 일함수에서 가전자대(valence band)쪽으로 가깝게 일함수가 형성된다. 상기의 일함수는 표면 채널 PMOS의 경우 어느 정도 적합한 수준이라고 할 수 있으나, NMOS의 경우 채널 도핑을 2∼5×1017/㎤ 정도로 가져갈 때 문턱 전압이 거의 0.8∼1.2V 정도가 됨을 의미한다. 즉, 이러한 경우 저전압 또는 저전력의 특성을 갖는 고성능 소자에서 요구되는 0.3∼0.6V의 문턱 전압 타겟을 만족시킬 수 없게 된다. 따라서, NMOS와 PMOS에서 동시에 0.3∼0.6V 정도의 낮은 문턱 전압을 얻기 위해서는 NMOS의 경우 일함수가 약 4.0∼4.4eV, PMOS의 경우 일함수가 약 4.8∼5.2eV 정도를 갖는 이중 금속 전극을 사용하는 것이 바람직하다.Much research has been conducted around TiN or WN to form gate electrodes from metals, however, they have valence at midgap work function because the work function is about 4.75 to 4.45 eV. The work function is formed close to the band). The above work function can be said to be suitable to some extent in the case of the surface channel PMOS, but in the case of the NMOS, when the channel doping is about 2 to 5 x 10 17 / cm 3, the threshold voltage is almost 0.8 to 1.2V. That is, in such a case, the threshold voltage target of 0.3 to 0.6 V, which is required in a high performance device having low voltage or low power, cannot be satisfied. Therefore, in order to obtain a low threshold voltage of 0.3 to 0.6V at the same time in the NMOS and the PMOS, a double metal electrode having a work function of about 4.0 to 4.4 eV for the NMOS and a work function of about 4.8 to 5.2 eV for the PMOS is used. It is desirable to.
본 발명의 목적은 NMOS 영역에는 낮은 일함수를 갖고, PMOS 영역에는 높은 일함수를 갖는 금속 게이트 전극을 형성함으로써 상기의 문제점을 해결할 수 있는 반도체 소자의 트랜지스터 제조 방법을 제공하는데 있다.An object of the present invention is to provide a transistor manufacturing method of a semiconductor device which can solve the above problems by forming a metal gate electrode having a low work function in the NMOS region and a high work function in the PMOS region.
본 발명의 다른 목적은 TaNx막의 일함수가 질소의 조성에 따라 변화하는 것을 이용하여 이중 일함수 금속 게이트 전극을 형성하는 반도체 소자의 트랜지스터 제조 방법을 제공하는데 있다.Another object of the present invention is to provide a transistor manufacturing method of a semiconductor device in which a double work function metal gate electrode is formed by using a work function of a TaN x film depending on the composition of nitrogen.
도 1은 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위해 도시한 소자의 단면도.BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a device for explaining the transistor manufacturing method of a semiconductor device according to the present invention.
도 2는 게이트 산화막 두께에 따른 TaNx막의 C-V 곡선.2 is a C-V curve of a TaNx film according to the gate oxide film thickness.
도 3(a)은 TaNx막의 질소 조성에 따른 유효 게이트 산화막 두께 및 그에 따른 플랫밴드 전압 그래프.Figure 3 (a) is a graph of the effective gate oxide film thickness and the flat band voltage according to the nitrogen composition of the TaNx film.
도 4는 TaNx막의 질소 함유량에 따른 상분석 결과도.4 is a phase analysis result according to the nitrogen content of the TaNx film.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
A : NMOS 영역B : PMOS 영역A: NMOS area B: PMOS area
11 : 반도체 기판12 : p-웰11 semiconductor substrate 12 p-well
13 : n-웰14 : 게이트 절연막13: n-well 14: gate insulating film
15 : 제 1 TaNx막16 : 제 2 TaNx막15: first TaNx film 16: second TaNx film
17 : 금속층18 : 스페이서17 metal layer 18 spacer
19 : p형 접합 영역20 : n형 접합 영역19: p-type junction region 20: n-type junction region
본 발명에 따른 반도체 소자의 트랜지스터 제조 방법은 반도체 기판의 소정 영역에 제 1 불순물 및 제 2 불순물을 각각 주입하여 제 1 영역 및 제 2 영역을 확정하는 단계와, 상기 제 1 영역 및 제 2 영역이 확정된 반도체 기판 상부에 게이트 절연막을 형성하는 단계와, 상기 제 1 영역 상부에 제 1 일함수를 갖도록 제 1 질소 조성을 갖는 제 1 TaNx막을 형성하는 단계와, 상기 제 2 영역 상부에 제 2 일함수를 갖도록 제 2 질소 조성을 갖는 제 2 TaNx막을 형성하는 단계와, 상기 제 1 및 제 2 TaNx막을 포함한 전체 구조 상부에 금속층을 형성하는 단계와, 상기 금속층, 제 1 및 제 2 TaNx막, 그리고 게이트 절연막을 패터닝하여 제 1 및 제 2 영역 각각에 게이트 전극을 형성하는 단계와, 상기 제 1 영역의 반도체 기판에 제 1 불순물을 주입하여 제 1 접합 영역을 형성하고, 상기 제 2 영역의 반도체 기판에 제 2 불순물을 주입하여 제 2 접합 영역을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In the method of manufacturing a transistor of a semiconductor device according to the present invention, the method comprises the steps of: injecting a first impurity and a second impurity into a predetermined region of a semiconductor substrate to determine a first region and a second region, wherein the first region and the second region Forming a gate insulating film over the determined semiconductor substrate, forming a first TaNx film having a first nitrogen composition to have a first work function over the first region, and a second work function over the second region Forming a second TaNx film having a second nitrogen composition to form a metal layer, forming a metal layer over the entire structure including the first and second TaNx films, the metal layer, the first and second TaNx films, and a gate insulating film Forming a gate electrode in each of the first and second regions by injecting a first electrode, implanting a first impurity into the semiconductor substrate of the first region to form a first junction region, and And forming a second junction region by injecting a second impurity into the semiconductor substrate of the second region.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1은 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 is a cross-sectional view of devices sequentially shown for explaining a method of manufacturing a transistor of a semiconductor device according to the present invention.
도 1을 참조하면, 반도체 기판(11)의 소정 영역에 p형 불순물 및 n형 불순물을 각각 주입하여 p-웰(12) 및 n-웰(13)을 형성함으로써 NMOS 영역(A)과 PMOS 영역(B)을 확정한다. 전체 구조 상부에 게이트 절연막(14)을 형성한다. NMOS 영역(A)의 게이트 절연막(14) 상부에 4.0∼4.4eV 정도의 일함수를 갖도록 질소의 조성(x)이 0.45∼0.55 정도인 제 1 TaNx막(15)을 형성한다. 한편, PMOS 영역(B)의 게이트 절연막(14) 상부에 4.8∼5.2eV 정도의 일함수를 갖도록 질소의 조성(x)이 0.6∼1.6 정도인 제 2 TaNx막(16)을 형성한다. 상기 제 1 및 제 2 TaNx막(15 및 16)은 각각 5∼500Å의 두께로 형성한다. 전체 구조 상부에 텅스텐등과 같은 저항이 낮은 금속층(17)을 형성한다. NMOS 영역(A) 및 PMOS 영역(B)의 금속층(17), 제 1 및 제 2 TaNx막(15 및 16), 그리고 게이트 절연막(14)의 소정 부분을 패터닝하여 게이트 전극을 각각 형성한다. NMOS 영역(A)의 반도체 기판(11)상에 저농도 n형 불순물을 주입하고, PMOS 영역(B)에 저농도 p형 불순물을 주입한다. 전체 구조 상부에 절연막을 형성한 후 전면 식각 공정을 실시하여 NMOS 영역(A) 및 PMOS 영역(B)에 각각 형성된 게이트 전극 측벽에 스페이서(18)를 각각 형성한다. NMOS 영역(A)의 반도체 기판(11)상에 고농도 n형 불순물을 주입하고, PMOS 영역(B)에 고농도 p형 불순물을 주입한다. 이에 의해 NMOS 영역(A)에는 LDD 구조의 n형 접합 영역(19)이 형성되고, PMOS 영역(B)에는 LDD 구조의 p형 접합 영역(20)이 형성된다.Referring to FIG. 1, an NMOS region A and a PMOS region are formed by implanting p-type impurities and n-type impurities into predetermined regions of the semiconductor substrate 11 to form p-well 12 and n-well 13, respectively. (B) is confirmed. A gate insulating film 14 is formed over the entire structure. A first TaNx film 15 having a composition (x) of about 0.45 to 0.55 is formed on the gate insulating film 14 in the NMOS region A so as to have a work function of about 4.0 to 4.4 eV. On the other hand, a second TaNx film 16 having a composition (x) of about 0.6 to 1.6 is formed on the gate insulating film 14 in the PMOS region B so as to have a work function of about 4.8 to 5.2 eV. The first and second TaNx films 15 and 16 are formed to have a thickness of 5 to 500 GPa, respectively. A low resistance metal layer 17 such as tungsten is formed on the entire structure. The gate electrodes are formed by patterning the metal layers 17, the first and second TaNx films 15 and 16, and the predetermined portions of the gate insulating film 14 in the NMOS region A and the PMOS region B, respectively. Low concentration n-type impurities are implanted into the semiconductor substrate 11 in the NMOS region A, and low concentration p-type impurities are implanted into the PMOS region B. FIG. After forming an insulating film over the entire structure, a front surface etching process is performed to form spacers 18 on sidewalls of gate electrodes formed in the NMOS region A and the PMOS region B, respectively. High concentration n-type impurities are implanted into the semiconductor substrate 11 in the NMOS region A, and high concentration p-type impurities are implanted into the PMOS region B. FIG. As a result, an n-type junction region 19 having an LDD structure is formed in the NMOS region A, and a p-type junction region 20 having an LDD structure is formed in the PMOS region B. As shown in FIG.
상기에서, 제 1 및 제 2 TaNx막(15 및 16)은 스퍼터링 방법, 전구체를 이용한 CVD 방법 또는 어드밴스드(advanced) CVD 방법, 단원자 증착법(atomic layer deposition), 원격 플라즈마(remote plasma) CVD 방법중에서 어느 하나의 방법으로 형성한다.In the above, the first and second TaNx films 15 and 16 may be formed by a sputtering method, a CVD method using a precursor or an advanced CVD method, an atomic layer deposition method, a remote plasma CVD method. It is formed by either method.
스퍼터링 방법을 사용하여 제 1 TaNx막(15)이 4.0∼4.4eV 정도의 일함수를 갖도록 하기 위해서는 Ta 타겟을 장착한 후 질소 및 Ar을 각각 0∼100sccm 및 5∼100sccm의 양으로 유입시키고, 직류 전원을 0.25∼15kW 인가하는 질소 반응성 스퍼터링 방법을 실시한다. 한편, 제 2 TaNx막(16)이 4.8∼5.2eV 정도의 일함수를 갖도록 하기 위해서는 Ta 타겟을 장착한 후 질소 및 Ar을 각각 30∼200sccm 및 5∼30sccm의 양으로 유입시키고, 직류 전원을 0.25∼15kW를 인가하는 질소 반응성 스퍼터링 방법을 실시한다. 여기서, 질소 및 Ar의 양은 직류 전원에 따라 증감할 수 있다.In order for the first TaNx film 15 to have a work function of about 4.0 to 4.4 eV using the sputtering method, after the Ta target is mounted, nitrogen and Ar are introduced in amounts of 0 to 100 sccm and 5 to 100 sccm, respectively. A nitrogen reactive sputtering method of applying 0.25-15 kW of power is performed. On the other hand, in order for the second TaNx film 16 to have a work function of about 4.8 to 5.2 eV, after mounting a Ta target, nitrogen and Ar are introduced in amounts of 30 to 200 sccm and 5 to 30 sccm, respectively, and the DC power supply is 0.25. The nitrogen reactive sputtering method which applies -15 kW is implemented. Here, the amounts of nitrogen and Ar can be increased or decreased in accordance with the DC power source.
전구체를 이용한 CVD 또는 어드밴스드(advanced) CVD 방법을 이용하여 제 1및 제 2 TaNx막(15 및 16)을 형성하기 위해서 Ta 전구체로 TaCl3, Ta(OC2H5)4, TDMAT, TDEAT중 어느 하나를 사용하며, 질소 소오스로는 NH3, N2, ND3중 어느 하나를 사용한다. 여기서, 제 1 TaNx막(15)을 형성하기 위해서는 Ta 전구체의 0.45∼0.55배 정도로 질소 소오스를 유입시키고, 제 2 TaNx막(16)을 형성하기 위해서는 Ta 전구체의 0.6∼1.4배 정도로 질소 소오스를 유입시킨다.Any of TaCl 3 , Ta (OC 2 H 5 ) 4 , TDMAT, TDEAT as the Ta precursor to form the first and second TaNx films 15 and 16 using CVD using precursors or advanced CVD methods One is used, and the nitrogen source is any one of NH 3 , N 2 , ND 3 . In order to form the first TaNx film 15, the nitrogen source is introduced at about 0.45 to 0.55 times the Ta precursor, and to form the second TaNx film 16, the nitrogen source is introduced at about 0.6 to 1.4 times the Ta precursor. Let's do it.
단원자 증착법을 이용하여 제 1 및 제 2 TaNx막(15 및 16)을 형성하기 위해서 TaCl3, Ta(OC2H5)4, TDMAT, TDEAT중 어느 하나를 Ta 전구체로 사용하여 50∼650℃의 온도와 0.05∼3Torr의 압력에서 형성한다. 이때, 질소 함량을 조절하기 위해 NH3, N2, ND3중 어느 하나를 이용하여 펌핑(pumping)을 실시하는데, 펌핑 사이클의 수로 질소의 조성을 제어한다. 여기서, 제 1 TaNx막(15)을 형성하기 위해서는 Ta 전구체의 0.45∼0.55배 정도로 질소 소오스를 유입시키고, 제 2 TaNx막(16)을 형성하기 위해서는 Ta 전구체의 0.6∼1.4배 정도로 질소 소오스를 유입시킨다.In order to form the first and second TaNx films 15 and 16 using monoatomic deposition, any one of TaCl 3 , Ta (OC 2 H 5 ) 4 , TDMAT, and TDEAT was used as a Ta precursor to 50 ° C. to 650 ° C. At a temperature of 0.05 to 3 Torr. At this time, pumping is performed using any one of NH 3 , N 2 , and ND 3 to adjust the nitrogen content, and the composition of nitrogen is controlled by the number of pumping cycles. In order to form the first TaNx film 15, the nitrogen source is introduced at about 0.45 to 0.55 times the Ta precursor, and to form the second TaNx film 16, the nitrogen source is introduced at about 0.6 to 1.4 times the Ta precursor. Let's do it.
원격 플라즈마 CVD 방법을 이용하여 제 1 및 제 2 TaNx막(15 및 16)을 형성하기 위해서 TaCl3, Ta(OC2H5)4, TDMAT, TDEAT중 어느 하나를 Ta 전구체로 사용하여 형성한다. 이때, 이때, 질소 함량을 조절하기 위해 NH3, N2, ND3중 어느 하나를 이용하여 펌핑(pumping)을 실시한다. 그리고, 원격 플라즈마를 위한 플라즈마 소오스로 ECR(Electron Cyclotron Resonance)을 사용할 경우 2.0∼9.0㎓의 주파수를 사용하며, 플라즈마를 여기하기 위해 He, Ar, Kr, Xe 가스중 어느 하나를 사용한다. 또한, 사용 가스의 흐름율을 조절하여 Ta와 N의 상대량을 조절한다. 이때, 원격 플라즈마 CVD 방법을 실시할 때 금속 소오스는 웨이퍼 부근에서 분사하여 챔버내로의 주입하며, 질소 소오스는 플라즈마 근처에서 여기시켜서 웨이퍼 부근으로 도입한다. 여기서, 제 1 TaNx막(15)을 형성하기 위해서는 Ta 전구체의 0.45∼0.55배 정도로 질소 소오스를 유입시키고, 제 2 TaNx막(16)을 형성하기 위해서는 Ta 전구체의 0.6∼1.4배 정도로 질소 소오스를 유입시킨다.In order to form the first and second TaNx films 15 and 16 using a remote plasma CVD method, any one of TaCl 3 , Ta (OC 2 H 5 ) 4 , TDMAT, and TDEAT is formed as a Ta precursor. At this time, in this case, pumping is performed using any one of NH 3 , N 2 , and ND 3 to adjust the nitrogen content. When using ECR (Electron Cyclotron Resonance) as a plasma source for remote plasma, a frequency of 2.0 to 9.0 GHz is used, and any one of He, Ar, Kr, and Xe gases is used to excite the plasma. In addition, the relative amounts of Ta and N are adjusted by adjusting the flow rate of the gas used. At this time, when performing the remote plasma CVD method, the metal source is injected near the wafer and injected into the chamber, and the nitrogen source is excited near the plasma and introduced into the wafer. In order to form the first TaNx film 15, the nitrogen source is introduced at about 0.45 to 0.55 times the Ta precursor, and to form the second TaNx film 16, the nitrogen source is introduced at about 0.6 to 1.4 times the Ta precursor. Let's do it.
상기의 방법 이외에도 여러가지 방법, 예를들어 다마신 공정으로 형성하는 게이트 등에서 NMOS와 PMOS 지역에 각각 질소 조성이 다른 TaNx막을 형성하여 일함수를 조절할 수도 있다.In addition to the above method, a work function may be adjusted by forming TaNx films having different nitrogen compositions in the NMOS and PMOS regions, for example, in gates formed by a damascene process.
통상적으로 게이트 전극의 일함수를 구하기 위해서는 도 2와 같이 몇가지 게이트 산화막의 두께에 대해 정전 용량-전압(capacitance-voltage: 이하, "C-V") 곡선을 구한 후 C-V 곡선에서 각 두께마다 플랫밴드(flatband) 전압을 구한다. 도 2는 TaNx(x=0.5)막의 C-V 곡선을 예로 나타내었다. 여기서, a는 실리콘 산화막이 116.1Å일 경우, b는 실리콘 산화막이 205.9Å일 경우, c는 실리콘 산화막이 290.2Å일 경우, 그리고 d는 실리콘 산화막이 372.7Å일 경우 TaNx막의 C-V 곡선이다. 그후 도 3과 같이 유효 게이트 산화막 두께(Teff)에 따른 플랫밴드 전압 곡선에서 선형 적합시키면(linear fitting) 하나의 직선을 얻게 된다. 이 직선과 Y-축이 만나는 절편값이 (φms/q)에 해당된다. 여기서 φms는 금속의 일함수(φm)와 실리콘 반도체의 일함수(φs)의 차이를 의미한다. 도 3은 TaNx막의 x가 0.5 및 1.0일 경우를 나타낸 것이다.In general, in order to obtain the work function of the gate electrode, a capacitance-voltage (“CV”) curve is obtained for the thicknesses of several gate oxide layers as shown in FIG. 2, and then a flatband is formed for each thickness in the CV curve. ) Get the voltage. 2 shows an example of a CV curve of a TaNx (x = 0.5) film. Where a is 116.1 ms of silicon oxide, b is 205.9 ms of silicon oxide film, c is 290.2 ms of silicon oxide film, and d is CV curve of TaNx film of 372.7 ms of silicon oxide film. After that, as shown in FIG. 3, if a linear fitting is performed on the flat band voltage curve according to the effective gate oxide thickness T eff , one straight line is obtained. The intercept between this straight line and the Y-axis corresponds to (φ ms / q). Here, φ ms means the difference between the work function φ m of the metal and the work function φ s of the silicon semiconductor. 3 shows the case where x of the TaNx film is 0.5 and 1.0.
[표 1]은 상기와 같은 방법으로 실험적으로 구한 TaNx막의 질소 조성에 따른 일함수(φm)를 나타낸다. 질소 조성(x)이 0.0∼0.2인 경우 4.45∼4.73eV 정도의 일함수를 가지고, 질소 조성(x)이 0.45∼0.55인 경우 4.20∼4.40eV 정도의 일함수를 가지며, 질소 조성(x)이 0.6∼1.4인 경우 5.0∼5.20eV 정도의 일함수를 가진다.[Table 1] shows the work function (φ m ) according to the nitrogen composition of the TaNx film experimentally obtained by the above method. When the nitrogen composition (x) is 0.0 to 0.2, it has a work function of about 4.45 to 4.73 eV, and when the nitrogen composition (x) is 0.45 to 0.55, it has a work function of about 4.20 to 4.40 eV, and the nitrogen composition (x) is In the case of 0.6 to 1.4, it has a work function of 5.0 to 5.20 eV.
이와 같이 질소 함유량에 따라 일함수가 달라지는 원인은 TaNx막 내부의 질소 함유량에 따라 형성상의 변화이다. 도 4는 TaNx막의 질소 함유량에 따라 생성되는 박막의 상변화를 XRD를 통하여 분석한 결과이다. TaNx가 Ta2N(x=0.5)이 형성되기에는 부족한 질소를 포함한 경우 α-Ta나 β-Ta와 같은 Ta계 상이 주로 형성되는 반면, Ta2N이 함유하고 있는 질소 조성보다 더 많은 양의 질소를 포함하고 있는 경우(x=0.6이상), 큐빅(cubic)이나 헥사고날(hexagonal) 구조를 갖는 TaN을 형성하고 있음을 알 수 있다. 결국에는 TaNx막내의 질소량을 조절함으로써 이중 일함수를 갖는 CMOS 금속 게이트 전극의 구현이 가능함을 의미한다. 즉, TaNx막을 게이트 전극으로 사용함에 있어서 NMOS 영역에는 0.45∼0.55 정도의 질소가 함유된 TaNx막을 사용하고, PMOS 영역에는 0.6∼1.4 정도의 질소가 함유된 TaNx막을 사용한다.The reason why the work function varies depending on the nitrogen content is a change in the formation phase depending on the nitrogen content in the TaNx film. 4 is a result of analyzing the phase change of the thin film produced according to the nitrogen content of the TaNx film through XRD. When TaNx contains nitrogen that is insufficient for Ta2N (x = 0.5), Ta-based phases such as α-Ta or β-Ta are mainly formed, but contain more nitrogen than the nitrogen composition contained in Ta2N. If present (x = 0.6 or more), it can be seen that it forms a TaN having a cubic or hexagonal structure. After all, it means that the CMOS metal gate electrode having a double work function can be implemented by adjusting the amount of nitrogen in the TaNx film. That is, in using a TaNx film as a gate electrode, a TaNx film containing about 0.45 to 0.55 nitrogen is used in the NMOS region, and a TaNx film containing about 0.6 to 1.4 nitrogen is used in the PMOS region.
상기에서는 CMOS 트랜지스터를 예로하여 설명하였으나, PMOS 트랜지스터 또는 NMOS 트랜지스터 각각에 대해서도 본 발명이 적용된다.In the above description, the CMOS transistor is described as an example, but the present invention also applies to each of the PMOS transistor and the NMOS transistor.
상술한 바와 같이 본 발명에 의하면 NMOS 영역에는 게이트 절연막 상부에 일함수가 4.0∼4.4eV가 되도록, 그리고 PMOS 영역에는 게이트 절연막 상부에 일함수가 4.8∼5.2eV가 되도록 TaNx막을 질소의 조성을 달리하여 형성함으로써 NMOS 영역 및 PMOS 영역 모두에서 표면 채널 CMOS 소자를 구현하여 문턱 전압을 낮출 수 있다.As described above, according to the present invention, the TaNx film is formed by varying the composition of nitrogen in the NMOS region such that the work function is 4.0 to 4.4 eV in the upper portion of the gate insulating film, and the work function is 4.8 to 5.2 eV in the PMOS region. Accordingly, the threshold voltage can be reduced by implementing a surface channel CMOS device in both the NMOS region and the PMOS region.
Claims (28)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0085138A KR100387261B1 (en) | 2000-12-29 | 2000-12-29 | Method of manufacturing a transistor in a semiconductor device |
| US09/887,511 US6537901B2 (en) | 2000-12-29 | 2001-06-25 | Method of manufacturing a transistor in a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2000-0085138A KR100387261B1 (en) | 2000-12-29 | 2000-12-29 | Method of manufacturing a transistor in a semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020055885A true KR20020055885A (en) | 2002-07-10 |
| KR100387261B1 KR100387261B1 (en) | 2003-06-12 |
Family
ID=27688407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2000-0085138A KR100387261B1 (en) | 2000-12-29 | 2000-12-29 | Method of manufacturing a transistor in a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100387261B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100753558B1 (en) * | 2006-08-21 | 2007-08-30 | 삼성전자주식회사 | Cmos transistor of semiconductor device and method of manufacturing the same |
-
2000
- 2000-12-29 KR KR10-2000-0085138A patent/KR100387261B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100753558B1 (en) * | 2006-08-21 | 2007-08-30 | 삼성전자주식회사 | Cmos transistor of semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100387261B1 (en) | 2003-06-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100387259B1 (en) | Method of manufacturing a semiconductor device | |
| US6537901B2 (en) | Method of manufacturing a transistor in a semiconductor device | |
| KR101144436B1 (en) | Introduction of metal impurity to change workfunction of conductive electrodes | |
| US8404594B2 (en) | Reverse ALD | |
| US9281373B2 (en) | Semiconductor device having tungsten gate electrode and method for fabricating the same | |
| JP5743377B2 (en) | Gate electrode structure and manufacturing method | |
| US20080061285A1 (en) | Metal layer inducing strain in silicon | |
| US7956413B2 (en) | Semiconductor device having a field effect transistor using a high dielectric constant gate insulating film and manufacturing method of the same | |
| KR20090025589A (en) | Semiconductor device and method for fabricating metal gate of the semiconductor device | |
| US20070284677A1 (en) | Metal oxynitride gate | |
| KR20000023176A (en) | Manufacture of mosfet devices | |
| US7880242B2 (en) | Semiconductor device and method of fabricating the same | |
| KR100387261B1 (en) | Method of manufacturing a transistor in a semiconductor device | |
| KR100482745B1 (en) | Method of manufacturing a transistor in a semiconductor device | |
| KR100764341B1 (en) | Manufacturing method for semiconductor device | |
| KR100463239B1 (en) | Method for fabricating CMOS semiconductor device | |
| KR100610433B1 (en) | Gate Electrode of Semi- conductor Device and Method for Gate Electrode of Fabricating Semiconductor Device | |
| WO2008005216A2 (en) | Metal layer inducing strain in silicon | |
| KR20030084346A (en) | Gate electrode in semiconductor device and method for fabricating the same | |
| KR20020049937A (en) | Method of manufacturing a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20120424 Year of fee payment: 10 |
|
| LAPS | Lapse due to unpaid annual fee |