KR20020054202A - Apaaratus for calculating inversion of multi level structure in the finite field - Google Patents

Abstract

PURPOSE: An inverse calculation system is provided to calculate an inverse of an arbitrary element by every one frequency of an externally transmitted clock in a Galois field used in an error correction system or an encryption system. CONSTITUTION: The system comprises an 8th power operator(201), multipliers(202, 209, 210, 213) registers(203, 204, 211, 212), a 128th power operator(205), a 2nd power operator(206), a 4th power operator(207) and an 8th power operator(208). The 8th power operator(201) raises an externally input primitive element to the power 8. The multiplier(202) multiplies the externally input primitive element by the number raised to the power 8. The register(203) stores the externally input primitive element. The register(204) stores a result operated by the multiplier(202). The 128th power operator(205) raises the number, stored at the register(203), to the power 128. The power operators(206, 207, 208) raise the number, stored at the register(204), to the power 2, 4, 8, respectively. The multiplier(209) multiplies the number, output by the power operator(205), by the number, output by the power operator(206). The multiplier(210) multiplies the number, output by the power operator(207), by the number, output by the power operator(208). The registers(211, 212) store the numbers output by the multipliers(209, 210), respectively. The multiplier(213) multiplies the number of the register(211) by the number of the register(212).

Description

Apaaratus for calculating inversion of multi level structure in the finite field}

The present invention is a finite field used in an error correction system or an encryption system. Relates to a reciprocal calculation apparatus for calculating an inverse in a circuit, and in particular, a reciprocal calculation of a multi-stage structure for outputting a reciprocal value of an arbitrary finite element per cycle of a clock signal applied from the outside. Relates to a device.

Finite bodies are widely used in codecs for correcting errors in data transmission in digital communication systems and in encryption systems for protecting information. In the finite field calculation, the division is more complicated than the addition or the multiplication, so the circuit is relatively large and the calculation time is long. Therefore, there are many researches on the implementation of efficient algorithms and algorithms for inverse calculation or division in finite bodies.

The number of bits of an arbitrary primitive element constituting the finite body is m, and the total number of elements Speaking of dogs, these finite bodies Express Also, Elements It is expressed as At this time, Is Has the same properties as For example, finite field when m = 8 One element is 8 bits and the total number of elements is 256. At this time, any element Say Same as Thus, any element The inverse for It can be seen that

Fig. 1 is a configuration diagram of a conventional reciprocal calculation device, where “11” denotes a register, “12” denotes a multiplexer, “13” denotes a square multiplier, and “14” denotes a multiplier.

A conventional reciprocal calculation device having a structure as described above is a finite body The operation of the reciprocal calculation circuit is explained as follows.

First, the operation during the clock cycle is as follows. Arbitrary primitive element consisting of 8 bits in a finite body Is input from the outside to the multiplexer 12, the multiplexer 12 is inputted Is selected and transmitted to the square multiplier (13). Input into power multiplier (13) Is Is computed and sent to the multiplier 14. The multiplier 14 is input from the outside And the output of the power multiplier (13) Is multiplied by Is stored in the register 11.

Second, the operation during the clock cycle is as follows. Stored in a register Is input to the multiplexer 12, where the multiplexer 12 selects the output of the register instead of receiving a signal from the outside. therefore, Is input to the power multiplier 13 through the multiplexer 12, and as a result of the calculation Will print Output Is input to the multiplier 14 and input from the outside Is multiplied by The value is sent to register 11.

In this way, the above operation is repeated until the sixth clock period to perform the operation.

Seventh, the value stored in the register 11 in the clock cycle is input to the power multiplier 13 through the multiplexer 12, and the output obtained from the output of the power multiplier 13 is to be. The value at this time The value corresponds to

Therefore, the conventional reciprocal calculation device is implemented with a register, a multiplexer, a square multiplier, and a multiplier, so the total circuit size is small, but a total of 8 clock cycles are required to calculate one reciprocal. This is difficult to apply to a system requiring a fast operation, and also has a problem that requires complex control to meet the calculation time.

The present invention has been proposed to solve the above problems, and consists of a reciprocal calculation circuit in multiple stages (pipelines), one finite element per clock cycle. It is an object of the present invention to provide a reciprocal calculation apparatus having a multi-stage structure for use in a system requiring fast processing speed or continuous output of reciprocal values by allowing the reciprocal value of elements to be output.

1 is a block diagram of a conventional reciprocal calculation device.

2 is a block diagram of an embodiment of a reciprocal calculation apparatus of a multi-stage structure according to the present invention.

3 is a schematic diagram of a quadratic circuit according to an embodiment of the present invention;

4 is a schematic diagram of a quadratic circuit in accordance with an embodiment of the present invention.

5 is an eight-circuit circuit diagram according to an embodiment of the present invention.

6 is a schematic diagram of a 128 power circuit according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

201,208: 8-square multiplier 202,209,210,213: multiplier

203,204,211,212: Register 205: 128 squared multiplier

206: 2 square multiplier 207: 4 square multiplier

The present invention for achieving the above object, finite body In an inverse number calculation device having a multi-stage structure, a source element input from the outside ( First computing means for performing a first predetermined squared operation on; First multiplication means for multiplying a primitive element input from the outside with a primitive element transferred through the first calculating means; First storage means for storing the operation value transferred through the first multiplication means and the source element input from the outside; Second arithmetic means for performing a second predetermined multi-class square operation on the values transmitted through said first storage means; Second multiplication means for multiplying the values output from the second calculation means; Second storage means for storing an output value from the second multiplication means; And third multiplication means for multiplying the output values from the second storage means with each other.

In addition, the present invention is a finite body In a multistage reciprocal calculation apparatus, a source element from the outside ( First reciprocal calculating means for performing an eighth squared operation and a multiplication operation for the " And a second to output a reciprocal value of one finite element every one clock period by performing a multiplication operation after performing a power of two, four, eight, and 128 square operations on the output value from the first reciprocal calculation means. Characterized in that it comprises a reciprocal calculation means.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a configuration diagram of an apparatus for calculating the reciprocal of the multistage structure according to the present invention.

As shown in Figure 2, the reciprocal calculation apparatus according to the present invention, the primitive element input from the outside ( 8) multiplier 201 for 8 squared), a multiplier 202 for multiplying primitive elements input from the outside and primitive elements input through the 8th square multiplier 201, and a primitive element input from the outside A register 203 for multiplying an externally inputted primitive element by eight squares and a register 204 for multiplying and storing an input primitive element and 128 squares for 128 squares of the primitive element stored through the register 203. Multipliers 205, 2, 4, and 8 square multipliers (206, 207, 208) and 128 and 2 square multipliers (205, 206) for 2, 4, and 8 squared primitive elements stored through the register 204, respectively. A multiplier 209 for multiplying 128 multiplied by 2 and a multiplier, and a multiplier 210 for multiplying the multiplying 4 and 8 multiplied by the 4th and 8th multipliers 207,208 , The operation value multiplied by the multiplier (209, 210) Each provided with a register (211 212), and a multiplier 213 for multiplying the output value transferred from the register (211 212) for storing.

Here, each multiplier 205, 206, 207, 208 for square multiplies the two input 8-bit primitive elements with each other to produce an 8-bit output. That is, each of these multipliers 205, 206, 207, and 208 consists of an 8-bit input and an 8-bit output, respectively. A detailed description of these multipliers will be made with reference to FIGS. 3 to 6 to be described later.

FIG. 3 is a schematic diagram of a quadratic circuit according to an embodiment of the present invention and is a description of a square multiplier of the inverse calculation apparatus described in FIG. 2.

As shown in Fig. 3, the input source element A is 8 bits. Multiply by 2 Is developed as shown in Equation 1 below.

FIG. 4 is a schematic diagram of a quadratic circuit according to an embodiment of the present invention, which is a description of a quadratic multiplier of the inverse calculation apparatus described in FIG.

FIG. 5 is a schematic diagram of an eight-circuit circuit according to an embodiment of the present invention, and relates to an eight-square multiplier of the reciprocal calculation apparatus described with reference to FIG.

FIG. 6 is a schematic diagram of a 128 power circuit according to an embodiment of the present invention, and is a 128 square multiplier of the reciprocal calculation apparatus described in FIG. 2. The 128 square multiplication is developed as shown in Equation 4 below.

Now, the operation of the apparatus for calculating the inverse of the multi-stage structure in the finite body of the present invention having the structure as described above is as follows.

First, the source element from the outside during the first cycle of the clock signal Is input and stored in the register 203. Primitive elements Is input to the eight-squared multiplier 201 Is calculated as Is the result of the operation of the eightth multiplier 201 Silver input primitive element Multiplied by multiplier 202 and as a result The value is stored in register 204.

Was stored in register 203 during the second cycle of the clock signal. Is input to the 128 square multiplier 205 Is stored in the register 204 Are input to the power of 2 multiplier 206, the power of 4 square 207 and the power of 8 square 208, respectively. , , Is calculated as 128 squared multiplier (205) and squared multiplier (206) , Is multiplied by multiplier 209 The value is stored in register 211. Is the result of the quadratic multiplier (207) and the eighth square multiplier (208). , Is multiplied by the multiplier 210 and the result is The value is stored in register 212.

Was stored in register 211 during the third cycle of the clock cycle. And stored in register 212 The value is multiplied by multiplier 213 and finally The value is output. If you expand this value It can be seen that.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

As described above, the present invention provides an arbitrary finite object for one clock period. By calculating and outputting the reciprocal value for the elements within, there is an effect that it can be efficiently utilized suitably for a data error correction system, an encryption system, or the like which requires a high processing speed or continuous output of the reciprocal value.

Claims (5)

Finite body In the inverse calculation device of the multi-stage structure, Primitive element input from outside ( First computing means for performing a first predetermined squared operation on; First multiplication means for multiplying a primitive element input from the outside with a primitive element transferred through the first calculating means; First storage means for storing the operation value transferred through the first multiplication means and the source element input from the outside; Second arithmetic means for performing a second predetermined multi-class square operation on the values transmitted through said first storage means; Second multiplication means for multiplying the values output from the second calculation means; Second storage means for storing an output value from the second multiplication means; And Third multiplication means for multiplying the output values from the second storage means with each other Inverse calculation device of a multi-stage structure in a finite body comprising a. The method of claim 1, The first calculating means performs an eighth-square operation on the primitive element, and the second calculating means performs a two-square, four-square, eight-square, or 128-square operation on the output value of the first storage means, respectively. An inverse calculation device of a multistage structure in a finite body. The method of claim 2, The first storage means, A first register for storing a source element input from the outside and a second register for storing an output value from the first multiplication means, The second storage means, A third register configured to receive a value multiplied by a power of 128 and a second power from the second multiplication means and a fourth register configured to receive and store a value obtained by multiplying a fourth power and an 8 power by the second multiplication means An inverse calculation device of a multi-stage structure in a finite body comprising a. The method according to any one of claims 1 to 3, The inverse calculation device, Inverse calculation of a multi-stage structure in a finite body, wherein the operation is completed within a predetermined clock period for a predetermined source element in the finite body, and a result value is output every clock for primitive elements which are continuously inputted every one clock period. Device. Finite body In the inverse calculation device of the multi-stage structure, Primitive elements from the outside ( First reciprocal calculating means for performing an eighth squared operation and a multiplication operation for the " And A second reciprocal for outputting the reciprocal of one finite element every one clock period by performing a multiplication operation after performing a power of two, four, eight, or 128 squares on the output value from the first reciprocal calculation means; Calculation means Inverse calculation device of a multi-stage structure in a finite body comprising a.