KR20020053541A - Method of deposition a metal film in a semiconductor device - Google Patents
Method of deposition a metal film in a semiconductor device Download PDFInfo
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- KR20020053541A KR20020053541A KR1020000083200A KR20000083200A KR20020053541A KR 20020053541 A KR20020053541 A KR 20020053541A KR 1020000083200 A KR1020000083200 A KR 1020000083200A KR 20000083200 A KR20000083200 A KR 20000083200A KR 20020053541 A KR20020053541 A KR 20020053541A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
Abstract
Description
본 발명은 반도체 소자의 금속막 증착 방법에 관한 것으로, 특히 금속막 증착시 수소 원자의 포획(Capture) 능력을 저하시켜 수소 어닐링시 수소의 대부분이 댕글링 본딩(Dangling bonding)된 불안정한 격자 구조를 완화시킬 있도록 하는 반도체 소자의 금속막 증착 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of depositing a metal film of a semiconductor device, and in particular, reduces capturing ability of hydrogen atoms during metal film deposition, thereby alleviating an unstable lattice structure in which most of hydrogen is dangling bonded during hydrogen annealing. The present invention relates to a metal film deposition method of a semiconductor device.
종래의 금속 배선 형성 공정은 배선 재료로 사용되는 알루미늄막의 특성을 향상시키기 위하여, 알루미늄막의 하단막으로 사용되는 티타늄 화합물(Titanium compound)의 두께를 조절하여 리프레시(Refresh) 특성을 개선한다. 특히, 제 1 금속 배선과 제 2 금속 배선의 라이너(Liner)막으로 적용되고 있는 티타늄, 티타늄 나이트라이드막의 두께가 증가하면 리프레시 특성의 급격한 저하로 수율이 낮아지기 때문에 라이너 막의 두께를 최대한 낮게 유지한다. 참고로, 티타늄막의 경우 수소 포획(Capture) 능력이 우수하여 수소 열처리시 패시베이션(Passivation)막에서 이동하는 수소의 이동을 방해함으로써 트랜지스터에 잔존하는 댕글링 본딩(Dangling bonding) 제거에 역작용을 함으로써 문턱전압 변화(Vt shift)의 원인이 된다.The conventional metal wiring forming process improves the refresh characteristics by adjusting the thickness of the titanium compound used as the bottom film of the aluminum film in order to improve the characteristics of the aluminum film used as the wiring material. In particular, when the thickness of the titanium and titanium nitride films applied as the liner films of the first metal wiring and the second metal wiring increases, the yield is lowered due to a sharp decrease in the refresh characteristics, thereby keeping the thickness of the liner film as low as possible. For reference, in the case of titanium film, the capturing ability of hydrogen is excellent, which prevents the migration of hydrogen from the passivation film during hydrogen heat treatment, thereby counteracting the removal of dangling bonding remaining in the transistor, thereby causing a threshold voltage. It causes a Vt shift.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 금속 배선이나 확산 방지막에 사용되는 금속 화합물에 수소 주입을 실시하여 수소 포화 금속막으로 형성함으로써 수소원자의 포획 능력을 저하시켜 패시베이션 등에서 이동하는 수소량이저하되는 것을 방지하고 다량의 수소 원자를 이용하여 트랜지스터의 댕글리 본딩된 불안전한 격자구조를 안정화시켜 문턱 전압 변화(Vt shift) 방지 및 리프레시 특성을 개선하여 전기적 특성을 향상시킬 수 있는 반도체 소자의 금속막 증착 방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems, the present invention provides a hydrogen-saturated metal film by injecting hydrogen into a metal compound used for metal wiring or a diffusion barrier to reduce the capturing ability of the hydrogen atoms, thereby reducing the amount of hydrogen that moves in passivation. Metal film of a semiconductor device which can prevent electrical stress and improve electrical characteristics by stabilizing the dangly bonded unstable lattice structure of the transistor by using a large amount of hydrogen atoms to prevent Vt shift and refresh characteristics. Its purpose is to provide a deposition method.
도 1은 본 발명에 따른 반도체 소자의 금속막 증착 방법을 설명하기 위하여 도시한 공정의 계략도.1 is a schematic diagram of a process shown for explaining a metal film deposition method of a semiconductor device according to the present invention.
도 2는 도 1에서 사용되는 금속 타겟의 제작 과정을 설명하기 위하여 도시한 공정의 계략도.FIG. 2 is a schematic diagram of a process shown to explain a manufacturing process of a metal target used in FIG. 1.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
1 : 반도체 기판10 :스퍼터링 챔버DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 10 Sputtering chamber
11 : 제 1 공급 라인12 : 제 2 공급 라인11: first supply line 12: second supply line
20 : 진공 펌프30 : 금속 타겟 물질20: vacuum pump 30: metal target material
31 : 금속 잉곳40 : 금속 잉곳 제조 장비31: metal ingot 40: metal ingot manufacturing equipment
본 발명에 따른 반도체 소자의 금속막 증착 방법은 반도체 소자를 형성하기 위한 소정의 공정을 실시한 후 티타늄 성분을 포함한 박막을 증착할 반도체 기판을 티타늄 타겟이 장착된 증착 챔버에 장착되는 단계, 반응 챔버 내부에 수소를 포함한 활성화 가스를 공급한 후 전계를 인가하여 반응 챔버 내부를 플라즈마 분위기로 만드는 단계, 활성화 가스 이온을 티타늄 타겟에 충돌시켜 발생한 수소 포화 티타늄 화합물을 반도체 기판의 표면에 증착시켜 수소 포화 티타늄 화합물 박막을 형성하는 단계로 이루어진다.In the method of depositing a metal film of a semiconductor device according to the present invention, after performing a predetermined process for forming a semiconductor device, mounting a semiconductor substrate for depositing a thin film including a titanium component in a deposition chamber equipped with a titanium target, inside the reaction chamber Supplying an activating gas containing hydrogen to the reactor and applying an electric field to make the inside of the reaction chamber into a plasma atmosphere; depositing a hydrogen saturated titanium compound generated by colliding the activated gas ions with the titanium target on the surface of the semiconductor substrate to produce a hydrogen saturated titanium compound Forming a thin film.
본 발명에 따른 반도체 소자의 금속막 증착 방법의 다른 실시예는 반도체 소자를 형성하기 위한 소정의 공정을 실시한 후 티타늄 성분을 포함한 박막을 증착할 반도체 기판을 수소 포화 티타늄 타겟이 장착된 증착 챔버에 장착되는 단계, 반응 챔버 내부에 활성화 가스를 공급한 후 전계를 인가하여 반응 챔버 내부를 플라즈마 분위기로 만드는 단계, 활성화 가스 이온을 수소 포화 티타늄 타겟에 충돌시켜 발생한 수소 포화 티타늄 화합물을 반도체 기판의 표면에 증착시켜 수소 포화 티타늄 화합물 박막을 형성하는 단계로 이루어진다.According to another embodiment of the method for depositing a metal film of a semiconductor device according to the present invention, after performing a predetermined process for forming a semiconductor device, a semiconductor substrate for depositing a thin film including a titanium component is mounted in a deposition chamber equipped with a hydrogen saturated titanium target. The method includes the steps of: supplying an activation gas into the reaction chamber and applying an electric field to make the inside of the reaction chamber into a plasma atmosphere; depositing a hydrogen saturated titanium compound generated by colliding the activation gas ions with a hydrogen saturated titanium target on the surface of the semiconductor substrate To form a hydrogen-saturated titanium compound thin film.
수소 포화 티타늄 타겟은 티타늄 파우더로 티타늄 잉곳을 제조한 후 수소 분위기에서 열처리한 뒤 잉곳을 소정의 크기로 잘라서 제조하거나, 수소 분위기에서 티타늄 파우더로 티타늄 잉곳을 제조한 뒤 잉곳을 소정의 크기로 잘라서 제조한다.Hydrogen saturated titanium target is manufactured by manufacturing titanium ingot with titanium powder and heat treatment in hydrogen atmosphere and then cutting the ingot to a certain size, or by manufacturing titanium ingot with titanium powder in hydrogen atmosphere and then cutting the ingot to predetermined size do.
활성화 가스는 수소 가스, 수소+아르곤 또는 수소+질소 혼합 가스이다. 수소 포화 티타늄 화합물의 화학식은 TixHy이며, 수소 포화 티타늄 화합물 박막은 티타늄막 또는 티타늄 질화막이다.The activating gas is hydrogen gas, hydrogen + argon or hydrogen + nitrogen mixed gas. The chemical formula of the hydrogen saturated titanium compound is TixHy, and the hydrogen saturated titanium compound thin film is a titanium film or a titanium nitride film.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.
도 1은 본 발명에 따른 반도체 소자의 금속막 증착 방법을 설명하기 위하여 도시한 공정의 계략도이다. 도 2는 도 1에서 사용되는 금속 타겟의 제작 과정을 설명하기 위하여 도시한 공정의 계략도이다.1 is a schematic diagram of a process shown for explaining a metal film deposition method of a semiconductor device according to the present invention. FIG. 2 is a schematic diagram of a process illustrated to explain a manufacturing process of the metal target used in FIG. 1.
본 발명에서는 반도체 기판에 금속막을 증착하되 수소 포화 금속막을 증착하는 방법으로 2가지 방법을 제시한다.In the present invention, two methods are proposed as a method of depositing a metal film on a semiconductor substrate and depositing a hydrogen saturated metal film.
첫 번째 방법은 도 1에서 도시한 일반적인 금속막을 증착하는 스퍼터링 장비에서 수소 포화 티타늄막을 증착시키는 방법이다.The first method is a method of depositing a hydrogen saturated titanium film in the sputtering equipment for depositing the general metal film shown in FIG.
도 1을 참조하면, 먼저 진공 펌프(20)가 구비된 고진공의 스퍼터링 챔버(10)로 각각의 제 1 및 제 2 공급 라인(11 및 12)을 통해 Ar 가스와 H2가스를 일정 비율로 주입하면, 일정한 열이 인가된 스퍼터링 챔버(10) 내부의 티타늄 타겟(30) 표면에서 수소와 티타늄과의 반응물이 생성된다. 이때, 전계를 인가하면 플라즈마가 발생한다. 플라즈마가 발생되면 아르곤 이온과 수소 이온이 음극을 형성한 티타늄 타겟 표면에 충돌하게되고, 티타늄 화합물(TixHy)이 반도체 기판(1)의 표면에 증착되어 수소 포화 티타늄막이 형성된다.Referring to FIG. 1, the Ar gas and the H 2 gas are first injected into the high vacuum sputtering chamber 10 having the vacuum pump 20 through the first and second supply lines 11 and 12, respectively. When reacted with hydrogen, titanium reacts with the surface of the titanium target 30 inside the sputtering chamber 10 to which a constant heat is applied. At this time, when an electric field is applied, plasma is generated. When plasma is generated, argon ions and hydrogen ions collide with the titanium target surface on which the cathode is formed, and a titanium compound (Ti x H y ) is deposited on the surface of the semiconductor substrate 1 to form a hydrogen saturated titanium film.
두 번째 방법은 도 1에서 도시한 금속막 증착시 소오스로 사용하는 금속 타겟을 수소 포화 금속 타켓으로 만들어 증착 공정을 실시하는 방법이다. 이때, 금속 물질로는 티타늄을 사용한다.The second method is a method of depositing a metal target used as a source when depositing a metal film as shown in FIG. 1 as a hydrogen saturated metal target. In this case, titanium is used as the metal material.
도 2를 참조하면, 금속 잉곳(Ingot) 제조 장비(40)에서 제조되는 금속 잉곳은 슬라이스 과정을 거쳐 스퍼터링 공정의 타겟 물질로 사용된다. 이때, 금속 잉곳 제조 장비(40) 내부로는 티타늄 파우더(Ti powder)를 소오스로 공급하여 잉곳(31)을 제조한다. 이후 열처리하는 과정에서 수소 가스를 공급해 준다. 티타늄은 수소와 쉽게 결합하는 특성이 있다. 따라서, 상기와 같이 잉곳을 제조한 후 수소 분위기에서 열처리를 실시하거나, 또는 잉곳을 제조하는 과정에서 수소 가스를 공급하여 주면 수소 포화 티타늄 잉곳을 제조할 수 있다. 이후 슬라이스 공정에 의해 소정의 크기로 나뉘어진 수소 포화 티타늄을 타켓으로 사용하여 스퍼터링 증착 장비에서 증착 공정을 실시하여 반도체 기판에 수소 포화 티타늄막을 형성한다.Referring to FIG. 2, the metal ingot manufactured in the metal ingot manufacturing equipment 40 is used as a target material of the sputtering process through a slicing process. At this time, the metal ingot manufacturing equipment 40 to supply the titanium powder (Ti powder) to the source to manufacture the ingot 31. After the heat treatment is supplied with hydrogen gas. Titanium has the property of easily bonding with hydrogen. Therefore, after the ingot is manufactured as described above, heat treatment is performed in a hydrogen atmosphere, or when hydrogen gas is supplied in the process of manufacturing the ingot, a hydrogen saturated titanium ingot may be manufactured. Subsequently, using a hydrogen saturated titanium divided into a predetermined size by a slice process as a target, a deposition process is performed in a sputtering deposition apparatus to form a hydrogen saturated titanium film on a semiconductor substrate.
상기와 같이, 금속 배선 형성 공정 또는 확산 방지막 형성 공정과 같은 티타늄막을 형성하는 모든 공정에 일반 티타늄막 대신에 수소 포화 티타늄막을 증착하여 수소 결합 능력을 저하시킴으로써 트랜지스터의 불안정한 격자 구조를 개선하기위하여 수소 분위기로 열처리하는 과정에서 수소 원자가 티타늄에 의해 포획되는 양을 최소화하여 격자 구조 개선 효과를 증대시킨다.As described above, in order to improve the unstable lattice structure of the transistor by depositing a hydrogen-saturated titanium film instead of the normal titanium film in all processes of forming a titanium film such as a metal wiring forming process or a diffusion barrier film forming process to reduce the hydrogen bonding ability. In the process of heat treatment by minimizing the amount of hydrogen atoms trapped by titanium to increase the lattice structure improvement effect.
상술한 바와 같이, 본 발명은 일반 티타늄막 대신에 수소 포화 티타늄막을 증착함으로써 수소 원자가 티타늄에 의해 포획되는 양을 최소화하여 격자 구조 개선 효과를 증대시킴으로써 문턱 전압을 안정화시키고, 리프레시 특성을 개선시켜 소자의 전기적 특성을 향상시키는 효과가 있다.As described above, the present invention minimizes the amount of hydrogen atoms trapped by titanium by depositing a hydrogen saturated titanium film instead of a general titanium film, thereby increasing the lattice structure improving effect, stabilizing a threshold voltage, and improving refresh characteristics. There is an effect of improving the electrical properties.
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US5298112A (en) * | 1987-08-28 | 1994-03-29 | Kabushiki Kaisha Toshiba | Method for removing composite attached to material by dry etching |
KR950024342A (en) * | 1994-01-14 | 1995-08-21 | 김광호 | Manufacturing method of semiconductor device |
KR980005367A (en) * | 1996-06-27 | 1998-03-30 | 김주용 | Method of forming titanium carbide nitride film |
KR19990007978A (en) * | 1996-02-23 | 1999-01-25 | 제임스엠.윌리암스 | Method of manufacturing integrated circuit using titanium hydride |
JP2000328245A (en) * | 1999-02-11 | 2000-11-28 | Applied Materials Inc | Method for performing titanium/titanium nitride integration |
-
2000
- 2000-12-27 KR KR1020000083200A patent/KR20020053541A/en not_active Application Discontinuation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5298112A (en) * | 1987-08-28 | 1994-03-29 | Kabushiki Kaisha Toshiba | Method for removing composite attached to material by dry etching |
KR950024342A (en) * | 1994-01-14 | 1995-08-21 | 김광호 | Manufacturing method of semiconductor device |
KR19990007978A (en) * | 1996-02-23 | 1999-01-25 | 제임스엠.윌리암스 | Method of manufacturing integrated circuit using titanium hydride |
KR980005367A (en) * | 1996-06-27 | 1998-03-30 | 김주용 | Method of forming titanium carbide nitride film |
JP2000328245A (en) * | 1999-02-11 | 2000-11-28 | Applied Materials Inc | Method for performing titanium/titanium nitride integration |
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