KR20020052045A - Data processing device - Google Patents

Abstract

PURPOSE: A data processor is provided to improve the receiving processing speed of a CPU by using the full data line of the CPU. CONSTITUTION: The data processor is for data transmission and reception between the nodes(300,400) having the CPU(302). The frames sequentially provided from a specific node are stored sequentially in many storage units. The CPU processes the frames stored in the storage units by reading simultaneously. A packet control logic(328) provides the write clocks to the storage units. The packet control logic includes the first logic to count the clocks indicating the frame transmission, the second logic to generate signals corresponding the frames with the storage units, the third logic to output the signals of the second logic by delaying, and the fourth logic to output write clocks for the storage units by AND-gating the outputs of the second and third logics. The packet control logic generates signals indicating a frame transmission terminating point and dummy data through the signals. The dummy data are stored in the rest storage units.

Description

DATA PROCESSING DEVICE}

The present invention relates to data transmission and reception technology between nodes having a central processing unit (hereinafter referred to as a CPU), and in particular, when there is more data that a CPU can process than data that can be transmitted and received by a node and a node. The present invention relates to a data processing apparatus capable of effectively processing.

In order to improve data efficiency, data transmission and reception between nodes having a CPU are bundled and transmitted in a single frame. The data transmission / reception method includes adding and receiving signals indicating a start and an end to a frame and a handshake signal, or transmitting and receiving a fixed size of data stored in the frame.

In general, the number of bytes of data that the CPU can process in one cycle is larger than the number of bytes of data transmitted and received once between the nodes. However, since the number of bytes of data that the CPU can process in one cycle depends on the bandwidth between the two nodes, that is, the number of bytes, the CPU could not process the data efficiently. In other words, a CPU having a 32-bit data line processes one byte per cycle for data received in eight bits and two bytes per cycle for data received in 16 bits. In the best case, the CPU is able to process 4 bytes per cycle, but configuring a backboard for this requires a lot of physical signals, and since the frame is sent in multiples of 4, the length information must be included in the frame. CPUs also typically have a memory for buffering for spike data.

A conventional data transmission / reception method will now be described with reference to FIG. The first node 100 and the second node 200 are nodes having a CPU. Since the data transmission / reception functions of the two nodes 100 and 200 are the same, only the data transmission / reception function of the first node 100 will be described in detail. When transmitting data, the CPU 102 transmits a START_FLAG indicating the data transmission start time to the target node through the packet control logic 112. Thereafter, data corresponding to the prescribed bandwidth with the target node is configured into a frame and transmitted to the target node through the buffer 106, the FIFO unit 108, and the buffer 110. The CPU 102 outputs a PRWR signal indicating that data exists while transmitting data. When the last data is transmitted, the CPU 102 provides the target node with an END_FLAG indicating an end point.

The received data is sequentially stored in the FIFO unit 112 through the buffer 114. The controller 102 reads and processes the sequentially stored data.

As described above, in order to increase the efficiency of data transmission and reception between a node having a CPU and a node, a plurality of pieces of data are bundled and transmitted in a single frame. However, if the number of bytes of data that the CPU can process in one cycle is greater than the number of bytes of data transmitted and received between the node and the node once, the number of data that the CPU can process in one cycle depends on the bandwidth between the two nodes. Done. Therefore, a CPU with a 32-bit data line (4BYTES) reads one byte for one cycle of packet data received in eight bits and two bytes for one cycle of data received in eight bits. If processing is required, there is a problem in that the full data line of the CPU cannot be used. In this case, there was a problem that the CPU selects a faster IC or requires one more board.

Accordingly, an object of the present invention is to solve the above-mentioned problems of the related art, and to provide a data processing apparatus capable of improving the CPU's reception processing speed by enabling the full data line of the CPU.

1 is a block diagram of a conventional data processing apparatus.

2 is a block diagram of a data processing apparatus according to a preferred embodiment of the present invention.

3 is a block diagram of logic for generating a data write clock.

4 is a timing diagram of FIG. 3.

5 is a block diagram of logic for generating dummy data.

6 is a timing diagram of FIG. 5.

<Explanation of symbols for important parts of the drawing>

300, 400: nodes

302: CPU

314, 320: FIFO section

322: buffer

The present invention for achieving the above object is a plurality of storage unit for sequentially storing the frames sequentially provided from any one node, a CPU for simultaneously reading and processing the frames stored in the plurality of storage units, and And a packet control logic for providing a write clock to a storage unit of the controller.

Hereinafter, with reference to the accompanying drawings will be described the configuration and operation of the present invention.

Hereinafter, a preferred embodiment of the present invention, which is applicable to a node and a device for transmitting and receiving 1 byte of data through a back board, will be described. In particular, the node has a CPU capable of processing 4 bytes of data.

The embodiment sequentially stores data received in 8 bits through the backboard in four independent FIFO units, and allows the CPU to simultaneously read and process data stored in the four independent FIFO units. As a result, the CPU can process 4 bytes of data in one cycle.

A data processing apparatus according to a preferred embodiment of the present invention will be described with reference to FIG.

The first node 300 and the second node 400 have a CPU. Since the data transmission / reception functions of the two nodes 300 and 400 are the same, only the data transmission / reception function of the first node 300 will be described in detail.

The first node 300 includes first to fourth FIFO units 314 to 320 that sequentially store 8-bit data received through the back board. Referring again to the order of the data stored in the first to fourth FIFO unit (314 to 320), the first data is stored in the first FIFO unit 314, the second data is stored in the second FIFO unit 316 The third data is stored in the third FIFO unit 318, the fourth data is stored in the fourth FIFO unit 320, and the fifth data is stored in the first FIFO unit 314. The CPU 302 of the first node 300 simultaneously processes data of 4 bytes by reading data stored in the first to fourth FIFO units 314 to 320. The first node 300 includes a buffer 322 for buffering between the backboard and the first to fourth FIFO units 314 to 320, and between the CPU 302 and the first to fourth FIFO units 314 to 320. First to fourth BI buffers 306 to 312 for buffering. The fourth BI buffer 312 provides eight bits of data to be transmitted by the CPU 302 to the fifth FIFO unit 324, and the data is transmitted to the target node through the backboard. The node 300 includes a buffer 326 for buffering between the fifth FIFO unit 324 and the backboard.

The packet control logic 328 is responsible for normal packet control, generates a clock for writing data to the first to fourth FIFO units 314 to 320, and also dummy data according to a preferred embodiment of the present invention. May be provided to the second to fourth FIFO units 316 to 320.

When the operation of the packet control logic 328 is described in more detail, the packet control logic 328 indicates that the START_FLAG representing the start point and the END_FLAG representing the end point and the data are loaded on the packet bus data line. A write clock for sequentially writing one byte of data input through the backboard to the first to fourth FIFO units 314 to 320 is generated using the PRWR.

Referring to Figure 3 showing the configuration of the write clock generation logic for this,

The first logic 500 counts PRWR as a clock to output a count value and is reset every time START_FLAG is input. The output of the first logic 500 is provided to the second logic 502. The second logic 502 analyzes the count value and outputs the signals corresponding to the first to fourth FIFO units 314 to 320 to provide to the third logic 504 and the fourth logic 506. The outputs are FSM0, FSM1, FSM2, and FSM3 shown in FIG. The third logic 504 outputs the FSM0, FSM1, FSM2, and FSM3 in synchronization with the inverted PRWR. These outputs are Q0_OUT, Q1_OUT, Q2_OUT and Q3_OUT shown in FIG. 4, which are input to the fourth logic 506. The fourth logic 506 generates and outputs a light clock for providing the FSM0, FSM1, FSM2, FSM3 and Q0_OUT, Q1_OUT, Q2_OUT, and Q3_OUT to the first to fourth FIFO units 314 to 320, respectively. . These write clocks are FSM0 & Q0_OUT, FSM1 & Q1_OUT, FSM2 & Q2_OUT, FSM3 & Q3_OUT shown in FIG.

In the case of a frame having an instantaneous bandwidth of 1 byte, the frame is not divided into 4 bytes when the CPU 302 reads data. In this case, since the CPU 302 reads the data written to the first to fourth FIFO units 314 to 320 in association with the END_FLAG, the packet control logic 328 writes the dummy data to the remaining FIFO in conjunction with the END_FLAG. do.

The packet control logic 328 does not need to write the dummy data when the number of data bytes of the frame is divided by four, but otherwise the dummy data should be written.

Dummy data write logic for this purpose will be described with reference to FIG. 5.

The fifth logic 600 generates dummy data when the last data is received, and generates a reference signal by end gating END_FLAG and the light clock. That is, the fifth logic 600 generates a signal indicating a time point at which END_FLAG appears and provides it to the sixth logic 602. The output of the fifth logic 600 is QX_WRITE_1, QX_WRITE_2, QX_WRITE_3, QY_WRITE_2, QY_WRITE_3, and QZ_WRITE_3 shown in FIG. The sixth logic generates three dummy data X_1, Y_1, and Z_1 when there are three remaining FIFO parts through the reference signal, and generates two dummy data X_1 and Y_1 when the remaining FIFO parts are two, and the remaining FIFO. If the number is one, one dummy data X_1 is generated. The dummy data thus generated is written to the corresponding FIFO unit according to the write clock.

The seventh logic 604 generates and provides the PRXWR0, PRXWR1, PRXWR2, and PRXWR3 of FIG. 4 to the eighth logic 606 by AND-gating the dummy data and the write clock by gating the value and START_FLAG. The eighth logic 606 inverts the PRXWR0, PRXWR1, PRXWR2, and PRXWR3 to generate PRXWR_0, PRXWR_1, PRXWR_2, and PRXWR_3 shown in FIG.

The functions of the logics are as follows. Here,! Means NOT GATE, & means end gate (AND GATE), and # means OR GATE.

First logic: COUNTER ([FQ4..FQ7], [FQ0..FQ3], VCC, PRWR, PTCLK, VCC,! START_FLAG);

Second logic: FSM0 =! FQ0 &! FQ1; FSM1 = FQ0 &! FQ1; FSM2 =! FQ0 &FQ1; FSM3 = FQ0 &FQ1;

Third logic: FD21 (Q0_OUT, FSM0,! PRWR.PTCLK,! STATRT_FLAG);

FD21 (Q1_OUT, FSM1,! PRWR.PTCLK,! STATRT_FLAG);

FD21 (Q2_OUT, FSM2,! PRWR.PTCLK,! STATRT_FLAG);

FD21 (Q3_OUT, FSM3,! PRWR.PTCLK,! STATRT_FLAG);

4th logic: FIFO_0 = FSM0 & Q0_OUT, FIFO_1 = FSM1 & Q1_OUT,

FIFO_2 = FSM2 & Q2_OUT, FIFO_3 = FSM3 & Q3_OUT

Fifth logic: QX_WRITE_1 = FIFO_0 &END_FLAG;

QX_WRITE_2 = FIFO_0 &END_FLAG;

QX_WRITE_3 = FIFO_0 &END_FLAG;

QY_WRITE_2 = FIFO_1 &END_FLAG;

QY_WRITE_3 = FIFO_1 &END_FLAG;

QZ_WRITE_3 = FIFO_2 &END_FLAG;

Sixth logic: X_1 = QX_WRITE_1;

Y_2 = (QX_WRITE_2 # QY_WRITE_2);

Z_3 = (QX_WRITE_3 # QY-WRITE_3 # QZ_WRITE_3);

Seventh logic: PRXWR0 = ((FIFO_0) &START_FLAG);

PRXWR1 = ((FIFO_1 # X_1) &START_FLAG);

PRXWR2 = ((FIFO_2 # Y_2) &START_FLAG);

PRXWR3 = ((FIFO_3 # Z_3) &START_FLAG);

Eighth logic: PRXWR_0 =! ((FIFO_0) &START_FLAG);

PRXWR_1 =! ((FIFO_1 # X_1) &START_FLAG);

PRXWR_2 =! ((FIFO_2 # Y_2) &START_FLAG);

PRXWR_3 =! ((FIFO_3 # Z_3) &START_FLAG);

The data processing apparatus according to the present invention described above provides the following effects.

The CPU's full data line can be used between nodes, improving the CPU's receive processing speed. This saves money by eliminating expensive ICs with faster CPU speeds. In addition, cost savings can be achieved by eliminating the need for additional identical boards in the system configuration, and the system can be described simply.

Claims (3)

In the data processing device for transmitting and receiving data between the node and the node having a CPU, A plurality of storage units sequentially storing frames sequentially provided from any one node; A CPU which simultaneously reads and processes the frames stored in the plurality of storage units; And a packet control logic for providing a write clock to a plurality of storage units. The method of claim 1, wherein the packet control logic, A first logic for counting a clock indicating that a frame is being transmitted, A second logic for generating signals corresponding to the sequentially provided frames and the plurality of storage units by using the count value of the first logic; A third logic for delaying and outputting the signals of the second logic; And a logic for generating a write clock comprising a fourth logic for outputting write clocks to the plurality of storage units by end-gating the outputs of the third logic and the outputs of the second logic. Processing unit. The method of claim 1, wherein the packet control logic, And receiving the signals indicating the write clocks and the end of frame transmission, generating signals indicating the end of frame transmission, generating dummy data through the signals, and storing dummy data in the remaining storage unit. Characterized in that the data processing device.