KR20020051097A - High speed data channel receiver and method for power control in high speed data channel - Google Patents

Abstract

PURPOSE: A high-speed data channel receiver and a method for controlling the power of a high-speed data channel are provided to shorten time to update a threshold determined by an external loop. CONSTITUTION: A high-speed data channel receiver includes a receiving part(11), an A/D converter(12), a PN(Pseudo Noise) correlator(13), a traffic channel correlator(14), an SNR(Signal to Noise Ratio) estimator(16), and a comparator(19). The receiving part(11) receives an RF CDMA signal and downconverts it into an IF signal. The A/D converter(12) converts the signal filtered from the receiving part(11) into a baseband signal. The PN correlator(13) correlates the output of the A/D converter(12) with its own local PN code and outputs the correlated value to the traffic channel correlator(14) and a pilot filter(15). The traffic channel correlator(14) takes correlation with a Walsh code allocated to a relevant channel in order to restore the data of the relevant channel and the correlated value to a coherent detector(17) and the SNR estimator(16). The SNR estimator(16) obtains an interference using the output signal of the pilot filter(15), calculates the energy strength of signals received for a sub frame using the output signal of the traffic channel correlator(14), and estimates the SNR of the sub frame period. The comparator(19) compares the output signal of the SNR estimator(16) with a given threshold and outputs a sub frame quality indicator.

Description

HIGH SPEED DATA CHANNEL RECEIVER AND METHOD FOR POWER CONTROL IN HIGH SPEED DATA CHANNEL}

The present invention relates to a high speed data channel receiver and a power control method for a high speed data channel, and more particularly, to a high speed power control scheme for a channel having a frame size that is a multiple of the basic frame size.

Next-generation personal digital mobile communication systems based on CDMA technology use a wider bandwidth than conventional IS-95 (or JSTD-008) CDMA systems, and are increasing the transmission speed to enable multimedia services. Thus, the number of channels allocated to a user varies depending on the type of service.

For example, several channels to one user, such as a channel for transmitting at a low data rate such as voice, a channel for transmitting at a high data rate such as video, and a channel for transmitting control messages. This can be assigned at the same time. In addition, methods for quickly performing power control in the forward link have been proposed.

Fast closed loop power control is generally divided into two parts: an inner loop and an outer loop. The inner loop measures the received signal-to-noise ratio (SNR) received through the channel, and the outer loop measures the quality of service required for the channel using a frame quality indicator. Hereinafter, a power control threshold for maintaining the QoS is generated, and a power control bit is generated by comparing with the received SNR measured in the inner loop.

In the next generation CDMA mobile communication system, multiple dedicated channels are allocated to a user, but power control bits are not generated and transmitted for all dedicated channels.

That is, the power control bit is generated by performing an inner loop on only some channels for power control. The reason for this is that the power control bit can be transmitted by using an existing channel rather than using a dedicated channel to send power control bits for high-speed power control.

Thus, in the general case, the received SNR is measured for only one channel, and the power control bit is generated and transmitted using the received SNR. The base station receives the one power control bit and controls transmission power for all channels allocated to the user.

In a special case, the reception SNR is measured for some channels to generate and transmit a power control bit for each channel. In this case, the transmission rate at which the power control bits of all channels are transmitted has the same transmission rate as in the general case described above.

Therefore, when the transmission rate of the power control bits for N channels is the same as the transmission rate for the power control bits of each channel, and the transmission rate for transmitting the power control bits of one channel is R, the power for each channel The transmission rate of the control bits is reduced to R / N, which in turn reduces the power control rate.

One example of such a case is an IS-2000 system. The fast forward power control mode can be divided into three parts. The first estimates the received SNR for one forward basic channel (hereinafter referred to as FFC) or forward dedicated channel (hereinafter referred to as FDC) even if multiple channels are assigned to a user. It is.

As a result, one forward power control bit is generated for each Power Control Group (hereinafter referred to as PCG), and through the Primary Reverse Power Control Subchannel (hereinafter referred to as PRPCS) at 800bps. send.

Second, when multiple channels are assigned to a user, the channels are divided into two groups to estimate the received SNRs of two reference channels, generating two power control bits.

However, there is only one forward power control bit that can be transmitted per PCG over the reverse link. Thus, the two forward power control bits are transmitted at 400 (or 200) bps and 400 (or 600) bps through the PRPCS and Secondary Reverse Power Control Subchannel (hereinafter referred to as SRPCS), respectively. . And finally, it is a low speed forward link power control mode performed at 50 Hz with an erase indicator bit (hereinafter referred to as EIB) or a quality indicator bit (hereinafter referred to as QIB).

In these two cases, the EIB is transmitted when two or more frames are sent to the PRPCS. The EIB is assigned when there is data in the frame, and the QIB is assigned even when there is no data such as the control hold state. do.

The SNR measured in the inner loop is compared with a power control threshold determined by the outer loop to generate and transmit a power control bit. The power control threshold is an SNR that satisfies the corresponding QoS by the frame quality indicator for each frame. to be. For example, the outer loop power control method performs a cyclic redundancy code (CRC) check on the received frame to determine whether the current received frame is good or bad. The power control threshold is adjusted to maintain a target frame error rate (hereinafter, referred to as FER) by examining the history of the CRC check result and the CRC check result of the previous frame, that is, the frame error rate.

The up / down step size ratio K of the power control threshold is determined as K = (1 / F) -1 in accordance with the target frame error rate F. That is, for the 1% target frame error rate, the down step size becomes Δ / 99 when the up step size for raising the power control threshold is Δ.

Fast data with SRPCS enabled as described above, i.e., independently generating power control bits for the main inner power control loop and the auxiliary inner power control loop, and the frame period of the auxiliary inner loop power control loop is 40 ms or 80 ms. When the received SNR is measured for the channel, the outer loop updates the power control threshold using a frame quality indicator generated every 40 ms or 80 ms. Therefore, after the initialization of the power control threshold that satisfies the QoS of the outer loop is set, the time taken for the transmission power to reach a certain state by the power control takes longer than when having the 20 ms frame period.

An object of the present invention is to solve the above-mentioned problems of the prior art and to meet the above-mentioned expectations of the same industry, and to reduce the update time of the threshold determined by the outer loop. It is an object of the present invention to provide a power control method for a receiver and a high speed data channel.

1 illustrates a receiver structure of a high speed data channel.

2 is a diagram illustrating a process of performing an outer loop.

* Description of the symbols for the main parts of the drawings *

11: receiver 12: A / D converter

13: PN correlator 14: call channel correlator

15: pilot filter 16: SNR estimator

17 Coherent Detector 18 Decoded Bits

19: comparator

In order to achieve the above object, a high-speed data channel receiver according to an aspect of the present invention,

A receiving unit for receiving the RF CDMA signal and down converting the IF signal into an IF signal; An A / D converter for converting the signal filtered by the receiver into a baseband signal;

A PN correlator for outputting a value that correlates the output of the A / D converter with its local PN code to the traffic channel correlator and the pilot filter;

A traffic channel correlator which correlates the Walsh code assigned to the channel and outputs the value to the coherent detector and the SNR estimator to recover data of the channel;

An SNR estimator for estimating SNR during the subframe by obtaining interference using the output signal from the pilot filter and obtaining an energy intensity of a signal received during the subframe using the output signal from the traffic channel correlator;

And a comparator for outputting a sub frame quality indicator by comparing the output signal from the SNR estimator to a predetermined threshold.

In addition, the SNR estimator obtains energy for each PCG, accumulates during the PCG corresponding to the subframe, measures energy of the signal received during the subframe, and predicts noise using a signal provided from the pilot filter. The SNR received during the subframe is obtained, the subframe quality indicator is obtained by comparing with the threshold value, and the decoded bit and the subframe quality indicator are received to perform an outer loop.

Example

When SRPCS is activated in forward fast power control to detect SNR from the primary and secondary channels, if the secondary channel is a high-speed data channel and the frame interval is greater than 20ms, the subframe quality indicator is divided into N equal parts by PCG. Perform an outer loop using

For the remaining cases, the existing forward fast power control method is used. For example, if the frame interval is 80ms and the PCG interval is 1.25ms, there are 64 PCG intervals within 80ms. If N = 4, the interval L of one subframe becomes 16 PCG intervals.

In this case, in order to estimate the received SNR, the energy and the received interference for the corresponding channel should be estimated in the received signal. The received interference N _t can be obtained from the pilot channel. In addition, the energy for the corresponding channel among the received signals obtains the received energy for the interval of the subframe. First, the estimated energy for the high speed data channel Is estimated as in Equation 1.

In Equation 1 Is the energy of the traffic channel measured during PCGl, a _l is a value to give a suitable weight for the traffic channel energy determined in PCGl.

For example, the value of a _l is 1, the value of L is the number of PCGs in one subframe, and is obtained during one subframe. Is the cumulative value of. The value of a _l is a value considering the case where power control is performed to correct the received energy converted by the power control.

That is, E _b / N _t for the subframe of the fast data channel is as follows.

In Equation 2, k is a bit-to-symbol rate ratio of a high speed data channel, and Nt includes interference by another user in the same cell and interference by another user in another cell. The SNR for the received subframe obtained by Equation 2 is compared with the subframe quality threshold, and the result is the quality of the subframe.

In the outer loop, the sub-frame quality indicator is used to maintain the target FER as an SNR that satisfies the QoS by using the history of the sub-frame quality indicator until the CRC result is completely decoded. The power control threshold is adjusted for each subframe period.

Hereinafter, an operation of a receiver of a high speed data channel according to the present invention will be described with reference to the accompanying drawings.

1 shows a receiver structure of a high speed data channel. The received signal downconverts the RF CDMA signal to an IF signal through the receiver, filters the IF signal, and then makes a baseband digital signal through an A / D converter.

The PN correlator provides an output signal taken by correlating the local PN code generated from the local PN code generator with its A / D converter output as a traffic channel correlator and a pilot signal. In order to recover the data of the channel, the traffic channel correlator correlates the Walsh codes assigned to the channel and provides them to the coherent detector and the SNR estimator.

On the other hand, the signal provided to the pilot filter is low pass filtered through the pilot filter and its output is provided to the coherent detector and the SNR estimator for coherent detection. The SNR estimator performs the input received from the traffic channel correlator as shown in Equation 1.

That is, the energy for each PCG is obtained, and the energy of the signal received during the subframe is measured by accumulating for the PCG corresponding to the subframe. In addition, noise is predicted using the signal provided from the pilot filter.

Then, Equation 2 is used to find the SNR received during the subframe and compare it with the threshold to find the subframe quality indicator. Take the decoded bits and subframe quality indicator and perform the outer loop.

2 shows the execution of the outer loop. First, the channel on which the inner loop is performed is a high speed data channel, and the frame period of the channel should exceed 20 ms. When this condition is satisfied, the outer loop of FIG. 2 is performed, and if this condition is not satisfied, the outer loop is performed as described above.

As described above, in step 2, one frame is divided into N to generate a subframe quality indicator for each subframe. While the CRC result of the currently received frame does not exist, the outer loop is performed using the subframe quality indicator (step S4), and the up / down steps are Δ / N and Δ / (KN), respectively. (Step S5).

If there is a CRC result of the currently received frame, the flow proceeds to step S6. In step S6, when the N subframe quality indicators do not have the same value, the process proceeds to step S7 to use the CRC result. In operation S8, the outer loop is performed using the CRC result.

The up / down steps at that time are Δ-ΣAk and Δ / K. Here,? Ak represents the amount updated by the subframe quality indicator. However, if the N subframe quality indicators have the same value in step S6, the flow goes to step S9.

In step S9, if the result is the same as the CRC result, the process proceeds to step S10, where the up / down steps are Δ / N and Δ / (KN). Finally, step S11 is a part for adjusting the threshold value because the threshold value for all subframe indicators of the frame is not appropriate.

According to the high-speed data channel receiver and the power control method of the high-speed data channel according to the present invention described above, 40ms or 80ms for the case that the inner loop is performed on the high-speed data channel and the frame period exceeds 20ms at the same time It is possible to reduce the time for updating the threshold determined by the outer loop by performing the outer loop of power control by generating a subframe quality indicator by dividing by N equals.

Claims (3)

A receiving unit for receiving the RF CDMA signal and down converting the IF signal into an IF signal; An A / D converter converting the signal filtered by the receiving unit into a baseband signal; A PN correlator for outputting a value that correlates the output of the A / D converter with its local PN code to a traffic channel correlator and a pilot filter; A traffic channel correlator which correlates the Walsh code assigned to the channel and outputs the value to the coherent detector and the SNR estimator to recover data of the channel; An SNR estimator for estimating SNR during the subframe by obtaining interference using the output signal from the pilot filter and obtaining an energy intensity of a signal received during the subframe using the output signal from the traffic channel correlator; And a comparator for comparing the output signal from the SNR estimator to a predetermined threshold and outputting a sub frame quality indicator. 2. The high speed data channel receiver of claim 1, further comprising means for decoding the output from the coherent detector. In the power control method of a high speed data channel, a) dividing one frame into N and generating a subframe quality indicator for each subframe; b) determining whether a CRC result of the currently received frame exists; b-1) performing an outer loop using a subframe quality indicator if there is no CRC as a result of the determination; b-2) if the CRC exists, determining whether the N subframe quality indicators have the same value; c) using the CRC result if the determination result in step b-2) does not have the same N subframe quality indicators; d) if, as a result of the determination in step b-2), the N subframe quality indicators have the same value, determining whether the result has the same value as the CRC result; and e) adjusting a threshold for the sub frame quality indicator if the determination result in step d) is not equal to the CRC value.