KR20020049931A - Method of testing a flash memory device - Google Patents

Abstract

PURPOSE: A method for testing a flash memory device is provided, which removes an error cause which is fatal to the flash memory device by performing the test by applying different voltages to each bit line under a drain stress. CONSTITUTION: A drain(bit line) stress is applied using a test mode when performing a wafer test, and different voltages are applied to adjacent bit lines. That is, if a voltage of 6V is applied to one bit line, an adjacent bit line is grounded. Then, a gate(word line) and a source are grounded. For example, when designing a circuit, a voltage of 6V is applied to odd-numbered bit lines, and even-numbered bit lines are grounded. That is, the voltage of 6V is applied through a drain pump circuit and the first NMOS transistor connected to the odd-numbered bit line is selected according to a bit line selection signal(SBL), and the second NMOS transistor connected to the even-numbered bit line is driven according to a bit line selection bar signal(SBLb).

Description

Method of testing a flash memory device

The present invention relates to a test method of a flash memory device, and in particular, a word line and a source of a flash memory cell array are grounded, and a different voltage is applied to an adjacent bit line in a drain stress test in which a predetermined voltage is applied to the bit line. The present invention relates to a test method of a flash memory device for detecting a defect.

The present invention relates to a test method of a flash memory device capable of detecting and removing a cause of a defect in advance by applying a predetermined voltage and a ground voltage to each bit line alternately during a bit line stress test.

In order to test the flash memory device, the stress mode is used to detect retention and particles.

To perform these tests, a stress is applied to the flash memory cell array, which is divided into gate stress, drain stress, and source stress, depending on the stress conditions. The existing stress application method is as follows.

Gate stress grounds the source and drain (bitline) and applies 9V or -9V to the gate (wordline) for hundreds of milliseconds. Drain stress grounds the source and gate (word line) and applies a voltage of more than 6V to the drain for hundreds of milliseconds. The source stress method also grounds the drain and gate (word line) and applies a voltage of at least 6V to the source for hundreds of milliseconds.

In this case, a common bias is applied to the source and gate lines, and the same bias is applied to the drain.

In the conventional test method as described above, when the same bias is transmitted between the bit lines, there is no method of properly detecting a defect between bit lines. Such defects cause a problem of shorting the bit lines while causing breakdown with the thin oxide film by performing cycling at least 30 times because thin oxide films exist between the bit lines. For 30 cycles, the actual stress time the bit line receives is 215 ms (1 bit program time = 7 ms x 2 times x 512 cells x 30 cycles = 215 ms). It is grounded.

Therefore, such a defect cannot be detected because the same potential is maintained between bit lines under the conventional drain stress condition.

An object of the present invention is to provide a test method of a flash memory device that can remove the cause of failure that can be fatal to the flash memory device by performing a test by applying a different voltage to each bit line in the drain stress.

The present invention for achieving the above object is characterized in that the word line and the source of the flash memory cell array is grounded, respectively, the bit line is characterized by detecting a defect by applying a different voltage to the adjacent bit line.

1 is a schematic diagram of a memory cell array shown for explaining a test method of a flash memory device according to the present invention;

The present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic diagram of a memory cell array for explaining a test method of a flash memory device according to the present invention.

In the present invention, when the wafer test is performed, the drain (bit line) stress is applied using the test mode, and different voltages are applied to adjacent bit lines. In other words, applying a voltage of 6V to one bit line causes another adjacent bit line to ground. At this time, the gate (word line) and the source are grounded. For example, when designing a circuit, a voltage of 6V is applied to odd bit lines, and even bit lines are grounded. That is, a voltage of 6 V is applied through the drain pump circuit, but the first NMOS transistor N11 connected to the odd bit line is selected according to the bit line select signal SBL, and the second connected to the even bit line. The NMOS transistor is driven in accordance with the bit line select bar signal SBLb.

Contrary to the above, the bit line stress test may be performed by grounding the odd bit line and applying a voltage of 6 V to the even bit line.

As described above, when different stress voltages are applied to the bit lines, the same voltage may be applied to solve the problem in the conventional method in which a defect cannot be detected because no voltage difference occurs between the bit lines.

As described above, according to the present invention, defects can be more easily detected by applying a high voltage to the odd bit lines and grounding the even bit lines so that a potential difference exists between the bit lines.

Claims (2)

In the test method of a flash memory device, The word line and the source of the flash memory cell array are grounded, respectively, and the bit line detects a defect by applying a different voltage to an adjacent bit line. The test method of claim 1, wherein the voltages applied to the bit lines are 6V and 0V.