KR20020048819A - Switching Interface Between Switching Core and Line Port - Google Patents

Abstract

PURPOSE: A switching interface between a switching core apparatus and a line port apparatus is provided to apply transmission/exchange/copy functions and QoS between multi line ports. CONSTITUTION: A Tx direction signal line is TxData(7:0), TxAddr(4:0), TxSync, TxEnb, TxClk toward an Internet link(24) of a line port apparatus side from a switch engine(20) as a switching core apparatus side and TxStatus(4:0) toward the switch engine(20) as a switching core apparatus side from the Internet link(24) of a line port apparatus side. An input pin of the switching core apparatus is an inside pull down input pad and is connected to signal lines of TxSync and TxStatus(4:0). An output pin of the line port apparatus is a tri-state output pin and is connected to a signal line of TxStatus(4:0).

Description

Switching Interface Between Switching Core Device and Line Port Device {Switching Interface Between Switching Core and Line Port}

The present invention relates to a switching interface between a switching core device and a line port device. More specifically, the interface connecting the switching core device and the line port device includes a transmission / switching / copying function of a variable length packet and a quality of service between multiple line ports. It relates to a switching interface between a line core device and a switching core device that supports (QoS).

The switching interface is a physical connection structure and a logical operation model located between a switching core and a line port device.

The prior art of such a switching interface will be described with reference to the accompanying drawings, FIGS. 1 and 2.

The switching interface between the switching core device 10 and the line port device 14 has a large point-to-point structure and a bus structure.

In FIG. 1, the Ethernet switch controller 12 for processing an Ethernet frame uses MII and RMII interfaces as an industry standard.

MII and RMII have a point-to-point structure and provide a signal line in a 1: 1 form between the line port device 14 and the switching core device 10.

The point-to-point switching interface has a unique handshaking procedure between the switching core device 10 and the line port device 14, and transmits frames.

In the point-to-point structure, since there is no line port device 14 competing with each other, it does not have an arbiter, and the frame can be transmitted from the switching core device 10 to the line port device 14.

The frame may also be transmitted from the line port device 14 to the switching core device 10.

The frame is also transmitted to the switching core device 10 or the line port device 14 without waiting.

In FIG. 2, the bus structure is a structure in which a switching core device 10 and a plurality of line port devices 14 are simultaneously connected to a single physical signal line, and a bus protocol between the line port device 14 and the switching core device 10 is used. Only defined signal lines are provided.

In the bus interface switching interface, a plurality of line port devices 14 share a single physical signal line.

Bus operation can be divided into bus read operation, write operation, bus request operation, and bus arbitration operation.

Since the bus write operation causes a collision to the physical signal lines of the bus lines, many line port devices 14 cannot write at the same time.

Prior to the bus write operation, the line port device 14 requests a bus right from the bus arbiter 16, which performs a bus request operation and serves as a bus arbitration.

The bus arbiter 16 grants the bus use right to the specific line port device 14.

The line port device 14, which has received a bus license, performs a bus write operation to load data on the bus line.

Since the bus read operation does not collide with the physical signal line, any device connected to the bus line can read the frame.

For this reason, a series of procedures for selecting the destination line port device 14 in the bus write operation must be performed.

Unlike the point-to-point structure, frame waiting may occur in the switching core device 10 and the line port device 14.

However, in the conventional point-to-point structure, there is no frame waiting time, but the connection signal line overhead between the switching core device and the line port device increases, and there are many problems in the future expansion of the line port device and the connectivity of the heterogeneous line port device. .

This point-to-point architecture is designed to simplify the Ethernet PHY device. The design of a switching system (eg, DSLAM) located at the access point node of an access network affects the scalability of the system as well as the cost.

In addition, although the scalability of the line port device is large in the conventional bus structure, it is difficult to provide a quality of service (QoS) between the heterogeneous line port devices when the connection between the heterogeneous line port devices is large compared to the design complexity.

Switching systems located at the access point nodes of an access sex network have increased demands for the role of the Internetworking of different heterogeneous traffics, while the support for processing such heterogeneous traffic is different while supporting line port devices and OAM (Operation & Management) messages. Effective bands are sacrificed.

Moreover, the complexity of the bus arbiter becomes very high to ensure the capacity of the effective band being sacrificed.

As a result, when both a variable length packet forwarding, a fixed length packet forwarding, QoS support, OAM support, and scalability are considered simultaneously, both the point-to-point structure and the bus structure of the prior art have a weak effect compared to the cost.

The present invention has been made to solve the problem of connection line overhead between the switching core device and the line port device, line port scalability problem, heterogeneous line port connectivity problem, bus system complexity problem, OAM problem of the prior art, The interface between the switching core device and the line port device is to provide a switching interface between the switching core device and the line port device that can support the transmission / exchange / copy function of the variable length packet and QoS between multiple line ports.

1 is a structural diagram of a switching interface of a conventional point-to-point structure.

2 is a schematic diagram of a switching interface of a conventional bus structure.

3 is a physical connection diagram in the Tx direction between the switching core device and the line port device according to the present invention.

4 is a physical connection diagram in the Rx direction between the line port device and the switching core device according to the present invention.

5A is a logical operation and format in the Tx direction between a switching core device and a line port device according to the present invention.

5B is a signal flow diagram when transmitting the first fragmented packet segment in the Tx direction between the switching core device and the line port device according to the present invention.

FIG. 5C is a signal flowchart of a fragmented packet segment transmission in the Tx direction between the switching core device and the line port device according to the present invention.

FIG. 5D is a signal flow diagram of the last fragmented packet segment transmission in the Tx direction between the switching core device and the line port device according to the present invention.

Figure 6a is a logical operation and format in the Rx direction between the line port device and the switching core device according to the present invention.

FIG. 6B is a signal flow diagram when transmitting the first fragmented packet segment in the Rx direction between the line port device and the switching core device.

Fig. 6C is a signal flow diagram in progress of packet segment transmission in the Rx direction between the line port device and the switching core device.

FIG. 6D is a signal flow diagram when transmitting the last fragmented packet segment in the Rx direction between the line port device and the switching core device.

7 is a connection structure diagram for each service group as an application example of the present invention.

<Description of the symbols for the main parts of the drawings>

10: switching core device 12: Ethernet switch controller

14 Line Port Device 16 Bus Arbitrator

20: switch engine 24: Ethernet link

26a: Ethernet line card group

26b: ATM Line Card Group

26c: T-carrier line card group

28: line port ASIC device

30: routing header part 32, 40: routing command part

34,42: packet segment

Hereinafter, the present invention will be described with reference to FIGS. 3 to 7.

3 is a physical connection diagram in the Tx direction between the switching core device and the line port device according to the present invention.

4 is a physical connection diagram in the Rx direction between the line port device and the switching core device according to the present invention.

5A is a logical operation and format in the Tx direction between a switching core device and a line port device according to the present invention.

5B is a signal flow diagram when transmitting the first fragmented packet segment in the Tx direction between the switching core device and the line port device according to the present invention.

FIG. 5C is a signal flowchart of a fragmented packet segment transmission in the Tx direction between the switching core device and the line port device according to the present invention.

FIG. 5D is a signal flow diagram of the last fragmented packet segment transmission in the Tx direction between the switching core device and the line port device according to the present invention.

Figure 6a is a logical operation and format in the Rx direction between the line port device and the switching core device according to the present invention.

FIG. 6B is a signal flow diagram when transmitting the first fragmented packet segment in the Rx direction between the line port device and the switching core device.

Fig. 6C is a signal flow diagram in progress of packet segment transmission in the Rx direction between the line port device and the switching core device.

FIG. 6D is a signal flow diagram when transmitting the last fragmented packet segment in the Rx direction between the line port device and the switching core device.

7 is a connection structure diagram for each service group as an application example of the present invention.

The switching interface is a physical connection structure and a logical operation model located between a switching core and a line port device.

The packet flow of the switching core device has a switching core output flow (TxFlow) and an input flow (RxFlow).

The switching core output flow starts at the switching core device and terminates at the line port device.

The switching core input flow starts at the line port device and terminates at the switching core device.

In FIG. 3, in the physical connection structure of the switching interface according to the present invention, the Tx direction is defined as a signal line for controlling the switching core output flow.

Tx direction signal lines are TxData [7: 0], TxAddr [4: 0], TxSync, TxEnb, TxFeb, TxClk from the switch engine 20 on the switching core device side to the Internet link 24 on the line port device side, TxStatus [4: 0] from the Internet link 24 on the line port device side to the switch engine 20 on the switching core device side.

The input pin of the switching core connected to the signal lines TxSync, TxStatus [4: 0] is an internal pulldown input pad.

The output pin of the line port device connected to the signal line TxStatus [4: 0] is a tri-state output pad.

In order to support the hot-swap function of the line port device, the line port device should be in the stop mode and the output pins TxStatus [4: 0] should be in the Hi-Z state.

Only after TxAddr [4: 0] and the line port device address provided by the switching core device are the same more than once, the Hi-Z state is cleared and can be converted to the normal operation mode.

In the physical connection structure of the switching interface according to the present invention of FIG. 4, the Rx direction is defined as a signal line for controlling the switching core input flow.

The Rx direction signal lines are RxData [7: 0], RxStatus [4: 0], RxSync, RxFeb and the switching core device side from the Ethernet link 24 on the line port device side to the switch engine 20 on the switching core device side. RxAddr [4: 0], RxEnb, and RxClk from the switch engine 20 to the Ethernet link 24 on the line port device side.

The input pin of the switching core connected to the signal lines RxData [7: 0], RxStatus [4: 0] and RxSync is an internal pulldown input pad.

The output pins of the line port device connected to the signal lines RxSync, RxData [7: 0], and RxStatus [4: 0] are tri-state output pads.

To support the hot-swap function of the line port device, the line port device must be in stop mode and the initial values of the output pins RxSync, RxData [7: 0], and RxStatus [4: 0] must be in Hi-Z state.

Only after the RxAddr [4: 0] and the line port device address provided by the switching core device are the same more than two times, the Hi-Z state is cleared and can be changed to the normal operation mode.

In order to handle the output (input) flow in the logical operation model of the switching interface, the Tx (Rx) direction signal line has a unique data format and handshaking procedure between the switching core device and the line port device.

In FIG. 5A, the data format in the Tx direction includes a routing header part 30, a routing command part 32, and a packet segment part 34.

The routing header portion 30 in the Tx direction is variable depending on the address range of the line port device.

If the address range is 0-7, the routing header part 30 of one clock is used, and if the address range is 0-15, two routing header parts 30 are used.

The routing header unit 30 determines the line port device to receive the packet segment in the Tx direction according to the unique position of the bit value of the routing header unit 30.

The relation between the routing header section 30 and the line port device address is TxData_RH (k) [I] = 1, k = residual (LinemaAdd (LinePortAddr, TxData Bus Width)), I = modulo (LinePortAddr, TxData Bus Width) )) to be.

TxData_RH (k) [I] indicates the routing header section 30 bit string I of the k-th clock in the TxData signal line.

LinePortAddr is a unique address of the line port device.

The Remainder and Modulo functions return integer and quotient values with integer operators.

When a broadcast packet is transmitted, every bit string value of the routing header section 30 has a value of 1.

When a multicast packet is transmitted, a bit string value of a predetermined group of the routing header unit 30 has a value of 1.

The routing command unit 32 in the Tx direction occupies two clocks and is composed of a routing command operation code 32a and a routing command variable 32b.

The routing command action code 32a is a command set for the switching core device to control the line port device.

Routing command variable 32b is a specific variable parameter value for the command set.

The command operation code 32a and the command variable 32b of the routing command unit 32 may be defined and used by a user.

The packet segment part 34 in the Tx direction occupies 64 clocks and is a basic transmission unit fragmenting a variable length packet into 64 bytes.

In FIG. 5B, transmission of variable length packets is performed by continuous packet segment transmission, and a packet segment virtual circuit is formed between the switching core device and the line port device while one variable length packet is transmitted.

In FIG. 5C, the packet segment virtual circuit occupies the switching core device and the line port device while the variable length packet is transmitted.

In FIG. 5D, the packet segment virtual circuit is disconnected after the variable length packet finishes transmission.

The packet segment part 34 is transmitted to all the line port devices, and the line port device selectively receives the packet segment with reference to the routing header part 30 provided by the switching core device.

In the logical operation model of the switching interface, the handshaking procedure of the Tx direction signal line for processing the output flow is handled by a line port state check operation and a packet segment transmission operation.

5B, 5C, and 5D show a Tx direction signal flowchart.

A variable length packet transmission process from one switching core device to the line port device-1 will be described over time.

The Tx direction signal lines associated with the line port status check operation are TxAddr and TxStatus.

The line port state check operation transfers TxAddr from the switching core device to the line port device.

When the line port device checks the TxAddr value corresponding to its own address, the line port device transmits the status (eg, buffer storage space) inside the line port to TxStatus.

If the line port device does not match its own address, the output of TxStatus outputs a Hi-Z status.

The switching core device cannot define TxAddr = 31 as a null address and use it as a unique address of the line port device.

The switching core device performs the TxAddr generation in parallel with the packet segment transmission operation in two clock cycles with pairs of null addresses and lineport addresses.

Signal lines associated with the packet segment transmission operation are TxSync, TxFeb, TxEnb, and TxData.

TxSync = 1 indicates the start of transmission of the packet segment, and the switching core device delivers TxSync = 1 at the routing header portion 30 position.

The switching core device collects / analyzes the line port information capable of receiving the variable length packet by the line port state check operation, and then transmits the packet segment by adding the routing header.

TxFeb indicates the valid byte end of the first fragmented packet segment and the last fragmented packet segment when the variable length packet is fragmented and transmitted to the switching core device and the lineport device.

The first fragment of the packet segment has a size of 64 bytes or more, and the switching core device transmits TxFeb = 1 at the position of the routing command variable 32b of the Tx direction signal data format.

The fragmented packet segment including the end of the packet has a size of 64 bytes or less, and the switching core device transmits TxFeb = 1 at the effective byte end position of the Tx direction packet segment part 34 variable length packet.

The switching core device delivers TxFeb = 0 during packet segment transmission except for the first and last fragmented packet segments.

TxEnb delivers TxEnb = 1 regardless of the data format position when the switching core device wants to pause transmission during packet segment transmission.

Under other conditions, the switching core device delivers TxEnb = 0.

TxData is a busline for delivering routing headers, routing commands, and packet segments from the switching core device to the lineport device.

The routing header section 30 varies depending on the address range of the line port device, but the routing command section 32 and the packet segment section 34 are fixed.

At the time of the last fragmented packet segment transmission, the invalid packet byte value is delivered filled with an arbitrary value (value 0 recommended).

In FIG. 6A, the data format in the Rx direction includes a routing command unit 40 and a packet segment unit 42.

The routing command unit 40 in the Rx direction occupies two clocks and includes a routing command operation code 40a and a routing command variable 40b.

The routing command operation code 40a is a command set for the line port device to transmit its state and command execution result to the switching core device.

Routing command variable 40b is a specific variable parameter value for the command set.

The command operation code 40a and the command variable 40b of the routing command unit 40 may be defined and used by a user.

The packet segment section 42 in the Rx direction occupies 64 clocks and is a basic transmission unit that fragments a variable length packet into 64 bytes.

In FIG. 6B, the transmission of the variable length packet is performed by continuous packet segment transmission, and a packet segment virtual circuit is formed between the line port device and the switch core device while one variable length packet is transmitted.

In FIG. 6C, the packet segment virtual circuit occupies the line port device and the switching core device while the variable length packet is transmitted.

In FIG. 6D, the packet segment virtual circuit is disconnected after the variable length packet finishes transmission.

The virtual circuit of the packet segment part 42 is set by the switching core device.

In the logical operation model of the switching interface, the handshaking procedure of the Rx direction signal line for processing the input flow is processed by the line port state check operation and the packet segment transmission operation.

6B, 6C and 6D show Rx direction signal flow diagrams.

One switching core device selects the line port device-1 to explain a variable length packet transmission process to the switching core device over time.

Rx direction signal lines associated with the line port status check operation are RxAddr and RxStatus.

The line port status check operation passes the RxAddr from the switching core device to the line port device.

When the line port device checks the RxAddr value corresponding to its own address, the line port device transmits the status (eg, buffer storage space) inside the line port to RxStatus.

If the line port device does not match its own address, the output of RxStatus outputs a Hi-Z status.

The switching core device cannot define RxAddr = 31 as a null address and use it as a unique address of the line port device.

The switching core device performs the RxAddr generation in parallel with the packet segment transmission operation in two clock cycles in pairs of null addresses and lineport addresses.

Signal lines associated with the packet segment transmission operation are RxSync, RxFeb, RxEnb, and RxData.

RxSync = 1 indicates the start of transmission of the packet segment, and the line port device delivers RxSync = 1 at the routing command unit 40 position.

RxFeb indicates the effective byte end of the first fragmented packet segment and the last fragmented packet segment when the variable length packet is fragmented and transmitted from the lineport device to the switching core device.

The first fragment of the packet segment has a size of 64 bytes or more, and the line port device delivers RxFeb = 1 at the position of the routing command variable 40b of the Rx direction signal data format.

The fragmented packet segment including the end of the packet has a size of 64 bytes or less, and the RxFeb = 1 is transmitted by the line port apparatus at the effective byte end position of the Rx direction packet segment section 42 variable length packet.

The lineport device sends RxFeb = 0 during packet segment transmission except for the first and last fragmented packet segments.

RxEnb drops to RxEnb = 1-> 0 when the switching core device allows RxData transmission of the line port device.

When the line port device matches the currently received RxAddr and its own address, when RxEnb = 1, the line port device enters a preparation stage for transmission.

When the line port device is ready to transmit, RxEnb = 0, the line port device may transmit RxData to the switching core device.

The switching core device may suspend packet segment transmission with RxEnb = 1 during RxData reception.

However, the switching core device must reselect the suspended line port device.

RxData is a busline for delivering routing commands and packet segments from the lineport device to the switching core device.

The routing command section 40 and the packet segment section 42 are fixed in size.

At the time of the last fragmented packet segment transmission, the invalid packet byte value is delivered filled with an arbitrary value (value 0 recommended).

The RxData of the line port device not selected by the switching core device must be in the Hi-Z state.

A packet transmission / switching / group transmission method will be described based on the physical connection structure and the logical operation model of the switching interface of the present invention.

The packet flow of the switching core device has a switching core output flow (TxFlow) and an input flow (RxFlow).

The switching core output flow starts at the switching core device and terminates at the line port device.

The switching core input flow starts at the line port device and terminates at the switching core device.

The transmission function of the switching packet is performed by each switching output flow and input flow occurring between the switching core device and the line port device.

When transmitting a variable length packet, a plurality of packet segment transmissions occur.

The switching core device collects / analyzes the internal state of the line port device through a line port state check operation, and transmits packet segments by adjusting a required band on a line port basis in the switching core device.

While the variable length packet is transmitted, the virtual circuit at the packet segment level is set, and when the variable length packet transmission is completed, the virtual circuit is disconnected.

The switching function of the switching packet is performed by two-tuple of switching input flow and switching output flow.

The packet generated at any line port-1 is transferred to the switching core as the switching input flow-1, and the switching core searches for the destination line port and transmits the packet to the line port device in the flow of the switching output port-2.

This series of processes is packet exchange.

The function of copying the switching packet includes switching input flow, switching output flow-1, switching output flow-2,... , N + 1 pairs (n-tuple) of switching output flow-n.

Packets originating at any line port-1 are forwarded to the switching core as switching input flow-1, which searches for the destination lineport.

If the searched destination line port is not a single line port, but a plurality of grouped line ports, the switching core copies the packet segment to output flow-1 and output flow-2 directed to lineport-1 and lineport-2. Send a packet segment to a lineport device in a specific group.

This series of procedures is called packet multicasting.

During the packet group transmission, n logical output flows from the switching core device to the line port device are treated as m physical output flows in the switching interface.

Where n >> m 1

The switching interface according to the present invention adjusts the service period from the switching core to the line port to provide QoS between the multiple line ports.

It can handle the flow of variable length packets between the switching core device and the line port device.

In addition, by setting a packet segment level virtual circuit between the switching core device and the line port device, different line port devices may operate with the switching core device regardless of the packet length.

That is, an Ethernet frame flow may be processed between the switching core device and the line port device-1, and an ATM cell flow may be processed between the switching core device and the line port device-2.

In addition, by adjusting the QoS support function between line ports, service priority may be provided to Line Port-2 where ATM cell flow is processed rather than Ethernet frame flow.

The present invention provides a switching interface structure that enhances the scalability, connectivity, complexity, and OAM problem of a line port device requiring a different traffic bandwidth characteristic from that of a switching core device. It is best to apply.

In addition, the present invention can be applied to the connection structure between the line card PCB, the connection structure between a single port inside the line card PCB, the multi-port device ASIC connection structure inside the line card PCB.

The IN structure of the access sex network system has a multi-point connection structure between a low speed line card device and a switching core device.

The multi-point connection structure has a line overhead problem, and the bus method is adopted as this alternative.

However, the bus method increases the design complexity problem of the line port device, and the transmission service according to the traffic requirements between heterogeneous line cards is difficult.

In FIG. 7, the system implementation model to which the present invention is applied is connected to one switching core device and a plurality of heterogeneous line port devices.

In Fig. 7, an Ethernet line card group 26a for processing the switch engine 20 on the switching core device side and an Ethernet frame on the line port device side, an ATM line card group 26b for processing the ATM cell, and a plurality of low-speed T- It consists of the T-carrier line card group 26c connected with the line port ASIC device 28 which concentrates one service.

The lineport ASIC device 28 providing T-1 service has integrated a number of T-1 ports.

In this case, in the switching interface of the present invention, TxAddr and RxAddr should allocate addresses as many as T-1 ports in the ASIC device 28.

The ATM line card group 26b which processes ATM cells allocates TxAddr and RxAddr addresses as many as ATM cell line cards.

The Ethernet line card group 26a which processes the Ethernet frame allocates TxAddr and RxAddr addresses as many as the number of Ethernet line cards.

The switching core apparatus assigns service priority to the T-carrier line card group 26c, the ATM line card group 26b, and the Ethernet line card group 26a according to the quality of service requirements.

That is, the switching core device changes the line port state check operation and the packet segment transmission period, assigns and processes the highest priority to the T-1 service requiring the circuit service, and provides a new circuit service during operation. Is determined by calculating the circuit service band currently being processed.

ATM line card group 26b handles the CBR traffic in the same way as circuit services.

VBR and UBR traffic have higher priority than connectionless services such as Ethernet frames, but lower priority than circuit services such as T-1 services.

Ethernet frame is a connectionless service and has a lower priority than T-1, ATM service group.

However, fairness between the same groups is provided in a round-robin between line ports belonging to the Ethernet line card group 26a.

The bus line width and operating frequency of the signal line shown in the physical connection structure of the present invention can be extended regardless of the logical operation model.

By providing more than the aggregated bandwidth of the entire line port device, the switching throughput of the system can be expanded.

As described above, according to the present invention, the following effects can be obtained.

First, it minimizes the overhead of the connection line between the switching core device and the line port device, the complexity of the bus method, maximizes the line port scalability, heterogeneous line port connectivity, and OAM with data channels and in-band. You can process the message.

Second, the connection type with the line port device provides flexible connection between line port devices inside the PCB as well as connection between the outside of the line card PCB.

Third, the switching interface according to the present invention can adjust the service period from the switching core to the line port to provide QoS between the multiple line ports and to handle the flow of variable length packets.

Fourth, by setting a packet segment level virtual circuit between the switching core device and the line port device, different line port devices can operate with the switching core device regardless of the type of packet.

For example, the Ethernet frame flow may be processed between the switching core device and the line port device-1, and the ATM cell flow may be processed between the switching core device and the line port device-2.

In addition, by adjusting the QoS support function between line ports, service priority may be provided to Line Port-2 where ATM cell flow is processed rather than Ethernet frame flow.

Claims (14)

Fragment the variable length packet to perform transmission / exchange / copy function for each packet segment and collect / analyze the information of the line port by checking the status of the line port device to establish a physical connection structure and logical operation model that supports QoS between multiple ports. Switching interface between the switching core device and the line port device. The switching interface between the switching core device and the line port device according to claim 1, wherein the Tx direction signal line from the switching core device to the line port device and the Rx direction signal line from the line port device to the switching core device are independent of each other. The Tx direction signal line is TxData [7: 0], TxAddr [4: 0], TxSync, TxEnb directed from the switch engine 20 on the switching core device side to the Internet link 24 on the line port device side. Switching between the switching core device and the line port device, comprising TxFeb, TxClk and TxStatus [4: 0] from the Internet link 24 on the line port device side to the switch engine 20 on the switching core device side. interface. The switching interface between the switching core device and the line port device according to claim 2 or 3, wherein a variable length packet is supported through the Tx direction signal line for single transmission, group transmission, and broadcasting. The switching interface between the switching core device and the line port device according to claim 2 or 3, further comprising in-band routing headers, routing commands, and packet segments through the Tx direction signal line. The signal line of claim 2, wherein the Rx direction signal line is RxData [7: 0], RxStatus [4: 0], RxSync, and RxFeb directed from the Ethernet link 24 on the line port device side to the switch engine 20 on the switching core device side. And switching between the switching core device and the line port device, comprising RxAddr [4: 0], RxEnb, and RxClk from the switch engine 20 on the switching core device side to the Ethernet link 24 on the line port device side. interface. The switching interface between the switching core device and the line port device according to claim 2 or 6, further comprising a routing command and a packet segment in-band through the Rx direction signal line. The switching interface of claim 1, wherein only the last packet valid byte is notified when the packet segment is transmitted. The switching interface between the switching core device and the line port device according to claim 1, wherein the OAM processing is performed by using a routing command format when transmitting the packet segment. 8. The switching interface between the switching core device and the line port device according to claim 7, wherein OAM processing is performed by using a routing command format when transmitting the packet segment. 4. The method of claim 3, wherein after the TxAddr [4: 0] provided by the switching core device is the same as the line port device address two or more times, the Hi-Z state is canceled, and the line port device enters the operation mode from the stop mode. A switching interface between a switching core device and a line port device. The method according to claim 6, wherein the Hi-Z state is canceled after RxAddr [4: 0] provided by the switching core device is the same as the line port device address two or more times, so that the line port device enters the operation mode from the stop mode. A switching interface between a switching core device and a line port device. The switching interface between the switching core device and the line port device according to claim 1, wherein the virtual circuit is supported on a line port device basis regardless of the packet type. The switching interface of claim 1 or 9, wherein the heterogeneous packet is processed as one switching interface using a virtual circuit of the line port device unit.