KR20020042077A - A method for snooping and fetching for cache coherency - Google Patents

Abstract

PURPOSE: A snooping and fetching method for the cache coherency is provided to reduce the data reading time of other CPU when cache hit happens by making the CPU writing the data transmit the signal informing that the valid data is loaded to a data bus to the CPU reading the data. CONSTITUTION: As a bus master is changed to a CPU2(2) from a CPU1(1) by a bus arbiter(6), in case that the CPU2 reads a memory(5) storing the garbage data, the CPU1 stops the reading operation by sending a signal(ARTRY*) to the CPU2. The CPU1 obtains a bus priority by receiving a signal(BG*) from the bus arbiter after sending a bus priority request signal to the bus arbiter and writes again a real value of a block unit stored in the cache1(3) of the CPU1 to the memory. When the CPU1 writes the data corresponding the data occurring the cache hit by the read request of the CPU2, the CPU1 informs the CPU2 that the data wanted by the CPU2 is loaded to the data bus by sending the valid data to the CPU2.

Description

Snooping and fetching methods for cache coherency {A METHOD FOR SNOOPING AND FETCHING FOR CACHE COHERENCY}

The present invention relates to cache coherency in write back cache mode in a multi-processor board. In particular, the present invention reads data of another CPU when a cache hit occurs. A snooping and fetching method for cache coherency that can save time.

In general, embedded systems use a multiprocessor approach that uses two or more CPUs on a board to improve performance.

That is, as shown in FIG. 1, the multiprocessor method includes two CPU1 (1) and CPU2 (2), each having a cache 1 (3) and a cache 2 (4), and one memory (5). ) Will be shared.

In this case, the bus arbiter 6, which is connected to the CPU 1 (1), the CPU 2 (2) and the memory 5 by an address, a data bus, or the like, adjusts the use right of the bus (bus grant).

At this time, the CPU (CPU1 or CPU2) that has received the bus right becomes the bus master.

By the way, each CPU (CPU1 or CPU2) reads data from the memory 5 and puts it in the cache to increase the data processing speed.

The CPU (CPU1 or CPU2) reads and writes data in caches 1, 2 (3) (4), so the value in caches 1,2 (3) (4) and the value in memory (5) may be different. have.

Therefore, if another CPU (CPU1 or CPU2) becomes the bus master and the data to be read from the memory (5) has already been changed by the CPU (CPU1 or CPU2) previously, an operation error may occur. It is cache coherency.

The method of using the cache 1, 2 (3) (4) has a large write-through writeback, the write-through is a memory (5) at the same time when writing data to the cache 1, 2 (3) (4) Is to write data to

When writing back data to cache 1, 2 (3) (4), the writeback does not write data to memory (5), thereby shortening the writing time and storing the data of cache 1, 2 (3) (4) if necessary. This is how to write in (5).

Therefore, cache coherency is important in the writeback mode, and various methods are used for cache coherency, a representative of which is snooping.

1 and 2, first, suppose that CPU1 1 is a bus master and that there is data of 0x00 at address 0x10 of the memory 5.

The CPU 1 reads it, stores it in the Cache 1 3, and then changes it back to 0xFF.

Then, the true value 0xFF is in the cache 1 (3) only and there is only a garbage value of 0x00 in the address 0x10 of the memory 5.

Subsequently, when the bus master is changed from CPU 1 (1) to CPU 2 (2) by the bus arbiter 6, the CPU 2 (2) performs various processing while reading or writing data in the memory (5), the CPU 2 (2). It also uses cache 2 (4) for data throughput.

At this time, if the address that the CPU2 2 attempts to read from the memory 5 is 0x00, the cache coherency is broken because only the garbage value is included in the address.

At this time, CPU1 (1) sends a signal (ARTRY *) to CPU2 (2) to stop the data read operation, sends a signal (BR *) to bus arbiter 6 to acquire a bus license, and then CPU1 (1). Writes the true value in cache 1 (3) into memory (5).

At this time, monitoring the address so that other CPUs (CPU1 or CPU2) do not read the wrong value is called snooping, and the address indicated by the address has a true value only in the cache (3 or 4) of the CPU (CPU1 or CPU2) and memory. (5) is called a snooping hit when it has a garbage value, and writing a true value back into the memory 5 is called a snooping push.

However, the conventional technique has a disadvantage in that the CPU (CPU1 or CPU2) to take data has to wait until the CPU (CPU1 or CPU2) having true data writes the data to the memory 5.

That is, when CPU1 (1) is snooping push, the data to be taken by CPU2 (2) is already loaded on the CPU bus, but the CPU2 (2) cannot use this value and the bus arbiter 6 Since the data must be requested to the memory (5) after the bus license is allocated from the system, the performance of the system decreases due to such a delay time in the case of using multiple CPUs to improve the processing speed.

The present invention utilizes the fact that the data to be read by the CPU is already loaded on the data bus when another CPU is snooping and pushes the CPU to write the data to the CPU to read the data. It provides a snooping and fetching method for cache coherency that transmits signals to reduce the data read time of other CPUs when a cache hit occurs. .

1 is a related block circuit diagram of a cache coherency applied in the related art.

2 is a flow chart illustrating a snooping and fetching method for conventional cache coherency.

3 is a related block circuit diagram of cache coherency applied to the present invention.

4 is a flow chart illustrating a snooping and fetching method for the present invention cache coherency.

A snooping and fetching method for the cache coherency of the present invention will be described with reference to FIGS. 3 and 4.

For reference, the drawings referred to below will be described with the same reference numerals for the same parts as in the prior art for convenience of description, and redundant descriptions are omitted.

As shown in Figs. 3 and 4, CPU1 (1) sends a signal to bus arbiter (6) and CPU2 (2) to stop the data read operation and the true value contained in cache 1 (3) of CPU1 (1). In a multiprocessor that writes data back into memory 5,

A valid signal is sent to CPU2 (2) when CPU2 (2) writing the data writes data corresponding to the address where the cache hit occurred to CPU 2 (2) when CPU 2 (2) makes a read request in a block where snooping pushes. send valid data to indicate that the desired data is on the data bus,

The CPU2 (2) is characterized in that the data carried on the data bus can be used to read through the valid signal output from the CPU (1).

The snooping and fetching methods for the present invention cache coherency are described in detail with reference to the accompanying drawings.

First, when the bus master changes from CPU 1 (1) to CPU 2 (2) by the bus arbiter 6, and the CPU 2 (2) wants to read the memory 5 containing the garbage value,

The CPU1 (1) snoops and sends a signal (ARTRY *) to the CPU2 (2) to stop the data read operation.

In addition, after requesting the bus license by sending a signal BR * to the bus arbiter 6, the bus 1 receives the signal BG * from the bus arbiter 6 and acquires a bus license. The true value of the block unit contained in 3) is written back into the memory (5).

At this time, when the CPU1 (1) that writes the data writes the data corresponding to the address at which the cache hit occurred to the memory 5 by the CPU2 (2) read request among the blocks that snooping push, the CPU1 (1) Transmits valid data to CPU2 (2) to inform CPU2 (2) that desired data has been loaded on the data bus.

Then, the CPU 2 (2) can read and use the data on the data bus through the valid signal output from the CPU (1).

In this case, when the CPU 2 (2) needs to read other data in addition to the data, after the snooping push of the CPU 1 (1) is finished, the bus usage rights may be obtained from the bus arbiter 6 to perform a read operation. .

In addition, since the snooping push of the CPU1 (1) is performed in units of blocks, if there is data desired by the CPU2 (2) in the block, the CPU2 (2) checks the address and data, and then the CPU1 (1). You can also get the data you need during your snooping push.

As described above, the present invention utilizes the fact that the data to be read by the CPU is loaded onto the data bus when another CPU is snooping. By sending a signal (Valid data) indicating that the is loaded, it provides an effect of reducing the data read time of the other CPU when the cache hit (cache hit) occurs.

The present invention is not limited to the above-described specific preferred embodiments, and various modifications can be made by any person having ordinary skill in the art without departing from the gist of the present invention claimed in the claims. Of course, such changes will fall within the scope of the claims.

Claims (1)

In a multiprocessor, CPU1 sends a signal to the bus arbiter and CPU2 to stop the data read operation and to rewrite the true value from cache1 of CPU1 into memory. When CPU1 writes the data, CPU2 sends a valid signal when CPU2 reads and writes the data corresponding to the address where the cache hit occurred to memory, and the desired data is loaded on the data bus. Informing step, The CPU2 reading data loaded on the data bus when a valid signal output from the CPU1 is recognized; Snooping and fetching methods for cache coherency characterized in that the control.