KR20020042030A - Semiconductor memory device having multi-bank capable of reducing refresh time and refresh method thereof - Google Patents

Abstract

PURPOSE: A semiconductor memory device having multiple banks is provided to reduce a refresh action time by sequentially refreshing many banks by means once auto refresh command, and reduces a refresh time of all banks. CONSTITUTION: A semiconductor memory device includes a delay part(100) for receiving a refresh signal and many delay circuits(D1-Dn). The semiconductor memory device includes many banks(BANK1-BANKn) respectively having a memory cell. One of many banks is refreshed by the refresh signal, and the others are refreshed by an output signal of a corresponding delay circuit among many delay circuits(D1-Dn). The delay circuits(D1-Dn) are connected in series, and have the same delay time or a different delay time. The delay circuits receive the refresh signal in common.

Description

Semiconductor memory device having multi-bank capable of reducing refresh execution time and refresh method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a refresh method and a circuit of a dynamic random access memory (DRAM).

Volatile memory devices such as DRAMs must refresh data stored in memory cells at regular intervals. In general, a memory cell of a DRAM is composed of one access transistor and one capacitor, and data is represented by an amount of charge accumulated at both ends of the capacitor. However, the amount of charge stored in the capacitor is leaked due to various reasons, and there is a risk of losing the stored data. Therefore, it is necessary to restore the data before the amount of charge leaks to the extent that data cannot be recovered, and the operation for this is called refresh. At every refresh cycle, all memory cells included in the semiconductor memory device must be refreshed at least once. Refresh can be divided into ROR (RAS ONLY REFRESH), Self Refresh (SELF REFRESH), and Auto Refresh (AUTO REFRESH) according to the DRAM operation. In the automatic refresh, a refresh address counter (REFRESH ADDRESS COUNTER) built in the DRAM chip generates a row address instead of receiving a refresh address from the outside, so that the refresh is performed and the address applied from the outside is ignored. Unlike the automatic refresh, the self refresh has an operation mode in which even the row address strobe signal (/ RAS; Row Address Strobe) used as the refresh synchronization signal is generated inside the DRAM. That is, when a certain timing condition is satisfied, a refresh request signal is automatically generated by an internally generated refresh timer without a control signal from the outside, so that the control signals of the RAS system are automatically generated inside the device and internally. The refresh operation is performed by the generated address.

When a memory cell array block of a DRAM is configured into a plurality of independently controlled memory cell array blocks, i.e., a plurality of banks, the other bank is precharged (or precharged) when one bank becomes active (or precharged). Concurrent operation in which active) operation is performed is possible.

However, in order to perform an automatic refresh cycle in a semiconductor memory device having multiple banks, all banks must be precharged first, and access to other banks is impossible while the automatic refresh cycle is performed. This means that time during the automatic refresh is wasted, so it is necessary to reduce the automatic refresh time.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor memory device capable of reducing an automatic refresh execution time.

Another object of the present invention is to provide a refresh method that can reduce the automatic refresh execution time.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram illustrating a semiconductor memory device according to a first embodiment of the present invention.

2A is a diagram illustrating a refresh time of a conventional semiconductor memory device having multiple banks.

2B is a view showing a refresh time of a semiconductor memory device having multiple banks according to the present invention.

3 is a block diagram illustrating a semiconductor memory device according to a second embodiment of the present invention.

According to a first embodiment of the present invention for achieving the above technical problem, a plurality of banks including a delay unit for receiving a refresh signal and having a plurality of delay circuits and a plurality of banks each including memory cells, One of them is refreshed by the refresh signal, and the other banks are refreshed by an output signal of a corresponding delay circuit among the delay circuits.

The plurality of delay circuits may be connected in series. In addition, the plurality of delay circuits may have the same delay time or different delay times.

According to a second exemplary embodiment of the present invention for achieving the above technical problem, the plurality of delay circuits commonly receive the refresh signal and have different delay times.

According to another aspect of the present invention, a method of refreshing a semiconductor memory device having a plurality of banks may include: applying a refresh signal to one of the plurality of banks, and refreshing the refresh signal. There is provided a refresh method comprising the steps of generating a plurality of delay refresh signals by delaying by a predetermined time of and applying the respective delay refresh signals to the respective banks for refresh.

Each predetermined time may be the same time or different times.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a block diagram of a semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 1, a semiconductor memory device according to a first embodiment of the present invention may include a delay unit 100 receiving a refresh signal SREF and including a plurality of delay circuits D1 to Dn and memory cells respectively. A plurality of banks BANK1 to BANK n including (not shown), one of the banks BANK1 to BANK n is refreshed by the refresh signal SREF, and the remaining banks are delayed circuits. It is refreshed by the output signal of the corresponding delay circuit among (D1-Dn).

The plurality of delay circuits D1 to Dn are connected in series.

Hereinafter, an operation of the semiconductor memory device according to the first embodiment of the present invention will be described in detail with reference to FIG. 1.

In a typical multi-bank DRAM, the refresh is performed by the sum of the rows of each bank. The total refresh time is (number of banks) * tRC. Where tRC is the time at which one bank is refreshed.

Referring to the refresh operation according to the present invention, the refresh signal SREF is first applied to the first bank BANK 1 and the delay circuit D1 of the delay unit 100. The refresh of the first bank BANK 1 is started by the refresh signal SREF. Here, the delay circuits D1 to Dn-1 in the delay unit 100 are provided in one fewer number than the plurality of banks BANK1 to BANK n. In addition, the delay circuits D1 to Dn-1 may include elements that may delay a signal such as a buffer or flip-flop. The delay time of the refresh signal SREF by the delay circuits D1 to Dn-1 may be the same or different for each of the delay circuits D1 to Dn-1. That is, the delay time may be freely determined by the elements constituting the delay circuits D1 to Dn-1. However, the delay time should be less than tRC, which is the time when one bank is refreshed.

After a predetermined delay time, the delay circuit D1 generates a delay refresh signal SDREF and applies it to the second bank BANK2 and the delay circuit D2 (not shown). The refresh of the second bank BANK 2 is started by the delay refresh signal SDREF. Each delay refresh signal SDREF generated in the delay circuits D1 to Dn-1 may be applied to any one of the banks BANK2 to BANK n except for the first bank BANK1. For convenience of explanation, the delay refresh signal SDREF generated by the delay circuit D1 is applied to the second bank BANK2, and in the same manner, the delay refresh signal SDREF generated by the delay circuit Dn-1 is applied. It is assumed that the n-th bank BANK n is applied.

As described above, when the delay refresh signal SDREF generated in the delay circuit Dn-1 is applied to the nth bank BANK n, the refresh of the nth bank BANK n is started and the nth bank after tRC time. The refresh of (BANK n) is completed.

That is, when the refresh signal SREF is input once, the refresh of the first bank BANK1 starts, and the refresh of the second bank BANK2 starts again after a predetermined delay time. In this manner, refreshes are sequentially performed up to the nth bank BANK n.

2A is a diagram illustrating a refresh time of a conventional semiconductor memory device having multiple banks.

2B is a view showing a refresh time of a semiconductor memory device having multiple banks according to the present invention.

Referring to FIG. 2A, one of the plurality of banks BANK1 to BANK n is refreshed, and a time of tRC is consumed and a time of tRC * n is required to refresh all of the n banks BANK1 to BANK n. Indicates exhausted. Typically tRC = 70ns. If n = 4, tRC * n = 70ns * 4 = 280ns is consumed to be refreshed from the first bank BANK1 to the fourth bank BANK4.

Referring to FIG. 2B, after the first bank BANK1 starts to be refreshed by the refresh signal SREF, the second bank BANK2 is refreshed by the delay refresh signal SDREF after a predetermined delay time tD. To start. In this manner, the last n-th bank BANK n starts to be refreshed, and after the tRC time, all the refreshes of the n-th bank BANK n finally end. Assuming a delay time tD of 20 ns, the time taken for all n banks BANK1 to BANK n to be refreshed is tD * (n-1) + tRC, and n = 4 20 ns * 3 + 70 ns = 130 ns. Based on four banks, refresh time is saved by 54%.

Although FIG. 2B illustrates only the case where the delay times tD of the delay circuits D1 to Dn-1 are all the same, the delay times tD of the delay circuits D1 to Dn-1 may be different. Should be.

3 is a diagram illustrating a semiconductor memory device according to a second embodiment of the present invention.

As shown in FIG. 3, the semiconductor memory device according to the second embodiment of the present invention is different from the first embodiment only in the internal structure of the delay unit 300. Therefore, the structure and function of the delay unit 300 is mainly described for convenience of description. The delay unit 300 is provided with a plurality of delay circuits DA1 to DAn-1 for receiving the refresh signal SREF in common. The plurality of delay circuits DA1 to DAn-1 may be provided in one less number than the plurality of banks BANK1 to BANK n. In addition, the plurality of delay circuits DA1 to DAn-1 may be provided with elements that may delay a signal such as a buffer or flip-flop. The delay time of the refresh signal SREF by the plurality of delay circuits DA1 to DAn-1 is different from each other, and the delay circuits DA1 to DAn-1 are different from each other. It can be freely determined by the constituent elements. However, the delay time tAD should be less than tRC, which is a time when one bank is refreshed.

When the refresh signal SREF is simultaneously applied to the first bank BANK1 and the plurality of delay circuits DA1 to DAn-1, the refresh of the first bank BANK1 is started and the plurality of delay circuits DA1 to DAn− are started. 1) generates a delay refresh signal SDREF after different predetermined delay times. Each of the delay refresh signals SDREF generated in the plurality of delay circuits DA1 to DAn-1 may be applied to any one of the banks BANK2 to BANK n except for the first bank BANK1. However, for the sake of convenience, the delay refresh signal SDREF generated by the delay circuit DA1 is applied to the second bank BANK2 and, in the same manner, the delay refresh signal SDREF generated by the delay circuit DAn-1. ) Is applied to the n-th bank (BANK n). The refresh of the second bank BANK2 is started by the delay refresh signal SDREF generated by the delay circuit DA1 having the shortest delay time, and in this manner, the delay refresh signal generated by the delay circuit DAn-1. When the SDREF is applied to the nth bank BANK n, the refresh of the nth bank BANK n is started, and the refresh of the nth bank BANK n is completed after tRC time.

That is, when the refresh signal SREF is input once, the refresh of the first bank BANK1 starts, and the refresh of the second bank BANK2 starts again after a predetermined delay time. In this manner, refreshes are sequentially performed up to the nth bank BANK n.

The refresh time of the semiconductor memory device according to the second embodiment of the present invention may be described in the same manner as shown in FIG. 2B. However, it should be taken into account that the delay times for generating delay refresh signals SDREF are different from each other.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, in a semiconductor memory device having multiple banks according to the present invention, a plurality of banks are sequentially refreshed by a single automatic refresh command, and the time to access the memory is reduced by reducing the refresh time of all banks. There is an advantage to increase.

Claims (9)

A delay unit for receiving the refresh signal and having a plurality of delay circuits; And A plurality of banks each including memory cells, one of the plurality of banks being refreshed by the refresh signal, and the remaining banks being refreshed by an output signal of a corresponding delay circuit of the delay circuits. A semiconductor memory device. The method of claim 1, wherein the plurality of delay circuits Semiconductor memory device characterized in that connected in series The method of claim 2, wherein the plurality of delay circuits A semiconductor memory device having the same delay time The method of claim 2, wherein the plurality of delay circuits Semiconductor memory device having a different delay time The method of claim 1, wherein the plurality of delay circuits And receiving the refresh signal in common. The method of claim 5, wherein the plurality of delay circuits A semiconductor memory device having a different delay time. A refreshing method of a semiconductor memory device having a plurality of banks, the method comprising: (a) applying a refresh signal to one of the plurality of banks to refresh; (b) delaying the refresh signal by a predetermined time to generate a plurality of delay refresh signals; And and (c) applying the respective delay refresh signals to the corresponding respective banks to refresh them. The method of claim 7, wherein Wherein each predetermined time is the same time. The method of claim 7, wherein Wherein each predetermined time is a different time.