KR20020038874A - Digital television for applying to internet connection - Google Patents

Abstract

PURPOSE: A digital broadcasting receiver supporting an Internet connection is provided to adopt a CPU compatible with x86 level in an STB(Set Top Box), to which ground wave and cable broadcasting are received, thereby receiving broadcasting programs and connecting Internet based on a PC. CONSTITUTION: A signal transceiving block(110) receives TP(Trick Play) signals from an antenna or a cable and converts the received TP signals into 1394-format signals for transmission to an external, or receives 1394-format TP signals from an external. An HD(High Definition) decoder(120) decodes ground wave or cable broadcasting and mixes graphics of a media processor block(150) for display. An AC-3 decoder(130) decodes data encoded in an AC-3 specification in the HD decoder(120) to output digital audio data. The media processor block(150) performs PC functions such as an Internet connection, play of HDD or DVD-ROM titles, processes graphics, and controls digital broadcasting play. A CPLD(Complex Programmable Logic Device,140) is for interface with the HD decoder(120) by providing PCI(Peripheral Component Interconnect) interface from the media processor block(150). A video ADC(Analog-to-Digital Converter,160) converts analog video signals output in the media processor block(150) into digital signals for the input to the HD decoder(120). An IDE(Integrated Device Electronics) interface(170) connects a DVD-ROM or an HDD. An RS-232 driver(180) is for serial interface with external equipment or for system check. An AC-97 codec(190) mixed digital audio and analog audio upon driving application related to audio, or adjust volume.

Description

DIGITAL TELEVISION FOR APPLYING TO INTERNET CONNECTION}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital broadcast receivers and, more particularly, to digital broadcast receivers that support Internet access.

With the development of digital broadcasting technology, digital broadcasting set-top boxes with Internet access have been developed.

The prior art can be classified into two types as follows.

First, there is a way to use a dedicated browser.

This technology uses the RISC series of CPUs and achieves Internet access by implementing a suitable Internet browser for each system in a set-top box powered by real-time operating system.

Second, there is a method of accessing other internet sites through a dedicated internet site mainly using an existing SD TV.

This technology supports only a few Internet sites on a dedicated Internet site as a prerequisite to display on existing TVs.

However, the prior art has a disadvantage in that it is difficult to implement all kinds of various applications supported by the Internet, and also it is not easy to update an already supported application program.

Accordingly, an object of the present invention is to provide a digital broadcast receiver supporting an Internet connection invented to implement a PC-based Internet function in a set-top box capable of watching digital TV broadcasts in order to improve the disadvantages of the related art.

That is, the present invention adopts CPI compatible with the x86 series in a digital set-top box capable of receiving terrestrial and cable broadcasting, thereby enabling broadcast reception as well as PC-based Internet access.

It is another object of the present invention to make DVD ROM and HDD accessible.

1 is a block diagram of a digital broadcast receiver according to an embodiment of the present invention.

2 is a block diagram showing the configuration of a media processor block in FIG.

Explanation of symbols on the main parts of the drawings

110: signal transmission and reception block 120: HD decoder

130: AC-3 decoder 140: CPLD

150: Media Processor 160: Video ADC

170: IDE interface unit 180: RS-232 driver

190: AC-97 codec

In order to achieve the above object, the present invention provides a media processor block for controlling PC functions such as Internet access, HDD or DVD ROM title playback, graphics processing and digital broadcast playback, and controlled by the media processor block, And an HD block for decoding wired broadcasting and mixing graphics on the media processor block to display on a display device screen, and an interface block for interfacing between the HD decoder and the media processor.

The media processor block outputs a signal for controlling the HD decoder and supports a PC function such as Internet access, HDD or DVD ROM title playback, a graphics processor for graphics processing, and MPEG data processing to output video data and audio data. A digital video processor, a video logic section for mixing and processing the video data of the digital video processor and the graphics data of the graphics processor and outputting the same to an HD decoder, recording / reproducing media such as HDD, DVD ROM, and audio. And an interface circuit for interfacing with a device or the like with the graphics processor or the digital video processor.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

As shown in the block diagram of FIG. 1, the set-top box supporting the Internet function according to the present invention includes a signal transmission / reception block 110, an HD decoder 120, an AC-3 decoder 130, a CPLD 140, and a media. The processor block 150, the video ADC 160, the IDE interface unit 170, the RS-232 driver 180, and the AC-97 codec 190 are configured to be provided.

The signal transmission / reception block 110 receives a TP signal from an antenna or a cable, and converts the received TP signal into a 1394 format and transmits it to the outside, or receives a 1394 format TP signal from the outside. The processor 111, the wired signal processor 112, the multiplexer 113 and 115, the CVBS processor 114, and the 1394 signal processor 116 are configured.

The VSB processor 111 is a part for processing digital TV terrestrial waves, and serves to generate valid TP data from a high frequency signal received by an antenna and input the same to the HD decoder 120.

The cable broadcasting processing unit 112 serves to generate valid TP data from a signal transmitted through a cable and input the same to the HD decoder 120.

Here, the VSB processing unit 111 and the cable broadcasting processing unit 112 may also receive a general analog signal, and thus may be configured to pass the analog IF signal to the CVBS processing unit 114.

The CVBS processor 114 separates video and audio from analog IF signals input from the VSB processor 111 or the cable broadcasting processor 112, converts the video signal into a digital signal, and separates the audio signal into stereo according to a standard. It serves to pass the next step.

The 1394 signal processor 116 includes a 1394 link layer and a 1394 physical layer (PHY). The 1394 signal processor 116 converts the TP data into an IEEE-1394 format and transmits the data to the outside or is input from an external 1394 type TP. The data is received and transmitted to the HD decoder 120.

The multiplexer (MUX1) 113 selects one of the TP data in the terrestrial wave and the TP data in the cable signal and inputs it to the TP input terminal of the HD decoder 120.

The multiplexer (MUX2) 115 selects one of the digital video data of the CVBS unit 114 and the graphics / video signal of the video ADC 150 and inputs it to an external video input terminal of the HD decoder 120.

The HD decoder 120 is a part that supports functions such as TP De-MUX, MPEG decoding (MP @ HL), 2D Graphics, Host I / F, External Video (XVGA) input function, and CVBS video output.

The AC-3 decoder 130 is a part for decoding the data encoded in the AC-3 standard by the HD decoder 120 and outputting the digital audio data.

The media processor block 150 is based on the x86 CPU, SDRAM memory I / F, PCI I / F, graphics controller, MPEG decoding (MP @ ML), IDE I / F, serial I / F, Ir I / It is a part for providing F, AC-97 I / F, etc., and a PCI slot for expansion is connected, and this slot can be easily connected to a high speed internet network.

The CPLD 140 is a part for I / F with the HD decoder 120 by providing PCI I / F in the media processor block 150, and the media processor block 150 is an HD decoder through the CPLD 140. Adjust 120.

The video ADC 160 is a part for converting an analog XVGA level video signal output from the media processor block 150 into a digital form for input to the HD decoder 120. The HD decoder 120 is an XVGA level. You can receive 24-bit RGB digital data and display it in full screen or on a PIP screen.

The IDE interface unit 170 is a part for connecting a DVD ROM or an HDD, and the RS-232 driver 180 is a part for serial interface or system check with an external device.

The AC-97 codec 190 is connected to the media processor block 150 through the AC-97 I / F. The AC-97 codec 190 is a part for mixing digital audio and analog audio or adjusting volume when driving various audio-related applications.

As shown in the block diagram of FIG. 2, the media processor block 150 includes a graphics processor 210 for supporting PC functions such as Internet access, DVD ROM title playback and graphics processing, and processing MPEG data to process video data. And a digital video processor 220 for outputting audio data, and for processing the video data in the digital video processor 220 and the graphics data in the graphics processor 210 and outputting the mixed data to the video ADC 160. And a video logic unit 230, a recording / reproducing medium such as an HDD and a DVD ROM, an audio device, and the like, and an interface circuit unit 240 for interfacing with the graphics processor 210 or the digital video processor 220.

Referring to the operation and effect of the embodiment of the present invention configured as described above are as follows.

Upon initial power-up of the system, the media processor block 150 drives the boot program to initialize the entire system, which controls the HD decoder 120 through the CPLD 140 to display the initial screen on the display device.

Thereafter, TV broadcasting, Internet access, or recording medium access may be performed. This will be described below.

1) The operation of watching a general digital TV broadcast is as follows.

When a high frequency signal (RF) is received by the signal transmission / reception block 110 through an antenna or a cable, the VSB processing unit 111 or the cable broadcasting processing unit 112 separates channel information desired by a user from each tuner, thereby VSB decoding or QAM decoding. After executing the TP data will be output.

At this time, the multiplexer (MUX1) 113 selects only one TP data of the VSB processing unit 111 or the cable broadcasting processing unit 112 and delivers the TP data to the TP input terminal of the HD decoder 120.

Accordingly, the HD decoder 120 separates the input TP data into compressed video, compressed audio, and information data, and then outputs audio data compressed to the AC-3 standard to the AC-3 decoder 130, and compresses the video data. Image processing is performed by decoding, and information data is separated and stored in a buffer to be read by the media processor block 150.

Thereafter, the media processor block 150 reads the video signal decoded by the HD decoder 120 and analyzes the data in the TP to determine that there is data to be displayed. It is processed to be suitable for processing and transmitted to the HD decoder 120 through the multiplexer 115 of the video logic 230, the video ADC 160, and the signal transmission / reception block 110.

Accordingly, the HD decoder 120 outputs a screen mixed with video and graphics.

The digital audio decoded by the AC-3 decoder 130 is input to the AC-97 codec 190, and then mixed with another audio signal by the AC-97 codec 190, or after gain is adjusted. Signal output.

2) The operation when accessing the Internet is as follows.

First, the graphics processor 210 equipped with an x86 series processor, an OS such as Windows or Windows CE, or Linux attempts to access the Internet through a modem or a LAN mounted in a PCI slot according to a user's attempt to access the Internet.

In this case, when the Internet data is input to the media processor block 150, the graphics processor 210 performs graphics processing, and the video logic unit 230 outputs an analog video signal through image processing, and the audio signal interface. It outputs to the AC-97 codec 190 through the AC-97 interface of the circuit unit 240.

Accordingly, the video ADC 160 digitally converts the analog video signal from the media processor block 150 and inputs it to the external video input port of the HD decoder 120 through the signal transmission / reception block 110.

Accordingly, the HD decoder 120 processes the video signal from the media processor block 150 to display the web page screen, so that the user can search for the desired information.

3) The operation when accessing the recording medium will be described as follows.

When the recording medium access mode is set by the user, the media processor block 150 causes the graphics processor 210 to control the playback operation of the recording medium, and the video data reproduced on the recording medium is transferred to the digital video processor 220 through the IED interface. ) Is decoded by the internal MPEG decoder and processed by the graphics processor 210 to be suitable for the graphics processing of the HD decoder 120 to the HD decoder 120 through the video logic unit 230 and the video ADC 160. Will be sent.

Accordingly, the HD decoder 120 performs video processing and graphics processing and then displays it on the screen.

Meanwhile, the present invention may separately perform operations for viewing digital TV broadcasts, accessing the Internet, or accessing a recording medium as described above, but may execute other functions while executing one function.

In this case, the main screen may display a digital broadcast, the sub screen may display an Internet web page, or conversely, the main screen may display an internet web page, and a sub screen may display a digital broadcast.

In addition, both the main screen and the sub-screen may display a digital TV broadcast or an Internet web page.

As described in detail above, the present invention enables the digital TV broadcasting receiver to use the x86 series of CPI (CPU) as well as digital TV broadcasting as well as PC-based Internet access can provide a variety of information to the user. .

Claims (2)

A digital broadcast receiver for receiving digital broadcasts, comprising: a media processor block for controlling an Internet connection, PC functions such as playing HDD or DVD ROM titles, graphics processing, and the like, controlled by the media processor block, and controlled by terrestrial broadcast or wired; An HD decoder for decoding a broadcast and mixing graphics from the media processor block to display on a display device screen, and an interface block for interfacing between the HD decoder and the media processor. Digital broadcast receiver. The media processor block according to claim 1, wherein the media processor block outputs a signal for controlling the HD decoder and supports a PC function such as Internet connection, HDD or DVD ROM title playback, a graphics processor for graphics processing, and MPEG data processing to process video data. And a digital video processor for outputting audio data, a video logic section for mixing and processing the video data in the digital video processor and the graphics data in the graphics processor and outputting the same to an HD decoder, recording of HDD, DVD ROM, etc. And / or interface circuitry for interfacing with a graphics processor or a digital video processor, such as a playback medium, an audio device, or the like.