KR20020036085A - Circuit of Semiconductor Memory - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided, which improves a productivity of the memory semiconductor, and prevents a current concentration phenomenon by improving a circuit configuration. CONSTITUTION: The first fuse part outputs a control signal to control a part or the whole chip to operate per bank according to a test result of the chip. The second fuse part outputs a mat selection signal to select a mat being turned on per bank according to the test result of the chip. The first counter circuit part generates an internal address except the most significant bit and an internal address per bank of the most significant bit according to the control signal and the mat selection signal. The first address selection circuit part outputs one of the internal address except the most significant bit and an external address applied from the external. The second address selection circuit part outputs one of the internal address per bank of the most significant bit and the external address. And a decoder circuit part selects a part of a number of word lines according to output signals of the first and the second address selection circuit part.

Description

Circuit of Semiconductor Memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit, and more particularly, to a semiconductor memory circuit for improving production efficiency of a memory semiconductor device by using a repairable portion of a defective chip in which a defect is generated in a highly integrated semiconductor device.

Hereinafter, a conventional semiconductor memory circuit will be described with reference to the accompanying drawings.

1 is a block diagram showing the structure of a conventional semiconductor memory circuit, FIG. 2 is a circuit diagram of the refresh counter unit of FIG. 1, FIG. 3 is a detailed circuit diagram of a refresh counter unit constituting the refresh counter unit, and FIG. 4 is FIG. Is a detailed circuit diagram of the address selection section.

First, as shown in FIG. 1, the conventional semiconductor memory circuit includes a refresh counter unit 11 which generates an internal address RAaB according to the refresh command signal REF, and an external address A <a> from an external device. ) And an address selector for selecting the internal address (RAaB) or external address (A <a>) and outputting them to the X-address (BXa) according to the refresh command signal REF. (13), an address latch & pre decoder 14 for latching and pre-decoding the X-address BXa to output a pre-decoded row address PRA, and the pre The row decoder 15 outputs a word line selection signal WL for activating a specific row according to the decoded row address PRA.

In addition, the refresh counter unit 11 of the 256M memory element is composed of first to thirteenth refresh counter units 21 to 33 that output internal addresses RA0B to RA12B, as shown in FIG. The explanation is as follows.

The first refresh counter unit 21 that outputs the internal address RA0B of the least significant bit with the DC driving voltage Vcc applied from the outside, and outputs the carry signal C0 to the neighboring refresh counter unit, and the neighboring lower bit. Second to twelfth refresh counter units 32 outputting the internal addresses RA1B to RA11B as a carry signal input from the refresh counter unit of FIG. 2 and outputting the carry signals C1 to C11 to the refresh counter units of adjacent higher bits. And a thirteenth refresh counter unit 33 that outputs an internal address RA12B as a carry signal C11 output from the twelfth refresh counter unit 32.

In addition, a detailed circuit configuration of the first to thirteenth refresh counter units 21 to 33 may include a first inverter 41 for inverting the refresh command signal REF and the first inverter as shown in FIG. 3. A first NAND gate 42 which inverts the output signal of the inverter 41 by the carry signal Cn-1 from the neighboring lower bit, and inverts the output signal of the first NAND gate 42. A second inverter 43 and a third inverter 44 which is enabled by the output signal of the first NAND gate 42 and the output signal of the second inverter 43 and inverts the signal of the node A, and The fourth inverter 45 which inverts the output signal of the third inverter 44, the output signal of the first NAND gate 42, and the output signal of the second inverter 43 and is enabled by the fourth inverter 45. The output signal of the inverter 45 is inverted and fed back to the input of the fourth inverter 45. A sixth inverter enabled by the fifth inverter 46, the output signal of the first NAND gate 42, and the output signal of the second inverter 43, and inverting the output signal of the fourth inverter 45. To the inverter 47, the seventh inverter 48 for inverting the output signal of the sixth inverter 47, the output signal of the first NAND gate 42 and the output signal of the second inverter 43. Enabled by the inverted output signal of the seventh inverter 48 to feed back to the input of the seventh inverter 48 and the eighth inverter 49 and the inverted output signal of the seventh inverter 48 From the ninth inverter 50 for outputting the A-node signal, the tenth inverter 51 for inverting the output signal of the fourth inverter 45 to output to the internal address (RAaB), and the neighboring lower bits Of the second signal to inversely multiply the carry signal (Cn-1) and the output signal of the seventh inverter 48 by And gate 52, and the second consists of a NAND gate 52, an eleventh inverter 53 to output a carry signal (Cn) to a higher-order bit adjacent to the inverted output signal of the.

Here, the third inverter 44, the fifth inverter 46, the sixth inverter 47, and the eighth inverter 49 are clock inverters, and the third inverter 44 and the eighth inverter are clocked inverters. The inverter 49 is enabled when the output signal of the first NAND gate 42 is low (L) and the output signal of the second inverter 43 is high (H) to invert the input signal. The output signal of the first NAND gate 42 is high (H) and the output signal of the second inverter 43 is low (L) of the fifth inverter 46 and the sixth inverter 47. Is enabled when the input signal is inverted and output.

As shown in FIG. 4, a detailed circuit configuration of the address selector 13 includes an output of the twelfth inverter 61 for inverting the refresh command signal REF and the output of the twelfth inverter 61. The thirteenth inverter 62 which is inverted and the fourteenth inverter 63 which is enabled according to the output signal of the thirteenth inverter 62 and the output signal of the twelfth inverter 61 and inverts the internal address RAaB. ), A fifteenth inverter 64 enabled according to the output signal of the twelfth inverter 61 and the output signal of the thirteenth inverter 62, and inverting the external address A <a>; And a sixteenth inverter 65 which inverts the output signal of the fourteenth inverter 63 or the output signal of the fifteenth inverter 64 and outputs the inverted signal to the X-address BXa.

Herein, the fourteenth inverter 63 and the fifteenth inverter 64 are clocked inverters, and the fourteenth inverter 63 has the output of the thirteenth inverter 62 being low (L). When the output of the twelfth inverter 61 is high (H) is enabled, the fifteenth inverter 64 is the output of the thirteenth inverter 62 is high (H) and the output of the twelfth inverter (61) Since it is enabled when the output is low (L), only one of the fourteenth inverter 63 and the fifteenth inverter 64 operates to output a signal to the sixteenth inverter (65).

The refresh operation of the conventional semiconductor memory circuit configured as described above is as follows.

5 is a diagram illustrating a counting procedure of a refresh counter of a conventional semiconductor memory circuit, and FIG. 6 is a timing diagram illustrating a refresh operation of the conventional semiconductor memory circuit.

First, as shown in FIG. 6, the refresh counter 11 generates an internal address RAaB at the falling edge of the refresh command signal REF, and the address selector 13 generates the refresh command. The internal address RAaB is selected at the rising edge of the signal REF and output to the X-address BXa.

The address latch & predecoder unit 14 latches the X-address BXa and uses the output thereof as an input to generate a predecoded row address PRA, and the row decoder 15 A word line selection signal WL for activating a specific row is output from the predecoded row address PRA and an externally applied black row address.

In addition, a sense amplifier of a memory array corresponding to the word line selection signal WL operates to sense information of a memory cell connected to the word line selection signal WL. In this manner, the memory cell information is refreshed.

In this case, since one row is selected by one word line selection signal WL, when the word line selection signal WL is i, 2 ⁱ refresh cycles are required to refresh the entire row.

A normal refresh specification is represented by the following formula.

For example, a 256M bit DRAM having a 4-bank structure has i = 12, and four rows are simultaneously operated by one refresh command signal REF, thereby enabling four rows to be activated.

In this case, the refresh specification is 8192 refresh cycles, and in the case of a normal 256M SDRAM, the cycle is 64msec.

Since the refresh counter 11 has a structure that is sequentially connected according to the bit order, as shown in FIG. 2, the counting order is shown in mat 0 (M0) as shown in FIG. 5. Starting with mat 15 (M15).

However, the conventional semiconductor memory circuit as described above has the following problems.

First, as the degree of integration of memory increases, the probability of obtaining a chip that can be used due to a defect such as a process decreases, so that the yield decreases.

Second, as the memory density increases, a lot of current is consumed during the refresh operation. Since the counting sequence of the refresh counters occurs sequentially, the current is consumed intensively in one place, resulting in unstable circuit operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. By using a repairable portion of a defective chip in a highly integrated memory semiconductor device, the production efficiency of the memory semiconductor can be improved, and the circuit structure can be improved to prevent current concentration. It is an object of the present invention to provide a semiconductor memory circuit.

1 is a block diagram showing the configuration of a conventional semiconductor memory circuit.

FIG. 2 is a circuit diagram of the refresh counter of FIG. 1.

3 is a detailed circuit diagram of a refresh counter unit constituting the refresh counter unit;

4 is a detailed circuit diagram of an address selector of FIG. 1;

5 is a view illustrating a counting procedure of the refresh counter of FIG. 1.

6 is a timing diagram for explaining an operation of a conventional semiconductor memory circuit.

7 is a block diagram showing a configuration of a semiconductor memory circuit according to an embodiment of the present invention.

8 is a circuit diagram of a refresh counter unit of the present invention.

9 is a detailed circuit diagram of a refresh counter unit constituting the refresh counter unit of the present invention.

10 is a detailed circuit diagram of an address selector of the present invention.

11 is a detailed circuit diagram of a half chip enable unit and a mat selector of the present invention.

12 is a view illustrating a counting procedure of the refresh counter unit of the present invention.

Fig. 13 is a diagram showing a mat configuration for configuring a memory of the present invention into half chips.

14 is a timing diagram when the semiconductor memory circuit of the present invention operates in a full chip.

Fig. 15 is a timing diagram when the semiconductor memory circuit of the present invention operates with a half chip.

Explanation of symbols for the main parts of drawings

71: address input unit

72: half chip enable part

73a to 72d: first to fourth mat selection portions

74: refresh counter

75a to 75e: first to fifth address selectors

76a to 76d: first to fourth address latch & pre decoder sections

77a to 77d: first to fourth row decoders

The semiconductor memory circuit of the present invention for achieving the above object comprises a first fuse unit for outputting a control signal for controlling the chip to operate part or all of each bank according to the test result of the chip, and the test result of the chip A second fuse unit for outputting a mat selection signal for selecting a mat that is turned on for each bank in accordance with the present invention, and an internal address excluding a most significant bit and an internal address for each bank of most significant bits according to the control signal and the mat selection signal. A first counter circuit unit, a first address selection circuit unit for selecting and outputting any one of an internal address except the most significant bit and an external address applied externally, and one of an internal address for each bank of the most significant bit and the external address A second address selection circuit section for selecting and outputting the second address selection circuit section; And a decoder circuit section for selecting a part of the plurality of word lines according to the output signal of the first address selection circuit section and the output signal of the second address selection circuit section.

Hereinafter, a semiconductor memory circuit of the present invention will be described with reference to the accompanying drawings.

7 is a block diagram showing a configuration of a semiconductor memory circuit according to an embodiment of the present invention, FIG. 8 is a circuit diagram of a refresh counter unit of the present invention, and FIG. 9 is a detailed circuit diagram of a refresh counter unit constituting the refresh counter unit of the present invention. 10 is a detailed circuit diagram of an address selector of the present invention, and FIG. 11 is a detailed circuit diagram of a half chip enable unit and a mat selector of the present invention.

As shown in FIG. 7, the semiconductor memory circuit according to the embodiment of the present invention includes an address input unit 71 that receives an external address input from an external device, and a memory in half chip according to a reset start signal RST. A half chip enable unit 72 for outputting a half chip enable signal HE, and a first to first enable to determine a selection mat for each bank when the half chip is configured and is enabled by the reset start signal RST. First to fourth mat selection units 73a to 73d for outputting the fourth mat selection signals HX_B0 to HX_B3 and internal addresses RAaB <a = 0 to i-1> according to the refresh command signal REF. Or selecting and outputting an external address A <a = 0 to i-1> and when the half chip enable signal HE is enabled, the first to fourth mat selection signals HX_B0 to Within the bank of most significant bit (a = i) according to HX_B3) A refresh counter 74 for outputting sub-addresses RAiB_B0 to RAiB_B3, and internal addresses from the refresh counter 74 according to the refresh command signal REF (RAaB <a = 0 to i-1>) Alternatively, the first address selector 75a which selects an external address A <a = 0 to i-1> from the address input unit 71 and outputs it to the X-address BXa <a = 0 to i-1>. ) And the bank 0 internal address (RAiB_B0) or the most significant bit of the most significant bit from the refresh counter unit 74 according to the refresh command signal REF, which is enabled by the half chip according to the half chip enable signal HE. A second address selector 75b which selects an external address A <a = i> of a bit and outputs it to the X-address BXi_0, and enables the half chip according to the half chip enable signal HE. And the maximum value from the refresh counter unit 74 according to the refresh command signal REF. A third address selector 75c for selecting the bank 1 internal address RAiB_B1 or the external address A <a = i> of the most significant bit and outputting the result to the X-address BXi_1; It is enabled by a half chip according to the enable signal HE, and according to the refresh command signal REF, the bank 2 internal address RAiB_B2 of the most significant bit or the external address A << of the most significant bit from the refresh counter unit 74. and a fourth address selector 75d for selecting and outputting a = i>) to the X-address BXi_2 and being enabled with a half chip according to the half chip enable signal HE, and refreshing the refresh command signal REF. A fifth to select the bank 3 internal address (RAiB_B3) of the most significant bit or the external address (A <a = i>) of the most significant bit from the refresh counter unit 74 and output to the X-address BXi_3. An address selector 75e, and the first The output signals BXa <a = 0 to i-1> of the first address selector 75a and the output signals BXi_0 to BXi_3 of the second to fifth address selectors 75b to 75e are latched and precoded. Of the first to fourth address latch & predecoder sections 76a to 76d for outputting the predecoded row addresses PREi_0 to PREi_3, and the first to fourth address latch & predecoder sections 76a to 76d. The first to fourth row decoders 77a to 77d output the word line selection signals WL_0 to WL_3 for each bank according to the output signal.

In addition, the refresh counter unit 74 of the 256M semiconductor memory circuit according to the embodiment of the present invention is composed of the first to sixteenth refresh counter units 81 to 96, as shown in FIG. Same as

A first refresh counter unit 81 for outputting an internal address RA11B of the 11th bit with a DC driving voltage Vcc and outputting a carry signal C0 to a neighboring refresh counter unit; and the first refresh counter unit ( The second refresh counter unit 82 which outputs the internal address RA0B of the least significant bit (a = 0) as the carry signal C0 from 81 and outputs the carry signal C1 to the neighboring upper refresh counter unit; And third to eleventh refresh counters which output internal addresses RA1B to RA9B as carry signals from the neighboring lower bit refresh counter units and output carry signals C2 to C10 to the neighboring higher bit refresh counter units. Outputs an internal address RA10B as a carry signal C10 from the units 83 to 91 and the eleventh refresh counter unit 91, and the thirteenth to sixteenth refresh counter units 93; A twelfth refresh counter unit 92 which outputs a carry signal C11 to the edge 96 and a half chip according to the half chip enable signal HE, and a refresh command signal REF and the carry signal C11. The first chip select signal HX_0 operates as a half chip according to the thirteenth refresh counter unit 93 which outputs the bank 0 internal address RAiB_B0 of the most significant bit and the half chip enable signal HE. A fourteenth refresh counter unit 94 which outputs the bank 1 internal address RAiB_B1 of the most significant bit according to the refresh command signal REF, the carry signal C11, and the second mat select signal HX_1, and a half chip It operates in half chip according to the enable signal HE and outputs the bank 2 internal address RAiB_B2 of the most significant bit by the refresh command signal REF, the carry signal C11, and the third mat select signal HX_2. 15th leaf It operates in half chip according to the sheath counter unit 95, the half chip enable signal HE, and the most significant bit according to the refresh command signal REF, the carry signal C11, and the fourth mat select signal HX_3. And a sixteenth refresh counter unit 96 that outputs the bank 3 internal address RAiB_B3.

The refresh counter unit constituting the refresh counter unit 74 of the present invention includes a first inverter 101 for inverting the refresh command signal REF and the first inverter 101 as shown in FIG. 9. A first NAND gate 102 for inverting and inverting the output signal of the neighboring bit by the carry signal Cn-1 of a neighboring bit, and a second inverter 103 for inverting the output signal of the first NAND gate 102. And a third inverter 104 which is enabled by the output signal of the first NAND gate 102 and the output signal of the second inverter 103 and inverts the signal of the B node, and a half chip enable signal ( A fourth inverter 105 for inverting HE, a second NAND gate 106 for inverting the output signal of the fourth inverter 105 and the output signal of the third inverter 104, and the second 1 based on the output signal of the NAND gate 102 and the output signal of the second inverter 103 A fifth inverter 107 that is enabled and inverts and outputs the second NAND gate 106 output signal to its input; an output signal of the first NAND gate 102 and an output signal of the second inverter 103. A sixth inverter 108 enabled by the second NAND gate 106 and inverting the output signal of the second NAND gate 106, a seventh inverter 109 inverting the output signal of the sixth inverter 108, and the sixth inverter 108. The eighth inverter 110 is enabled by the output signal of the first NAND gate 102 and the output signal of the second inverter 103 and inverts the output signal of the seventh inverter 109 and feeds back to the input. A ninth inverter 111 for inverting the output signal of the seventh inverter 109 and outputting a signal to the B node, a carry signal Cn-1 from the neighboring lower bits, and the seventh inverter ( Third NAND gate 112 that inverses the output signal of 109 A ninth inverter 113 which inverts the output signal of the third NAND gate 112 and outputs the carry signal Cn to a neighboring upper refresh counter unit, and a tenth inverter that inverts the mat selection signal HX. And a fourth NAND gate 115 for performing an AND operation on the output signal of the second NAND gate 106 and the output signal of the tenth inverter 114, and inverting the output signal to the internal address RAaB. .

Here, the third inverter 104, the fifth inverter 107, the sixth inverter 108 and the eighth inverter 110 are clock inverters (Clked inverter), the third inverter 104 and the eighth inverter 110 is enabled when the output signal of the first NAND gate 102 is low (L) and the output signal of the second inverter 103 is high (H), and the fifth inverter ( 107 and the sixth inverter 108 are enabled when the output signal of the first NAND gate 102 is high (H) and the output signal of the second inverter 103 is low (L).

That is, when the third inverter 104 and the eighth inverter 110 are enabled, the fifth inverter 107 and the sixth inverter 108 are disabled and, conversely, the third inverter 104. When the eighth inverter 110 is disabled, the fifth inverter 107 and the sixth inverter 108 are enabled.

In addition, as shown in FIG. 10, the address selectors 75a to 75e of the present invention include a NOR gate 121 for inverting and inverting the refresh command signal REF and the half chip enable signal HE. It is enabled by an eleventh inverter 122 that inverts the output signal of the noah gate 121, an output signal of the eleventh inverter 122, and an output signal of the noah gate 121 and receives an external address A <a. And a thirteenth inverter 123 that inverts the &lt; RTI ID = 0.0 &gt; and &lt; / RTI &gt; an output signal of the NOR gate 121 and an output signal of the eleventh inverter 122 and inverts the internal address RAaB. 124 and the fourteenth inverter 125 for inverting the output signal of the twelfth inverter 123 or the thirteenth inverter 124 and outputting the inverted signal to the X-address BXa.

The twelfth inverter 123 and the thirteenth inverter 124 are clocked inverters. When the twelfth inverter 123 is enabled, the thirteenth inverter 124 is disabled and vice versa. When the inverter 123 is enabled, the eleventh inverter 122 is disabled, so that the fourteenth inverter 125 has only one of an output signal of the eleventh inverter 122 and an output signal of the twelfth inverter 123. Will be input.

The half chip enable unit 72 and the first to fourth mat selectors 73a to 72d have the same configuration, and the detailed circuit diagram thereof is illustrated in FIG. A fuse 131 connected to Vcc, a first NMOS 132 on which one electrode is connected to the other electrode of the fuse 131, and a reset start signal RST is applied to the gate electrode, and the first A second NMOS 133 and a third NMOS 134 connected in series between the other electrode of the NMOS 132 and a ground terminal, and to which a DC driving voltage Vcc is applied to the gate electrode, and the fuse 131. 15th to 17th inverters 135 to 137 for inverting the output signal of the other electrode of the terminal and outputting the half chip enable signal HE, and connected between the other electrode of the fuse 131 and the ground terminal. And a fourth NMOS 138 having a gate electrode connected to the output terminal of the fifteenth inverter 135. The.

The operation of the semiconductor memory circuit of the present invention configured as described above is as follows.

12 is a diagram illustrating a counting procedure of the refresh counter unit of the present invention, FIG. 13 is a diagram illustrating a mat configuration for configuring the memory of the present invention into a half chip, and FIG. 14 is a full chip of the semiconductor memory circuit of the present invention. Fig. 15 is a timing diagram when the semiconductor memory circuit of the present invention operates in a half chip.

First, the refresh counter 74 generates an internal address RAaB at the falling edge of the refresh command signal REF, and the first to fifth address selectors 75a to 75e generate the refresh command signal. On the rising edge of (REF), the internal address (RAaB <a = 0 to i>) generated by the refresh counter 71 is selected to select the X-address BXa <a = 0 to i>. Generate.

Here, when the half chip is configured, BXi, which is the most significant bit signal of the X-address BXa, selects a mat MAT that is enabled using a fuse for each bank according to the state of each bank of the chip. (In the case of 256M, i = 12) corresponds to the number of chip banks (eg, BXi_0, BXi_1, BXi_2, and BXi_3). The X-address (BXi) of the most significant bit is controlled for each bank.

The address latch & predecoder 76a to 76d latches the X-address BXa <a = 0 to i> and inputs the output thereof to generate a predecoded row address, and the row decoders 77a to 76d. 77d) outputs a wordline select signal WL for activating a specific wordline by the predecoded row address.

In addition, a sense amplifier of a memory array in which a word line is selected by the word line selection signal WL operates to sense the memory cell information connected to the selected word line. Refreshed.

In the embodiment of the present invention, the row address is 0 to i (i = 12 for 256M bits), and in the case of SDRAM, one word line is selected by one row address (word line selection signal) per bank. Refreshing the entire row of the bank requires 2 ⁱ refresh cycles (8k with i = 2 for 256M bits).

In the present invention, in the case of 256M, the fuse of the half chip enable unit 72 is set as shown in Table 1 according to the P-check test result of the chip.

Fuse Status Half Chip Enable Signal (HE) Chip status NO CUT (Default) L 256M SDRAM CUT H 128M SDRAM

That is, in the case of 256M, a chip having no defect or a chip capable of being repaired due to defects, that is, a chip capable of recovering the memory of 256M, that is, the memory of 256M can be used, as shown in Table 1 above. The fuse of 72) has a default state that is not cut and the half chip enable signal HE is low (L) so that the refresh counter unit corresponding to the most significant bit of the refresh counter unit 71 has an internal address like 256M DRAM. Perform a counting operation to perform an 8K refresh cycle.

In the refresh operation of the semiconductor memory circuit of the present invention, as shown in FIG. 8, the refresh counter 74 has the highest count of the counts of RAiB_B0 to RAiB_B3 (i = 12 in the case of 256M) of the most significant bit of each bank. Bit, and the internal address of the second most significant bit of the address, RA <i-1> B (i = 12 in the case of 256M) becomes the least significant bit of the counting, and the refresh counting order for each bank is shown in FIG. 12. Similarly, WL1 of MAT4 (M4) is activated after WL0 of MAT0 (M0).

That is, the bank is divided into two equal portions (M0-7, M8-15) and counting is performed in units of 1/4 mats (M0-3, M4-7).

When the chip p-check test cannot obtain 256M DRAM and can be configured as 128M DRAM by a combination of banks, as shown in Table 1, the fuse of the half chip enable unit 72 is cut. The half chip enable signal HE is made high (H), and the first to fourth mat selectors 73a to 73d are set according to the first to fourth mat selectors 73a to 73d. Set as shown in 2.

Fuse status Matte Select Signal (HX) × 12 One NO CUT (Default) L × 12B 2 CUT H × 12T

That is, the mat for each bank is selected according to the state of the mat selection signals HX_B0 to HX_B3 which are output signals of the first to fourth mat selection units 73a to 73d.

For example, when the mat selection signals HX_B0 to HX_B3 are low L, that is, when the fuses of the first to fourth mat selection units 73a to 73d are not cut, all of the fuses shown in FIG. 15 are cut. As described above, the outputs RAiB_B0 to RAiB_B3 of the refresh counter units 93 to 96 of the most significant bit of the refresh counter unit 74 are fixed to low L to form a mat as shown in case 1 of FIG. Configure.

As shown in Table 1, when the fuse of the half chip enable unit 72 is cut, the half chip enable signal becomes high (H). As shown in Table 2, the first to fourth mats All of the mat selection signals HX_B0 to HX_B3 which are output signals of the selectors 73a to 73d are fixed to high H to form a mat as shown in case 2 of FIG. 13 to form a 128M DRAM.

Table 3 shows a case in which a 256M DRAM composed of 4 banks can be configured as a half chip 128M DRAM in this manner.

case Fuse Status by Bank on Mat Selection X-Address Status of Matt Select Signal & Highest Bit for Each Bank Matte selected for each bank (× 12) Bank 3 Bank 2 Bank 1 Bank 0 Bank 3 Bank 2 Bank 1 Bank 0 Bank 3 Bank 2 Bank 1 Bank 0 One NO CUT NO CUT NO CUT NO CUT L L L L × 12B × 12B × 12B × 12B 2 NO CUT NO CUT NO CUT CUT L L L H × 12B × 12B × 12B × 12T 3 NO CUT NO CUT CUT NO CUT L L H L × 12B × 12B × 12T × 12B 4 NO CUT NO CUT CUT CUT L L H H × 12B × 12B × 12T × 12T 5 NO CUT CUT NO CUT NO CUT L H L L × 12B × 12T × 12B × 12B 6 NO CUT CUT NO CUT CUT L H L H × 12B × 12T × 12B × 12T 7 NO CUT CUT CUT NO CUT L H H L × 12B × 12T × 12T × 12B 8 NO CUT CUT CUT CUT L H H H × 12B × 12T × 12T × 12T 9 CUT NO CUT NO CUT NO CUT H L L L × 12T × 12B × 12B × 12B 10 CUT NO CUT NO CUT CUT H L L H × 12T × 12B × 12B × 12T 11 CUT NO CUT CUT NO CUT H L H L × 12T × 12B × 12T × 12B 12 CUT NO CUT CUT CUT H L H H × 12T × 12B × 12T × 12T 13 CUT CUT NO CUT NO CUT H H L L × 12T × 12T × 12B × 12B 14 CUT CUT NO CUT CUT H H L H × 12T × 12T × 12B × 12T 15 CUT CUT CUT NO CUT H H H L × 12T × 12T × 12T × 12B 16 CUT CUT CUT CUT H H H H × 12T × 12T × 12T × 12T

That is, as shown in Table 3, in the case of 256M DRAM, there are 16 methods for configuring a half chip 128M DRAM depending on the state of each bank.

In the 128M SDRAM configuration, as shown in FIG. 12, when the mat select signals HX_0 to HX_B3 are low L, 4K word lines are activated on the mats 0 to 7 in units of 4 mats, and mat selection is performed. When the signals HX_0 to HX_3 are high (H), the 4K word lines are activated in units of 4 to 4 mats of the mats 8 to 15, so that word lines of non-neighboring mats are always operated.

The semiconductor memory circuit of the present invention as described above has the following effects.

First, when a defect occurs in a memory device and a memory cannot be implemented as a full chip, there are various methods of configuring a half chip according to test results, thereby improving the yield of highly integrated memory.

Second, during the refresh operation, the word lines are sequentially activated on mats that are not immediately adjacent to each other, thereby improving current vulnerabilities intensively consumed in specific portions of the chip during refresh.

Claims (3)

A first fuse unit for outputting a control signal for controlling the chip to operate in part or in whole according to the test result of the chip; A second fuse unit configured to output a mat selection signal for selecting a mat turned on for each bank according to a test result of the chip; A first counter circuit section for generating an internal address excluding the most significant bit and an internal address for each bank of the most significant bit according to the control signal and the mat selection signal; A first address selection circuit unit for selecting and outputting any one of an internal address except the most significant bit and an external address applied from the outside; A second address selection circuit unit which selects and outputs any one of an internal address for each bank of the most significant bit and the external address; And a decoder circuit section for selecting a part of a plurality of word lines in accordance with an output signal of the first address selection circuit section and an output signal of the second address selection circuit section. The method of claim 1, wherein the decoder circuit is configured to output a signal for selecting a portion of the plurality of word lines by latching and decoding the output signal of the first address selection circuit portion and the output signal of the second address selection circuit portion. A semiconductor memory circuit. 2. The semiconductor memory circuit according to claim 1, wherein the counter circuit portion is configured such that the second most significant bit of the address is the least significant bit when counting internal addresses and the most significant bit of the address is the most significant bit when counting internal addresses.