KR20020023598A - Delay circuit - Google Patents

Abstract

PURPOSE: A delay circuit is provided to prevent a malfunction of the whole circuit, by making a duty of an input signal correspond to that of an output signal even if a degree of delay at a rising edge is different from that at a falling edge in a low voltage operation. CONSTITUTION: The first exclusive OR gate(XOR11) exclusively ORs an input signal and a delayed input signal through the first delay part(11). The first inverter(INV11) inverts the input signal. The second exclusive OR gate(XOR12) exclusively ORs an output signal of the fist inverter and a delayed output signal of the first inverter through the second delay part(12). A NAND gate(NAND11) NANDs the output signals of the first and second exclusive OR gates. The second inverter(INV12) inverts the output signal of the NAND gate. A latch unit(14) is synchronized by the output signal of the NAND gate and the second inverter, and transits the input signal passing through a buffer(13) to output the transit signal as an output signal. The latch unit maintains the output signal until a next synchronization occurs.

Description

Delay circuit {DELAY CIRCUIT}

The present invention relates to a delay circuit, and more particularly, to a delay circuit suitable for obtaining a delayed output signal whose duty matches the input signal.

In general, a delay circuit manufactured through a CMOS transistor is configured to have a desired delay value by serially combining a plurality of delay units that uniformly delay an input signal, or buffer the input signal through an input buffer and then through a delay circuit. It is designed to be delayed and configured to obtain a final delay signal through the output buffer again. Such a general delay circuit has difficulty in accurately controlling a desired delay value, and in particular, there is a problem in that a circuit operation defect occurs due to a change in input / output duty at a low voltage.

Referring to the drawings with a conventional delay circuit in detail as follows.

Fig. 1 is a conventional delay circuit diagram, which shows an inverter INV1 for inverting an input signal IN as shown therein; An NMOS transistor NM1 which receives the output of the inverter INV1 to a drain through a resistor R1, a source is grounded, and is electrically controlled by applying an input signal IN to a gate; When the NMOS transistor NM1 is turned on and connected between the drain of the NMOS transistor NM1 and ground, a capacitor C1 for RC delaying the drain output of the NMOS transistor NM1 together with the resistor R1; ; The NAND gate receives the drain output of the NMOS transistor NM1 delayed through the capacitor C1 on one side, receives the initialization signal RST input from the user on the other side, and outputs the NAND combination as an output signal OUT. It consists of (NAND1).

Hereinafter, the operation of the conventional delay circuit configured as described above will be described in detail with reference to the input / output waveform diagram of FIG.

First, when the input signal IN transitions from the low potential to the high potential, the inverter INV1 inverts it and outputs the low potential. At this time, since the NMOS transistor NM1 applying the input signal IN to the gate is turned on, the capacitor C1 is discharged.

Accordingly, the NAND gate NAND1 outputs an output signal OUT that transitions to a high potential by delaying the input signal IN by the time required for discharging the capacitor C1 regardless of the initialization signal RST input to the other side. do.

When the input signal IN transitions from a high potential to a low potential, the inverter INV1 inverts it and outputs a high potential. At this time, since the NMOS transistor NM1 applying the input signal IN to the gate is turned off, the capacitor C1 is charged.

Accordingly, when the NAND1 NAND1 is supplied with the initialization signal RST input to the other side with high potential, the RC delay due to the charging and resistance R1 of the capacitor C1 and the capacitor C1 is applied to the input signal IN. The output signal OUT which transitions to the low potential with a delay by time is output.

At this time, since the charging of the capacitor C1 takes longer than the discharge at low voltage, the duty of the input signal IN and the output signal OUT depends on the delay degree of the rising edge and the falling edge of the output signal OUT. Does not match.

However, in the conventional delay circuit as described above, as shown in the waveform diagram of FIG. 2, the delay degree of the rising edge and the falling edge of the output signal is changed at low voltage so that the duty of the input signal and the output signal does not match. As the driving capability of the transistors constituting the circuit at low voltage is lowered, the duty difference is further increased, which causes a problem in that a defect occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to provide a delay circuit capable of obtaining a delayed output signal in which the input signal and the duty match.

1 is a conventional delay circuit diagram.

2 is an input / output waveform diagram of FIG. 1;

Figure 3 is a block diagram showing an embodiment of the present invention.

4 is a waveform diagram of each node of FIG. 3 at a normal voltage.

FIG. 5 is a waveform diagram of each node of FIG. 3 at low voltage. FIG.

*** Explanation of symbols for main parts of drawing ***

IN: input signal OUT: output signal

11, 12: first and second delayed portions XOR 11, XOR 12: first and second exclusive oragate

NAND11: NAND gate INV11, INV12: 1st, 2nd inverter

13: Buffer 14: latch

A delay circuit for achieving the object of the present invention as described above comprises a first exclusive ora gate for combining the exclusive signal of the input signal and the delayed input signal through the first delay unit; A first inverter for inverting the input signal; A second exclusive oragate which combines an output signal of the first inverter and an output signal of the first inverter delayed through a second delay unit; A NAND gate NAND combining the output signals of the first and second exclusive ogates; A second inverter for inverting an output signal of the NAND gate; And a latch unit for shifting the input signal passed through the buffer in synchronization with the output signal of the NAND gate and the second inverter to output the output signal, and holding the output signal until the next synchronization occurs. .

When described in detail with reference to the accompanying drawings a delay circuit according to the present invention as follows.

FIG. 3 is a block diagram showing an embodiment of the present invention. As shown therein, a first exclusive ogate for exclusively combining an input signal IN and an input signal IN delayed by the first delay unit 11 is shown. (XOR11); A first inverter INV11 for inverting the input signal IN; A second exclusive ogate (XOR11) for exclusively combining the output signal of the first inverter (INV11) and the output signal of the first inverter (INV11) delayed by the second delay unit (12); A NAND gate NAND11 for NAND combining the output signals of the first and second exclusive ogates XOR11 and XOR12; A second inverter INV12 for inverting an output signal of the NAND gate NAND11; The input signal IN passing through the buffer 13 is shifted and output as the output signal OUT in synchronization with the output signals of the NAND gate NAND11 and the second inverter INV12, and is output until the next synchronization occurs. A latch 14 is provided to hold the output signal OUT, and reference numerals A to H are nodes inserted to explain the waveform diagrams of FIGS. 4 and 5.

An operation process at a general voltage (3.3V) according to an embodiment of the present invention configured as described above will be described in detail with reference to the waveform diagram of FIG.

First, node A shows a signal inverting the input signal IN through the inverter INV11, node B shows a signal delaying the input signal IN, and node C shows a node ( The signal which delayed the signal of A) appears.

In addition, the first exclusive ogate (XOR11) outputs the same signal as the node (D) by combining the exclusive signal of the node (B) and the input signal (IN) passing through the first delay unit (11), The second exclusive ogate XOR12 combines the signal of the node C passing through the second delay unit 12 with the signal of the node A, which is the output of the first inverter INV12, to node E. Outputs the same signal as).

The signals of the nodes D and E are NAND-combined through the NAND gate NAND11 to output the same signal as the node F, and the second inverter INV12 inverts the same and outputs the same signal as the node G. do.

Meanwhile, the buffer 13 buffers the input signal IN and outputs the same signal as the node H. In this case, the buffer 13 includes an eleventh inverter for simply inverting the input signal IN; An eleventh to thirteenth ring buffer sequentially buffering an output signal of the eleventh inverter; The twelfth inverter may be configured to invert the output of the thirteenth ring buffer.

The latch unit 14 shifts the signal of the node H in synchronization with the rising edge of the node F and the falling edge of the node G, and changes its state to the next rising edge of the node F and the node G. FIG. ) Is maintained as the next falling edge and finally output as the output signal (OUT). At this time, the latch unit 14 simply receives the node signals F and G as clock signals and inverted clock signals, respectively, and synchronizes the signals. After latching, the output value is held until the next synchronization is made.

The waveform diagram of FIG. 4 illustrates waveforms of the nodes A to H and the output signal OUT at a normal voltage at which the voltage level of the input signal IN is about 3.3 V. As shown in FIG. It can be seen that the delays of the rising edge and the falling edge of the node B and C waveforms passing through the second delay parts 11 and 12 coincide with each other.

On the other hand, the waveform diagram of FIG. 5 shows the waveforms of the nodes A to H and the output signal OUT at the low voltage of about 1.1 V, and the voltage level of the input signal IN. Since the charge of the internal capacitors of the second delay parts 11 and 12 takes longer than that of the discharge, it can be seen that the delays of the rising edge and the falling edge of the node B and C waveforms are different.

As described above, even if the delay degree of the rising edge and the falling edge is different, as a result, the latch unit 14 is synchronized with the rising edge of the node F and the falling edge of the node G so as to signal the node H. And the state is maintained until the next rising edge of the node F and the next falling edge of the node G, so that the duty of the output signal OUT with respect to the input signal IN coincides.

In the delay circuit according to the present invention as described above, even if the delay degree of the rising edge and the falling edge is changed by the influence of the capacitor of the delay portion during the low voltage operation, by correcting this to match the duty of the input signal and the output signal, There is an effect that can prevent the malfunction of the entire circuit.

Claims (1)

A first exclusive oragate for combining or exclusive combining the input signal and the input signal delayed through the first delay unit; A first inverter for inverting the input signal; A second exclusive oragate which combines an output signal of the first inverter and an output signal of the first inverter delayed through a second delay unit; A NAND gate NAND combining the output signals of the first and second exclusive ogates; A second inverter for inverting an output signal of the NAND gate; And a latch unit for shifting the input signal passed through the buffer in synchronization with the output signal of the NAND gate and the second inverter to output the output signal, and holding the output signal until the next synchronization occurs. Delay circuit.