KR20020017278A - Self test circuit of semiconductor memory - Google Patents

Abstract

PURPOSE: A self test circuit is provided to automatically perform a self test operation at system power-up and output a test result whenever a user requires the test result. CONSTITUTION: A monitor circuit(104) tests a memory state after a memory is reset at power-up. A flag register(106) stores a monitor result of the monitor circuit as a flag bit of logic 1 or logic 0. The first switch(108a) is switched by a power-up signal or a user input control signal. A user register(110a-110n) receives and stores a flag bit stored in the flag register via the first switch. The second switch(112b) is switched by a user output control signal. The third switch(114c) is switched by the user output control signal, and is connected to the second switch and an input/output terminal of the memory. The third switch selects one of the flag bit in the user register and an output signal of the memory to transfer the selected one to a pad.

Description

Self test circuit of semiconductor memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memories, and more particularly to self test circuits for semiconductor memories.

The test of semiconductor memory is largely divided into product test and probe test according to the purpose. Product testing aims to detect defects in manufacturing processes, such as wafer processing and assembly processes, to eliminate defective products and to select only good products.

Probe testing verifies that the function or performance of a semiconductor memory matches design specifications. Therefore, product testing is conducted in large quantities in the shipping process, and high productivity is required. The purpose of the probe test is to conduct the research carefully during the research and development to improve the product completion and shorten the development period.

If these tests reveal manufacturing defects or inconsistencies in design and function, analysis or failure analysis is the key to investigating the exact cause of the failure.

In such a test method of a semiconductor memory, a predetermined test vector is stored in each memory cell and retrieved again, and it is determined whether a defect occurs in the memory by comparing whether the input data and the extracted data are the same.

When testing the memory in this way, in order to save the time required for the test, the test data is input to only a part of the input / output pads provided without inputting data to all the input / output pads provided in the memory to be tested. Do it.

However, in order to test such a conventional semiconductor memory, a process of inputting a predetermined test vector into a memory and a process of drawing and comparing the same are required. In addition, because the test results are not stored, there is a problem that the results must be checked immediately.

The self test circuit of the semiconductor memory according to the present invention has an object of automatically performing a self test when the system is powered up and then outputting a test result whenever a user requests it.

The present invention for this purpose includes a monitor circuit, a flag register, first to third switches, and a user register.

The monitor circuitry checks the state of the memory after the memory is initialized at power-on. The flag register stores the test result of the monitor circuit as flag bits of logic 1 or logic 0. The first switch is switched by a power up signal or a user input control signal. The user register receives and stores a flag bit stored in the flag register through the first switch. The second switch is switched by the user output control signal. The third switch is switched by the user output control signal, is connected to the second switch and the input / output terminals of the memory, and selects one of the flag bits of the user register and the output signal of the memory transmitted through the second switch to the pad. do.

1 is a diagram illustrating a self test circuit of a semiconductor memory according to the present invention.

2 is a timing diagram showing an operating characteristic of a self test circuit of a semiconductor memory according to the present invention.

Explanation of symbols on the main parts of the drawings

102: memory

104: monitor circuit

106: flag register

108: first switch

110: user register

112: second switch

114: third switch

116: Pad

118: or gate

A preferred embodiment of a self test circuit of a semiconductor memory according to the present invention will be described with reference to FIGS. 1 and 2 as follows. 1 is a diagram illustrating a self test circuit of a semiconductor memory according to the present invention.

As shown in FIG. 1, the monitor circuit 104 monitors the state of major components of the memory 102. For example, by monitoring the initial value of the output signal of the latch constituting the memory 102, the level of the power voltage output from the power generator, and the like, the bit value of the corresponding flag is logical 0. In case of abnormality, the bit value of the corresponding flag is recorded as logic 1. The monitoring operation of the memory 102 by the monitor circuit 104 is automatically performed at the time of the power up signal PWR_UP.

The power-up signal PWR_UP is a signal generated when a predetermined time elapses when the power supply voltage VDD reaches a sufficient level (full VDD) when the system is powered on. That is, the power up signal PWR_UP is a signal indicating that the power supply voltage VDD has reached a sufficient level, and the system is initialized only when this power up signal PWR_UP is generated.

That is, the monitor circuit 204 tests the state of the memory 202 while the power up signal PWR_UP is generated and the system is initialized.

The flag register 106 is made up of registers for storing respective flags representing the states of major components of the memory 102, in which the monitor results of the monitor circuit 104 are stored.

The first switch 108 is switched by the power-up signal PWR_UP or the user input control signal USER_IN, and transmits the flag bits stored in the flag register 106 to the user register 110 so as to be stored. do.

The first switch 208 is switched by the output signal of the OR gate 118, and the input of the OR gate 118 is a power up signal PWR_UP and a user input control signal USER_IN. Therefore, when at least one of the power-up signal PWR_UP and the user input control signal USER_IN is activated to a high level, the output of logic 1 is generated to turn on the first switch 108.

The user register 110 stores the flag bits passed from the flag register 106 through the first switch 108. The flag bits stored in the user register 110 are then output to the pad 216 by the user output control signal USER_OUT when requested by the user.

The second switch 112 is switched by the user output control signal USER_OUT and transfers flag bits output from the user register 110 to the third switch 114.

The third switch 114 is switched by the user output control signal USER_OUT, and selectively connects one of the second switch 112 and the input / output terminal I / O of the memory 102 with the pad 116. . If the third switch 214 is connected to the second switch 112, the flag bits of the user register 110 may be output to the outside through the pad 116. On the contrary, when the third switch 214 is connected to the input / output terminal I / O of the memory 102, output data output from the memory 102 is output through the pad 116 or the pad 116. Input data that is input through is transferred to the memory 102.

2 is a timing diagram illustrating an operating characteristic of a self test circuit of a semiconductor memory according to the present invention. As shown in FIG. 2, when a predetermined time Δt elapses while the power supply voltage VDD rises to reach a sufficient level, the power-up signal PWR_UP is activated to a high level. The first data DATA # 1 is stored in the user register 110 by this power-up signal PWR_UP, or by the user input control signal USER_IN generated arbitrarily by the user. Second data DATA # 2 may be stored.

If the user output control signal USER_OUT is generated by the user while the first data DATA # 1 or the second data DATA # 2 are stored in the user register 110, the user register 110 at that time. ) Data (DATA # 1 or DATA # 2) stored in the () is output through the pad 116.

The self test circuit of the semiconductor memory according to the present invention automatically performs a self test when the system is powered up, stores the result, and then outputs a test result whenever a user requests, thereby allowing an external user to check the state of the semiconductor memory. It has the advantage of being easy to grasp.

Claims (2)

A monitor circuit that initializes the memory upon power-on and checks the state of the memory; A flag register for storing the monitor result of the monitor circuit as a flag bit of logic 1 or logic 0; A first switch switched by a power up signal or a user input control signal; A user register configured to receive and store flag bits stored in the flag register through the first switch; A second switch switched by a user output control signal; Switched by a user output control signal, connected to the second switch and the input and output terminals of the memory, selects one of the flag bit of the user register and the output signal of the memory transmitted through the second switch to the pad A self test circuit of a semiconductor memory comprising a third switch for transmitting. The method according to claim 1, wherein the power up signal, Self-test circuit of a semiconductor memory, characterized in that when the power supply voltage reaches a predetermined level for more than a predetermined time is generated in the form of a pulse signal to initialize the memory.