KR20020015165A - Method of semiconductor device using salicidation - Google Patents
Method of semiconductor device using salicidation Download PDFInfo
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- KR20020015165A KR20020015165A KR1020000048336A KR20000048336A KR20020015165A KR 20020015165 A KR20020015165 A KR 20020015165A KR 1020000048336 A KR1020000048336 A KR 1020000048336A KR 20000048336 A KR20000048336 A KR 20000048336A KR 20020015165 A KR20020015165 A KR 20020015165A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims abstract description 28
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 30
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 150000002500 ions Chemical class 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 230000009969 flowable effect Effects 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 3
- 125000006850 spacer group Chemical group 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- 238000005755 formation reaction Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000000053 physical method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로, 좀더 구체적으로 샐리사이드(salicide: self-aligned silicide) 공정을 사용하는 반도체 장치의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device using a salicide (self-aligned silicide) process.
반도체 소자의 동작 속도를 향상시키기 위하여 단위 소자들을 전기적으로 연결시키는 금속 배선의 저항을 감소시키는 것이 요구된다. 특히, MOSFET 구조의 소자에서는 게이트 전극 및 소오스/드레인의 저항을 감소시키는 것이 요구되며, 이를 위하여 게이트 전극 및 소오스/드레인 영역에 저저항 물질인 실리사이드막을 형성하는 샐리사이드 공정이 널리 사용되고 있다.In order to improve the operating speed of the semiconductor device, it is required to reduce the resistance of the metal wiring that electrically connects the unit devices. In particular, it is required to reduce the resistance of the gate electrode and the source / drain in a device having a MOSFET structure, and for this purpose, a salicide process for forming a silicide layer, which is a low resistance material, is widely used in the gate electrode and the source / drain region.
통상적으로 샐리사이드 공정은 게이트 전극 및 소오스/드레인 영역을 포함하는 반도체 기판 전면에 코발트(Co) 또는 티타늄(Ti)과 같은 금속막을 형성한 후 열처리하여 게이트 전극 및 소오스/드레인 영역의 상부에 CoSi2또는 TiSi2등과 같은 실리사이드막을 형성하는 방법으로 진행된다.In general, a salicide process forms a metal film such as cobalt (Co) or titanium (Ti) on the front surface of a semiconductor substrate including a gate electrode and a source / drain region, and then heat-treats the CoSi 2 on the gate electrode and the source / drain region. Or a method of forming a silicide film such as TiSi 2 or the like.
이하, 도 1 및 도 2를 참조하여 종래 기술의 문제점을 설명한다.Hereinafter, the problems of the prior art will be described with reference to FIGS. 1 and 2.
도 1a 내지 도 1d는 종래 기술에 의한 샐리사이드 공정을 사용하는 반도체 장치의 제조 방법을 설명하는 단면도들이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device using a salicide process according to the prior art.
도 1a를 참조하면, 반도체 기판(10)에 게이트 산화막(12)을 형성한다. 게이트 산화막(12) 상에 및 게이트 전극막인 폴리실리콘막(13)을 형성한다. 패터닝 공정으로 게이트 산화막(12) 및 게이트 전극막(13)이 차례로 적층된 게이트 패턴(15)을 형성한다. 게이트 패턴(15) 양옆의 활성 영역에 불순물 이온을 낮은 도우즈로주입하여 저농도의 불순물층을 형성한다. 불순물층이 형성된 반도체 기판(10) 전면에 절연막을 형성한 후 이방성 식각하여 게이트 패턴(15)의 양측벽에 스페이서(17)를 형성한다. 스페이서(17)가 형성된 반도체 기판(10) 전면에 도전형의 불순물 이온을 높은 도우즈로 주입하여 게이트 패턴(15) 양옆에 소오스/드레인(20) 영역을 형성한다.Referring to FIG. 1A, a gate oxide film 12 is formed on a semiconductor substrate 10. The polysilicon film 13 which is a gate electrode film and on the gate oxide film 12 is formed. In the patterning process, the gate pattern 15 in which the gate oxide film 12 and the gate electrode film 13 are sequentially stacked is formed. Impurity ions are injected into the active regions on both sides of the gate pattern 15 at low doses to form a low concentration impurity layer. An insulating layer is formed on the entire surface of the semiconductor substrate 10 on which the impurity layer is formed, and then anisotropically etched to form spacers 17 on both sidewalls of the gate pattern 15. A conductive dopant ion is implanted into the entire surface of the semiconductor substrate 10 on which the spacers 17 are formed with a high dose to form source / drain 20 regions on both sides of the gate pattern 15.
도 1b 내지 도 1d를 참조하면, 소오스/드레인(20) 영역이 형성된 반도체 기판(10) 전면에 금속막(23)을 형성한 후 열처리한다. 그러면, 금속막(23)이 하부의 실리콘과 반응하여 게이트 전극막(13)의 상부와 소오스/드레인(20) 영역의 상부에 금속 실리사이드막(24)이 형성된다. 반면, 절연막 스페이서(17)가 형성된 부분에는 실리사이드막(24)이 형성되지 않아 금속막(23)이 그대로 남게 된다. 절연막 스페이서(17) 상에 남아있는 금속막(23)을 제거한다. 그러면, 저저항 실리사이드막(24)이 상부에 형성된 게이트 전극 및 소오스/드레인 영역이 완성된다.1B to 1D, the metal film 23 is formed on the entire surface of the semiconductor substrate 10 where the source / drain 20 region is formed, and then heat-treated. As a result, the metal film 23 reacts with the lower silicon to form the metal silicide film 24 on the gate electrode film 13 and on the source / drain 20 region. On the other hand, the silicide film 24 is not formed in the portion where the insulating film spacers 17 are formed so that the metal film 23 remains. The metal film 23 remaining on the insulating film spacer 17 is removed. Then, the gate electrode and the source / drain regions in which the low resistance silicide layer 24 is formed are completed.
이러한 종래 기술에 의하면, 게이트 전극(13)의 상부와 소오스/드레인(20) 영역 모두에 실리사이드막(24)이 형성된다. 그런데, 도 2에 도시된 바와 같이, 소오스/드레인(20) 영역 내부에서 실리사이드막(24)의 프로파일이 불량하게 형성된 경우, 실리사이드막(24)에 기인한 접합 누설 전류가 발생하여 소자의 전기적인 특성을 저하시키게 된다.According to this conventional technique, the silicide film 24 is formed on both the top of the gate electrode 13 and the region of the source / drain 20. However, as shown in FIG. 2, when the profile of the silicide film 24 is poorly formed in the source / drain 20 region, a junction leakage current due to the silicide film 24 is generated so that the device is electrically connected. It will lower the characteristics.
또한, 정전기(electrostatic discharge; ESD)에 의한 칩 파괴를 방지하기 위한 ESD 트랜지스터의 경우 드레인단의 저항이 높아야 정전기에 대한 보호 특성을 극대화할 수 있다. 그런데, 드레인 영역에 저저항 실리사이드막이 형성되면, 드레인의 길이를 증가시키는 물리적인 방법으로는 정전기를 극복할 수 있는 높은 저항을 얻기 어렵다는 문제가 있다.In addition, in the case of an ESD transistor for preventing chip destruction by electrostatic discharge (ESD), the resistance of the drain terminal must be high to maximize the protection against static electricity. However, when the low resistance silicide film is formed in the drain region, there is a problem that it is difficult to obtain a high resistance capable of overcoming static electricity by a physical method of increasing the length of the drain.
즉, 실리사이드막의 형성은 저저항 배선을 구현하여 소자의 동작 속도를 증가시킨다는 이득이 있지만, 일부 소자에서는 오히려 특성 저하를 야기할 수 있으므로 선택적으로 실리사이드막을 형성하는 공정이 요구되는 추세이다. 특히, 게이트 전극에만 실리사이드를 형성하고 소오스/드레인 영역에는 실리사이드를 형성하지 않는 기술이 요구되고 있다.That is, the formation of the silicide film has the advantage of increasing the operation speed of the device by implementing low resistance wiring, but in some devices it may cause a deterioration of characteristics, so a process of selectively forming the silicide film is required. In particular, there is a demand for a technique in which silicide is formed only in the gate electrode and silicide is not formed in the source / drain regions.
본 발명은 상술한 제반 문제를 해결하기 위해 제안된 것으로, 게이트 전극에만 선택적으로 실리사이드를 형성할 수 있는 반도체 장치의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a method of manufacturing a semiconductor device capable of selectively forming silicide only on a gate electrode.
도 1a 내지 도 1d는 종래 기술에 의한 반도체 장치의 제조 방법을 설명하기 위한 단면도들이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2는 종래 기술에 의해 제조된 반도체 장치의 문제점을 설명하기 위한 단면도이다.2 is a cross-sectional view illustrating a problem of a semiconductor device manufactured by the prior art.
도 3a 내지 도 3g는 본 발명의 실시예에 의한 반도체 장치의 제조 방법을 설명하기 위한 단면도들이다.3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10, 100 : 반도체 기판 12, 102 : 게이트 산화막10, 100: semiconductor substrate 12, 102: gate oxide film
13, 103 : 게이트 전극막 15, 105 : 게이트 패턴13, 103: gate electrode film 15, 105: gate pattern
17, 110 : 스페이서 20, 112 : 소오스/드레인 영역17, 110: spacer 20, 112: source / drain region
115 : 제 1 절연막 117 : 제 2 절연막115: first insulating film 117: second insulating film
23, 120 : 금속막 24, 122 : 실리사이드막23, 120: metal film 24, 122: silicide film
(구성)(Configuration)
상술한 목적을 달성하기 위한 본 발명은, 반도체 기판 상에 게이트 산화막 및 게이트 전극막을 차례로 형성한 후 패터닝하여 게이트 패턴을 형성한다. 게이트 패턴의 양옆에 도전형의 불순물 이온을 주입하여 소오스/드레인 영역을 형성한다. 소오스/드레인 영역이 형성된 반도체 기판 전면에 절연막을 형성하고, 게이트 전극막이 노출되도록 절연막을 식각한다. 노출된 게이트 전극막을 포함하는 절연막 상에 금속막을 형성하고 열처리하면, 상기 노출된 게이트 전극막에만 선택적으로 금속 실리사이드막이 형성된다.In order to achieve the above object, the present invention forms a gate pattern by sequentially forming a gate oxide film and a gate electrode film on a semiconductor substrate and then patterning the gate oxide film. A conductive type impurity ion is implanted on both sides of the gate pattern to form a source / drain region. An insulating film is formed over the semiconductor substrate on which the source / drain regions are formed, and the insulating film is etched to expose the gate electrode film. When a metal film is formed on the insulating film including the exposed gate electrode film and subjected to heat treatment, a metal silicide film is selectively formed only on the exposed gate electrode film.
바람직하게는 상기 절연막을 형성한 후 절연막 상에 평탄화 특성이 좋은 유동성막을 형성하는 단계를 더 포함한다.Preferably, the method further includes forming a flowable film having good planarization characteristics on the insulating film after forming the insulating film.
또한, 상기 절연막은 실리콘 산화막 또는 실리콘 질화막으로 형성하는 것이 바람직하다.In addition, the insulating film is preferably formed of a silicon oxide film or a silicon nitride film.
(실시예)(Example)
이하, 도 3을 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 3.
도 3a 및 도 3g는 본 발명의 실시예에 의한 반도체 장치의 제조 방법을 설명하기 위한 단면도들이다.3A and 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 3a를 참조하면, 반도체 기판(100)의 소정 영역에 활성 영역을 한정하는 소자분리막(도면에 미도시)을 형성한다. 소자분리막은 통상적인 로코스(LOCOS) 공정 또는 트렌치 소자분리 공정을 사용하여 형성한다. 소자분리막이 형성된 반도체 기판(100) 전면에 게이트 산화막(102)을 형성한다. 게이트 산화막(102) 상에 게이트 전극막(103), 바람직하게는 폴리실리콘막을 형성한다. 패터닝 공정으로 게이트 산화막(102) 및 게이트 전극막(103)이 차례로 적층된 게이트 패턴(105)을 형성한다.Referring to FIG. 3A, an isolation layer (not shown) defining an active region is formed in a predetermined region of the semiconductor substrate 100. The device isolation film is formed using a conventional LOCOS process or a trench device isolation process. A gate oxide layer 102 is formed on the entire surface of the semiconductor substrate 100 on which the device isolation layer is formed. A gate electrode film 103, preferably a polysilicon film, is formed on the gate oxide film 102. In the patterning process, the gate pattern 105 in which the gate oxide film 102 and the gate electrode film 103 are sequentially stacked is formed.
도 3b를 참조하면, 게이트 패턴(105) 양옆의 활성 영역에 도전형의 불순물 이온을 낮은 도우즈(dose)로 주입하여 LDD(lightly doped drain) 영역을 형성하기 위한 저농도의 불순물층(107)을 형성한다. 저농도의 불순물층(107)이 형성된 반도체 기판(100) 전면에 절연막을 형성한 후 이방성 식각하여 게이트 패턴(105)의 양측벽에 스페이서(110)를 형성한다. 스페이서(110) 형성용 절연막은 실리콘 질화막또는 실리콘 산화막으로 형성한다.Referring to FIG. 3B, a low concentration impurity layer 107 is formed to form a lightly doped drain (LDD) region by implanting a conductive dopant ion with low dose into the active regions on both sides of the gate pattern 105. Form. An insulating layer is formed on the entire surface of the semiconductor substrate 100 having the low concentration impurity layer 107 and then anisotropically etched to form spacers 110 on both sidewalls of the gate pattern 105. The insulating film for forming the spacer 110 is formed of a silicon nitride film or a silicon oxide film.
도 3c를 참조하면, 스페이서(110)가 형성된 게이트 패턴(105)의 양옆에 도전형의 불순물 이온을 높은 도우즈로 주입하여 소오스/드레인(112) 영역을 형성한다. 이때, 노출된 게이트 전극막(103)에도 불순물 이온이 주입되므로, 게이트 전극막(103)이 소오스/드레인(112) 영역에 주입되는 이온과 동일한 불순물 이온으로 도핑된다.Referring to FIG. 3C, source / drain 112 regions are formed by implanting a conductive dopant ion with a high dose on both sides of the gate pattern 105 on which the spacers 110 are formed. At this time, since the impurity ions are implanted into the exposed gate electrode film 103, the gate electrode film 103 is doped with the same impurity ions as the ions implanted into the source / drain 112 region.
도 3d를 참조하면, 소오스/드레인(112) 영역이 형성된 반도체 기판(100) 전면에 본 발명의 특징으로, 게이트 전극막 패턴(103) 상부에만 선택적으로 실리사이드막을 형성하기 위한 제 1 절연막(115)을 형성한다. 제 1 절연막(115)은 실리콘 산화막 또는 실리콘 질화막으로 형성하고, 후속 공정에서 형성되는 금속막이 소오스/드레인(112) 영역의 반도체 기판(100)과 반응하는 것을 방지할 수 있을 정도의 충분한 두께로 형성하는 것이 바람직하다. 예를 들어, 후속 식각 공정 후에 소오스/드레인(112) 영역 상에 남아있는 제 1 절연막(115)의 두께가 100 Å 이상이 되도록 형성한다. 또한, 제 1 절연막(115)은 게이트 패턴(105) 부위와 소오스/드레인(112) 영역의 단차를 최소화시킬 수 있는 증착 조건으로 형성하는 것이 바람직하다.Referring to FIG. 3D, the first insulating layer 115 for selectively forming a silicide layer only on the gate electrode layer pattern 103 may be formed on the entire surface of the semiconductor substrate 100 on which the source / drain 112 regions are formed. To form. The first insulating film 115 is formed of a silicon oxide film or a silicon nitride film, and is formed to a thickness sufficient to prevent the metal film formed in a subsequent process from reacting with the semiconductor substrate 100 in the source / drain 112 region. It is desirable to. For example, the thickness of the first insulating film 115 remaining on the source / drain 112 region after the subsequent etching process is formed to be 100 GPa or more. In addition, the first insulating layer 115 may be formed under deposition conditions to minimize the step difference between the gate pattern 105 and the source / drain 112 region.
제 1 절연막(115)을 형성한 후, 게이트 패턴(105)이 형성된 부위와 소오스/드레인(112) 영역의 단차가 충분히 감소되지 못한 경우에는, 제 1 절연막(115) 상에 평탄화 특성이 우수한 유동성막으로 제 2 절연막(117)을 형성한다. 제 2 절연막(117)은 예를 들어, 포토레지스트막 또는 SOG(spin on glass)막으로 형성한다. 이때, 제 1 절연막(115) 또는 제 2 절연막(117)이 형성된 후의 단차는 게이트 패턴(105)의 높이에서 실리사이드의 형성 반응을 억제하기 위해 필요한 절연막의 최소 두께를 뺀 값보다 작아야 한다. 그렇지 않으면, 후속 식각 공정 후에 소오스/드레인(112) 영역 상에 실리사이드 형성 반응을 억제하기에 충분한 절연막이 남지 않는다.After the first insulating film 115 is formed, when the step difference between the portion where the gate pattern 105 is formed and the source / drain 112 region is not sufficiently reduced, the fluidity of the planarization characteristic is excellent on the first insulating film 115. The second insulating film 117 is formed of a film. The second insulating film 117 is formed of, for example, a photoresist film or a spin on glass (SOG) film. At this time, the step after the first insulating film 115 or the second insulating film 117 is formed should be less than the value of the height of the gate pattern 105 minus the minimum thickness of the insulating film required to suppress the formation reaction of the silicide. Otherwise, no sufficient insulating film remains on the source / drain 112 region after the subsequent etching process to inhibit the silicide formation reaction.
도 3e를 참조하면, 게이트 패턴(105)의 상면, 즉 게이트 전극막(103)이 노출될 때까지 제 2 절연막(117) 및 제 1 절연막(115)을 식각한다. 이때, 식각 공정은 제 1 절연막(115) 및 제 2 절연막(117) 간의 식각선택비는 낮고, 제 1 및 제 2 절연막(115,117)과 게이트 전극막(103) 간의 식각 선택비는 높은 조건의 건식 식각 또는 습식 식각을 사용하여 진행한다. 그러면, 게이트 전극막(103)은 노출되고, 소오스/드레인 영역(112) 상에는 실리사이드막의 형성 반응을 방지하기 위한 제 1 절연막(115)이 남게 된다. 여기서, 게이트 전극막(103)을 노출시킨 후 제 1 절연막(115) 상에 제 2 절연막(117)이 남게 되는 경우에는 제 2 절연막(117)을 제거하기 위한 식각 공정을 진행한다.Referring to FIG. 3E, the second insulating layer 117 and the first insulating layer 115 are etched until the upper surface of the gate pattern 105, that is, the gate electrode layer 103 is exposed. At this time, in the etching process, the etching selectivity between the first insulating film 115 and the second insulating film 117 is low, and the etching selectivity between the first and second insulating films 115 and 117 and the gate electrode film 103 has a high dry condition. Proceed with etching or wet etching. As a result, the gate electrode film 103 is exposed, and the first insulating film 115 for preventing a silicide film forming reaction remains on the source / drain region 112. Here, when the second insulating film 117 remains on the first insulating film 115 after the gate electrode film 103 is exposed, an etching process for removing the second insulating film 117 is performed.
도 3f 및 도 3g를 참조하면, 제 1 절연막(115) 및 노출된 게이트 전극막(103) 상에 금속막(117)을 형성한다. 금속막(117)은 예를 들어, 코발트 또는 티타늄으로 형성한다. 이어서, 금속막(117)이 형성된 결과물을 300 ℃ 이상의 온도로 열처리한다. 그러면, 금속막(117)이 노출된 게이트 전극막(103), 즉 폴리실리콘막과 반응하여 게이트 전극막(103)의 상부에만 선택적으로 금속 실리사이드막(122)이 형성된다. 이때, 소오스/드레인 영역에는 제 1 절연막(115)이 소정 두께로 형성되어 있으므로, 활성 영역의 반도체 기판(100)과 금속막(117) 간의 반응은 일어나지 않게 된다.3F and 3G, a metal film 117 is formed on the first insulating film 115 and the exposed gate electrode film 103. The metal film 117 is made of cobalt or titanium, for example. Subsequently, the resultant on which the metal film 117 is formed is heat-treated at a temperature of 300 ° C. or higher. Then, the metal silicide layer 122 is selectively formed only on the gate electrode layer 103 by reacting with the gate electrode layer 103, that is, the polysilicon layer, to which the metal layer 117 is exposed. At this time, since the first insulating film 115 is formed to have a predetermined thickness in the source / drain region, the reaction between the semiconductor substrate 100 and the metal film 117 in the active region does not occur.
제 1 절연막(115) 상에 반응하지 않고 남아있는 금속막(117)을 습식 식각으로 제거한다. 그러면, 폴리실리콘막(103) 상부에 금속 실리사이드막(122)이 적층된 게이트 전극이 형성되고, 게이트 패턴(105) 양옆의 활성 영역에는 제 1 절연막(115)이 남는다. 이후, 바람직하게는 실리사이드막(122)을 안정화시키고 저저항화시키기 위한 추가의 후속 열처리 공정을 진행한다. 후속 열처리 공정은 예를 들어, 700 ℃ 이상의 고온에서 진행한다.The metal film 117 remaining on the first insulating film 115 without reacting is removed by wet etching. As a result, a gate electrode in which the metal silicide layer 122 is stacked is formed on the polysilicon layer 103, and the first insulating layer 115 remains in the active regions on both sides of the gate pattern 105. Thereafter, an additional subsequent heat treatment process is preferably performed to stabilize and lower the silicide film 122. The subsequent heat treatment process proceeds, for example, at a high temperature of 700 ° C. or higher.
이와 같은 발명에 의하면, 샐리사이드 공정을 진행하기 전에 절연막을 형성한 후 원하는 부위만 선택적으로 노출시켜 금속 실리사이드막을 형성하게 되므로, 국부적인 샐리사이드 공정이 가능해진다.According to the present invention, since the insulating film is formed before the salicide process is performed, only a desired portion is selectively exposed to form a metal silicide film, thereby allowing a local salicide process.
본 발명은 절연막을 형성하여 게이트 패턴의 상면만 노출시킨 후 샐리사이드 공정을 진행함으로써, 게이트 전극막의 상부에만 선택적으로 실리사이드막을 형성할 수 있게 된다. 이에 따라, 원하는 부위만 실리사이드막을 형성할 수 있으므로, 소자의 신뢰성을 향상시키는 효과가 있다.According to the present invention, a silicide film can be selectively formed only on the gate electrode film by forming an insulating film to expose only the top surface of the gate pattern and then performing a salicide process. Thereby, since only a desired site | part can form a silicide film, there exists an effect which improves the reliability of an element.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100356472B1 (en) * | 2000-12-29 | 2002-10-14 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| KR100587593B1 (en) * | 2002-07-12 | 2006-06-08 | 매그나칩 반도체 유한회사 | Method of making selective silicide using cmp |
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2000
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100356472B1 (en) * | 2000-12-29 | 2002-10-14 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| KR100587593B1 (en) * | 2002-07-12 | 2006-06-08 | 매그나칩 반도체 유한회사 | Method of making selective silicide using cmp |
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