KR20020012077A - A method for fabricating heterojunction bipolar transistor - Google Patents

Abstract

PURPOSE: A method for manufacturing a hetero-junction bipolar transistor(HBT) is provided to reduce a modulation degree of a base, by uniformly controlling the flow of current injected to an emitter while precisely controlling the density in a very thin region. CONSTITUTION: A lower collector(2) and a collector Si epitaxial layer(3) are formed on a silicon substrate(1). An isolation layer is formed on the silicon substrate. A collector plug(6) and a selective implanted collector(SIC) region are formed in the active region of the silicon substrate. A mask insulation layer pattern wherein the SIC region is opened is formed on the resultant structure. A Si epitaxial layer is selectively grown by using the mask insulation layer pattern such that the Si epitaxial layer is partially and laterally over-grown on the mask insulation layer pattern. A SiGe base epitaxial layer(10) is grown on the resultant structure, and a plurality of second-dimensional doping layers are formed in the SiGe base epitaxial layer. The SiGe base epitaxial layer is patterned to define a base region. The emitter in contact with the SiGe base epitaxial layer is formed.

Description

A method for fabricating heterojunction bipolar transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method for manufacturing a heterojunction bipolar transistor (HBT).

SiGe semiconductor is a semiconductor material composed of silicon (Si) and germanium (Ge), and has the advantage of controlling physical properties such as energy band and carrier mobility as desired. The technology related to SiGe hetero devices has been rapidly developed in recent years, and among them, HBT has been commercialized in a wide range of applications and frequency domains such as RF circuits required for wireless communication and optical communication. In addition, SiGe hetero devices such as heterostructure field effect transistor (HFET) and heterostructure complementary metal-oxide-semiconductor (HCMOS) have been developed to meet high-speed operation and high integration.

SiGe HBT has succeeded in commercializing for the first time among silicon hetero devices, and has matured enough in manufacturing technology to compete with group III-V compound semiconductors in yield, reliability, integration, and production cost. Therefore, various SiGe hetero devices, such as digital, analog, RF, microwave, and optoelectronic devices, are already commercially available, and above all, 1Gbit-level CMOS technology and 1 ~ The SiGe BiCMOS, which combines 12 GHz HBT technology, implements a system-on-a-chip.

SiGe is a ratio of the critical frequency f _t to the maximum allowable frequency f _max , i.e., f _t / f _max is large, the early voltage is high, and the base-emitter junction is precisely controlled and the base is larger than the conventional Si semiconductor. There is an advantage of accelerating the movement of electrons by the high electric field present in the. Compared with GaAs, which is a III-V semiconductor, it has advantages such as single power supply, low power use by low turn-on voltage, low 1 / f noise, low parasitics and economic efficiency. SiGe devices, on the other hand, are capable of 3V operation and can be powered by either a single-cell Lithium-Ion or three-cell Nickel Metal Hydride (NiMH) battery, reducing power consumption with weight / size. As it can be reduced, it is very suitable to be applied as a part of mobile communication terminal.

SiGe HBT differs in that the base layer by ion implantation used in general BJT is replaced with SiGe epi. High gain in HBT is achieved by blocking the injection of holes due to the large off-set of the balance band at the base-emitter interface, and reducing the turn-on voltage by reducing the off-set of the conduction band. Reduce In addition, the highly doped 5-10 nm thick base reduces the modulation of the base to increase linearity, increase the critical frequency f _t , and at the same time lower the resistance of the base, greatly increasing the maximum allowable frequency f _max .

The highest critical frequency f _t (= 116 GHz) and the maximum allowable frequency f _max (= 160 GHz) have been published by the Daimler-Chrysler research group, and currently f _t / f _max is usually 70- The device is designed and used at 80 GHz. The noise figure of SiGe HBT is very good, keeping 0.5 to 1 dB at 2 to 12 GHz. In the characteristics of low frequency noise, the corner frequency f _c from 1 / f noise to shot noise can be obtained at the lowest value of f _c = 0.1 to 10 kHz for 10 to 100 GHz operation. ) Shows the best characteristics for the fabrication.

The possibility of SiGe was first presented in 1957. However, due to the lack of understanding of the physical properties of SiGe semiconductors, the fabrication of heterostructures by epitaxial growth, and the understanding of the characteristics of dipole devices, a long period of development was required. Applicable SiGe cold growth began to be announced, and in 1987, SiGe HBT, which was operated by Meyerson, who developed UHV-CVD, was announced. Thus, in 1990, the critical frequency f _t exceeded 75 GHz, and by 1995 Daimler-Benz announced the high frequency characteristic of f _t / f _max = 130/160 GHz, Showed its applicability. With the development of these unit devices, SiGe BiCMOS began to be developed in 1992, and in 1994 IBM announced that it would produce SiGe HBT on 8-inch silicon substrates. Practically speaking, IBM, Temic, Maxim, and SGS Thomson have been using LNAs, mixers, power amplifiers, and voltage controls throughout 1998 and 1999. With the launch of oscillators (VCOs), commercialization of SiGe integrated devices is in full swing.

However, there is still a lot of room for improvement in epi technology and device structure in order to develop a technology that can be used in common with the process technology of CMOS to reduce the steps of the process and to improve the performance.

1 is a cross-sectional view of a SiGe HBT manufactured according to the prior art, the manufacturing process of which is as follows.

First, the lower collector 2 is formed through selective ion implantation on the silicon substrate 1, the Si epilayer is grown on the surface of the silicon substrate 1, and ion implantation is performed to form the collector epilayer 3. . Subsequently, a LOCOS oxide film 4 for isolation of the device is grown using a pattern made of a SiN thin film (not shown) as a mask on a substrate on which the collector epilayer 3 is formed.

Subsequently, the SiN thin film was removed, and the collector plug 6 and the collector selective ion implanted collector (hereinafter referred to as SIC) 7 were sequentially formed through an ion implantation mask process and an ion implantation process, and the upper part of the entire structure. The SiGe base epitaxial layer 10 is grown.

Next, a polysilicon film is deposited on the SiGe base epi layer 10 and patterned to form the emitter 11 and the collector, and ion implantation is performed to form an external base. Reference numeral '12' denotes a sidewall spacer, and '17' denotes an impurity region by external base ion implantation, respectively.

However, the conventional SiGe HBT manufactured through the above process has a high leakage current between the base and the collector and a large junction capacitance, so that the maximum permissible frequency is used for a high-integrated circuit such as BiCMOS of Mbit class. There was a low issue. In addition, there is a problem in that the reliability and linear characteristics deteriorate because it is difficult to precisely control the doping concentration inside the very thin base.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a heterojunction dipole transistor capable of reducing leakage current and junction capacitance between a base and a collector, and precisely adjusting a doping concentration in a base.

1 is a cross-sectional view of a SiGe HBT prepared according to the prior art.

2A to 2G are SiGe HBT manufacturing process diagram according to an embodiment of the present invention.

3A is a representative impurity distribution diagram when impurity distribution and heat treatment for impurity redistribution are performed when three-dimensional doping is performed to grow the base epi.

FIG. 3B is an impurity distribution diagram when four two-dimensional doping is performed and retrograde doping is performed. FIG.

4A is an electric field distribution diagram of a bipolar transistor manufactured by conventional continuous doping.

4B is an electric field distribution diagram when a plurality of high concentration two-dimensional doped layers are disposed at a uniform concentration in accordance with the present invention.

4C is an electric field distribution diagram when a plurality of high concentration two-dimensional doped layers are disposed with a gradient of concentration according to the present invention.

* Explanation of symbols for the main parts of the drawings

1: silicon substrate 2: lower collector

3: collector epi layer 4: LOCOS oxide film

5: oxide film 6: collector plug

7: Selective ion implanted collector 8: Photoresist pattern

9: Si SEG layer 10: base epi layer

11: emitter 12: oxide film sidewall spacer

13: SiGe epi layer 14: Ti / TiN film

15 Ti silicide 16 Metal wiring

In order to achieve the above technical problem, the present invention is characterized in that in the method of manufacturing a heterojunction dipole transistor having a SiGe base epi layer, a plurality of two-dimensional doping is performed during the growth of the SiGe base epi layer.

In another aspect, the present invention, the first step of forming a lower collector and a collector Si epi layer on the silicon substrate; Forming a device isolation film on the silicon substrate; A third step of forming a collector plug and a select ion implanted collector (SIC) in an active region of the silicon substrate; A fourth step of forming a mask insulating layer pattern on which the collector (SIC) region in which the selection ion implantation is opened is formed on the entire structure after the third step; A fifth step of selectively growing a Si epitaxial layer using the mask insulating layer pattern, wherein the Si epitaxial layer is also grown on the mask insulating layer pattern on the side surface to a certain degree; Growing a SiGe base epitaxial layer on the entire structure after the fifth step, and forming a plurality of two-dimensional doped layers in the SiGe base epitaxial layer; A seventh step of patterning the SiGe base epi layer to define a base region; And an eighth step of forming an emitter contacting the SiGe base epi layer.

Preferably, the eighth step may include: a ninth step of forming the emitter using a doped polysilicon film; A tenth step of performing the external base ion implantation; And an eleventh step of forming a sidewall spacer insulating layer on the emitter sidewall.

Preferably, after performing the eleventh step, a twelfth step of selectively growing a SiGe or Si epilayer on the exposed doped polysilicon film and the exposed SiGe base epilayer surface; Forming a high melting point metal barrier layer along the entire structure surface of the twelfth step; Performing a heat treatment to form a silicide layer on surfaces of the doped polysilicon layer and the SiGe base epitaxial layer; And a fifteenth step of removing the unreacted high melting point metal barrier layer.

Preferably, the mask insulating film pattern is formed of a low temperature oxide film.

Preferably, the SiGe base epi layer has a stacked structure of a Si seed layer / SiGe epi layer / Si cap layer.

Preferably, the plurality of two-dimensional doped layers are formed at regular intervals in the SiGe epi layer, or are formed at regular intervals with a concentration gradient in the SiGe epi layer.

That is, the method of manufacturing SiGe HBT according to the present invention forms a self-aligned base-collector junction by using self-aligned base-emitter junction and selective growth using oxide sidewalls to reduce leakage current and operate at high frequency. It improves the uniformity of the device and the base epi layer by forming a plurality of two-dimensional doping layers so that the doping concentration of the base can be locally controlled in a very thin area in a desired shape, and during and after the growth process. By minimizing the diffusion of impurities, it provides the advantage of precisely controlling the doping concentration in a very thin base, making it possible to manufacture devices with excellent linear characteristics and low leakage current in high speed operation. The present invention can be usefully used for the next generation ultra-fine silicon semiconductor or quantum device fabrication process requiring low temperature process.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

2A to 2G illustrate a SiGe HBT manufacturing process according to an embodiment of the present invention, which will be described below with reference to the drawings.

In the SiGe HBT manufacturing process according to the present embodiment, first, as shown in FIG. 2A, as ion is injected into the silicon substrate 1 having a resistivity of 5 to 8 ohm · cm at 80 keV, the lower collector 2 is injected. After the formation, the Si epilayer is grown using dichlorosilane (DCS) gas in atmospheric pressure chemical vapor deposition (APCVD) mode, and P ion is implanted to form the collector epilayer 3. Subsequently, a LOCOS oxide film 4 for isolation of the device is grown using a pattern formed by depositing a SiN thin film (not shown) in a thickness of 160 nm on a substrate on which the collector epi layer 3 is formed.

Subsequently, the SiN thin film is removed and the oxide film 5 is deposited on the entire structure, and then the collector plug 6 is formed through an ion implantation mask process and an ion implantation process (n-type impurities), and the emitter and the base are formed. A photoresist pattern 8 for opening the emitter region for self alignment is formed on the oxide film 5, and n-type impurities are ion implanted to form a selective ion implanted collector (SIC) 7. Here, the oxide film 5 preferably uses a low temperature oxide film (LTO), and serves to protect the substrate during the ion implantation process.

Prior to loading the wafer into the growth chamber from above, the wafer is washed successively in a 4: 1 H ₂ SO ₄ / H ₂ O ₂ solution and a 100: 1H ₂ O / HF solution to remove the native oxide film and impurities from the substrate surface. After that, the natural oxide film adsorbed to the surface in a very short time is removed by heat treatment with a hydrogen atmosphere in the chamber of the growth apparatus. The APCVD growth apparatus is heated by a tungsten-halogen lamp at the top and bottom of the quartz chamber to provide rapid heat treatment. The growth chamber is a rectangular parallelepiped structure in which gas is injected from one side to be pumped to the opposite side through the substrate, and the wafer is rotated at 0 to 50 rpm to grow a very uniform epi with less than 1% of thin film thickness variation. Let's do it. The hot plate on which the wafer is placed uses a SiC coated graphite plate to prevent out-gassing of the impurity gas. The reaction gases SiH ₄ , GeH ₄ (1.5% in H ₂ ), PH ₃ (5% in H ₂ ), B ₂ H ₆ (1000 ppm in H ₂ ) are high purity of 99.990% or higher and H ₂ Is fed through an in-line purifier.

Since the collector uses Si epi, it is deposited in APCVD mode using DCS gas at a high temperature of 1100 ^o C. DCS is pyrolyzed at temperatures above approximately 1080 ^o C, and at higher temperatures, the growth rate of the silicon epi is grown in diffusion control mode, which is independent of temperature changes and depends entirely on the dosage of the DCS source. That is, the DCS can be described by the Precursor mediated desorption model in which the DCS is grown on the silicon substrate 1 at about 1000 ^o C or less, and the main Kinetic reactor is represented by the following scheme 1. Can be.

SiH ₂ Cl ₂ + Si (s) → 2H _Si ^* + 2Cl _Si ^* + Si (b)

Here, '*' means a chemically adsorbed state, and 's' and 'b' in parentheses mean a substrate and a bulk, respectively. The activation energy of the reactor is known to be approximately 3.8 kcal / mole.

Next, as shown in FIG. 2B, the photoresist pattern 8 and the oxide film 5 are removed, and the oxide film pattern 18 in which the SIC 7 region is opened is formed again. In this case, the oxide film pattern 18 may be patterned without removing the oxide film 5, but it is preferable to deposit and pattern the oxide film pattern again (preferably low temperature oxide film) for precise process condition control.

Subsequently, FIG. 2C shows a state after the selective growth of the selective epytaxial growth (Si SEG) layer 9 using the LOCOS oxide film 4 and the oxide film pattern 18 as a mask. At this time, the Si SEG layer 9 may be selectively grown at a low temperature of 700 ^° C. or lower using a growth method of repeating deposition and etching. In the case of growth using SiH ₄ gas, the immersion time is short as 60 to 90 seconds, and when the crystal nuclei are formed on the oxide film 18 and small crystal grains start to exist, they grow rapidly. Therefore, the selectivity between the oxide film 5 and the silicon Si may be increased by maintaining the deposition time shorter than the immersion time and then etching the particles that may be formed on the oxide film 18. Meanwhile, in order to increase the immersion time, deposition may be performed while flowing SiH ₄ and HCl together, followed by etching with only the next HCl, followed by repeated deposition and etching.

On the other hand, although the silicon SEG layer 9 is easily formed at a high temperature of 800 ^° C. or higher, it is an important issue to control defects generated near the oxide sidewalls and facets formed during growth. In addition, SEG technology is important in order to reduce the thermal burden and obtain a good quality epitaxial film at a very low temperature near 600 to 700 ^° C. Therefore, it concentrates mainly on high vacuum and low temperature growth, and as the temperature goes down to low temperature, the partial pressure of oxygen and moisture affect the SEG. For SEG to be possible at 600 ^o C, the partial pressure must be below 30 to 100 ppb. In severe cases, single and polycrystalline transitions can occur even at 50 and 20 ppb of H ₂ O and O ₂ at 750 ^o C.

Basically, in order to obtain high quality epitaxy thin film through SEG method, it is necessary to maintain the entire source gas and carrier gas, the substrate surface and the chamber atmosphere free of oxygen or moisture. In addition, as the material of the mask used for the growth of SEG, oxide film and nitride film are used a lot, and the oxide film also differs little by little depending on the deposition method (for example, wet, dry, low temperature deposition). In addition, the state of the side of the mask layer affects the formation of defects (e.g., twins, stacking faults, and cutting faces {{}}, {111}), so appropriate treatment is required. Done.

Subsequent to the above-described SEG process, Lateral Over Growth (LOG) is continuously performed to allow crystal growth to occur without defects of 0.5 mm or more above the edge of the emitter region on the oxide film 18. At this time, it is important that the nucleation of silicon is not induced on the oxide film 18, and even if it is generated, the vapor pressure of the reaction gas is maintained at 1 mTorr or lower so as to decompose and desorb by the reaction with chlorine (Cl).

Next, as shown in FIG. 2D, the SiGe base epitaxial layer 10 is formed. The SiGe base epi layer 10 is formed of a stacked structure of a Si seed layer, a SiGe epi layer, and an Si cap layer thereon, and in-situ of the SiGe epi layer is grown. situ) two-dimensional doping several times. Two-dimensional doping supplies an Si source and a Ge source to grow an epitaxial layer, stops the supply for a predetermined time, and supplies a doping source (eg, B ₂ H ₆ ).

This is explained in detail. The substrate on which the collector is formed is adjusted to a temperature for base growth, and then directly connected to base epilayer growth. Therefore, it is advantageous to make the base-emitter junction of high quality so that the wafer is not exposed out of the growth chamber when the collector-base junction is formed. In particular, the growth condition of the base is to use a heterojunction structure composed of multiple layers to grow SiGe epi at low temperature to suppress the diffusion of boron (B) and to minimize the amount of oxygen injected into the impurities during epi growth. . In general, the concentration of oxygen atoms injected into the epi can be increased to a level of 10 ¹⁹ cm ^-3 or more visible increase below 700 ^° C. Assuming that the kinetic reaction at the substrate surface of silicon is continuously grown in the region of 600 to 900 ^° C., the main reactors to which SiH ₄ is reacted can be represented by the following schemes (2) and (3).

SiH ₄ + 2Si (s) → 2SiH + Si (b) + H ₂

SiH → Si (s) + 1/2 H ₂

Schemes 2 and 3 are known to control the rate of growth at high and low temperatures, respectively. Meanwhile, like SiH ₄ sources, GeH ₄ exhibits the same reaction process. The activation energy for epi growth is known to be 1.6 eV and 1.0 eV for SiH ₄ and GeH ₄ , respectively. Therefore, when SiGe is grown by injecting GeH ₄ , the growth rate is rapidly increased, and the SiGe epilayer is grown at a growth rate of 10 nm / min or less with a pressure of 10 to 50 Torr and a temperature of 550 to 700 ^° C.

The SiGe epilayer should be uniform in Ge composition within 5%, low in carbon (C) and oxygen (O) at the interface, sharp doping concentration control, high productivity growth process, high thermal stability (Problem of stress relaxation or defect occurrence of thin film near 600 ^o C), low defects (high yield, low cost), and 800 to 1000 ^o C heat treatment should be possible. Low temperature growth prevents interfacial diffusion of SiGe / Si and diffusion of boron (B) by keeping the temperature below 650 ^o C, and prevents defects due to stress relaxation of metastable SiGe layer. However, surface diffusion of Si Insufficient crystallization may result in crystal defects, difficult in-situ cleaning of the natural oxide film, low growth rate, and in-situ doping of high concentrations of n-type and p-type impurities, making it difficult to secure long-term stability and reliability. The problem of low temperature growth can be solved somewhat by high vacuum, which increases the uniformity from the high vacuum to the molecular flow, reduces the gas phase reaction, and controls the epi growth by the surface reaction. High-quality epitaxial growth is possible at low temperature, so the loading effect is small, the concentration of defects or impurities is minimized, and it is advantageous for SEG growth.

When the base grown on silicon is Si _1-x Ge _x , the critical thickness h _c depends on the growth conditions of the epi, and the lower the growth temperature, the critical thickness increases. The theory of the critical thickness is very well established, the general formula of the critical thickness can be represented by the following equation (1).

Where n, a, b are constants, and x is the mole fraction of Ge. The high temperature growth (700 ^~ 800 ^o C) is very consistent with Van der Merwe's theory (n = 1, a = 0.55, b = 0.1), and the experimental result is 1.7793x ^-1.2371 (nm). Follow. When the growth temperature is lowered, the critical thickness starts to increase and follows the theory of energy balance of 'People &Bean'.In low temperature below 550 ^o C, the critical thickness increases by about 10 times and n = 2, a = 1, b = 0.38 Can be obtained from the experimental results.

The mole fraction of Ge in the base is used as a triangle or a square. In the case of a triangle, the critical thickness is increased and the acceleration effect of electrons by the electric field is advantageous. The shape of the rectangle is very thin in the base layer, which is advantageous for increasing the operating frequency. .

On the other hand, it is necessary to grow the epi layer below the critical thickness to control the energy gap to produce the desired hetero device. The energy gap of Si _1-x Ge _x is controlled in each of x <in ^{_{0.85 E g = 1.155-0.43x + 0.0206x 2}} (eV), x> 0.85 as E _g = 2.01-1.27x (eV). However, when stressed Si _1-x Ge _x is grown on the relaxed Si _1-y Ge _y (Si _1-y Ge _y / Si _1-x Ge _x ), if x> y, the balance band is caused by the compressive stress. Most of the offset E _v = (0.74-0.06y) (xy) eV, and when x <0.6, tensile stress is applied and most of offset is generated in the conduction band. E _c = 0.6y (eV). Accordingly, the SiGe base layer subjected to the compressive stress between the relaxed SiGe layers increases the offset of the balance band to form a conductive layer having increased conductivity. At this time, intermixing at the interface is very important. An offset of 70-110 meV is generated in the balance band of the base of the HBT to increase the barrier to holes, thereby increasing the current gain.

As described above, the base epi layer has a structure in which the mole fraction of Ge forms a rectangle or a triangle. At this time, epitaxial single crystals are grown in the active region where silicon is exposed, and polycrystalline crystals are grown on the oxide film 18.

Subsequently, as illustrated in FIG. 2E, the SiGe base epitaxial layer 10 is patterned through a lithography operation to leave only the region to be used as the base. Next, after depositing a low temperature oxide film (not shown) on the substrate again, a region for emitter bonding is formed by repeating dry etching and wet etching, and loading the substrate into an RPCVD apparatus to insert in-situ doped P. After depositing the polysilicon thin film 11 of the type, the polysilicon thin film 11 and the low temperature oxide film are sequentially dry-etched to form an emitter junction and a collector junction. In the case of a collector joint, a contact portion must be secured in advance so as to be connected to the collector plug 6.

Typically, in BJT, the removal of the surface oxide film by hydrogen atmosphere heat treatment is frequently used to form the emitter. However, in HBT, the natural oxide film on the surface cannot be removed by H ₂ reduction at high temperature due to a thermal budget problem in which the SiGe base epi layer 10 must be maintained without being destroyed. Therefore, since it is difficult to remove the native oxide film in-situ, it is difficult to completely remove the trace amount of the natural oxide film remaining on the surface of the substrate. If the natural oxide film is not properly controlled and remains at the interface between the emitter and the base in a few nm thickness, the current gain is abnormally increased and the emitter resistance is increased. Therefore, the problem is solved by appropriately driving-in the impurity of the emitter injected at a high concentration of 10 ²¹ cm ⁻³ or more during the heat treatment process. At the same time, heat-treatment by drive-in annealed the defects of the surface area caused by dry etching of the oxide film to make the emitter junction window, and enters the high concentration emitter junction, thereby preventing leakage current through the depletion layer. Minimize. On the other hand, LPCVD equipment or UHVCVD equipment with high vacuum load-lock uses a method of protecting the surface of silicon by H-Si bonding in HF treatment and surface treatment at low temperature before growth.

Subsequently, BF ₂ is ion-implanted on the entire structure to form an extrinsic base for self-alignment, and an oxide sidewall spacer 12 is formed on the sidewall of the emitter electrode using a low temperature oxide film, followed by SiGe base. The SiGe epi layer (or Si epi layer) 13 is selectively grown on the epi layer 12 and the polysilicon thin film 11. At this time, the SiGe epilayer 13 is grown to a thickness of 40 to 200 nm using a low temperature SEG technique.

This technique of depositing the SiGe epilayer 13 on the outer base plays a very important role in helping to stabilize the formation of subsequent Ti silicide 15 and reducing the resistance of the base, allowing the emitter and outer base to self-align. For the growth, the growth and etching method described above is repeated. The growth temperature is 700 ^o C or less, and the used gas is SiH ₄ + GeH ₄ + HCl (in case of SiGe epitaxial growth), and HCl is used for etching. Use each. The growth rate is above 3 nm / min at temperatures above 650 ^o C and doping is possible up to 10 ²¹ cm ^-3 using PH ₃ and B ₂ H ₆ gases.

Next, as shown in FIG. 2F, Ti / TiN films 14, which are barriers, are deposited on the entire structure to a thickness of 20 to 40 nm, respectively, by sputtering.

Subsequently, as shown in FIG. 2G, in the first silicide-ized rapid heat treatment, a C49 phase is formed and wet-etched with a chemical solution based on NH ₄ OH to react with unreacted Ti on the oxide film 18 and the oxide sidewall spacer 12. 5 ohm / by removing the TiN (14) film and forming Ti silicide 15 on C54 in the second rapid thermal treatment. After forming a junction having the following low sheet resistance, a subsequent interlayer insulating film 19 and metallization 16 process is performed.

At this time, the cross-sectional shape of the SiGe HBT has a structure that is very suitable for implementing BiCMOS by self-aligning the emitter, the base, the collector electrode, the cross-sectional structure of the emitter, the oxide sidewall spacer, and the like.

Meanwhile, when growing the SiGe base epitaxial layer 10 in FIG. 2D, an important point is to form a plurality of two-dimensional doped layers in the base layer by applying atomic layer epitaxial growth control technology.

First, FIG. 3A shows a representative impurity distribution when the impurity distribution when the base epi is grown by three-dimensional doping and the heat treatment for impurity redistribution. FIG. 3A shows a conventional continuous doping for comparison. ) Is shown together.

The advantage of two-dimensional doping is that in the use of a base where the energy band is controlled by using a heterojunction structure between Si and SiGe, the operation speed can be increased by doping the base at a high concentration and reducing the base width. That is, the base width is reduced to increase the gain, and the turn-on voltage is reduced to minimize the high frequency power consumption. And the base is made high, and the modulation rate of a base width is made small and linearity is improved. In this case, the time τ _{ec at} which the electrons injected from the emitter arrive at the collector determines the critical frequency f _t (= 1 / 2πτ _ec ). First, the biggest advantage of SiGe is that it is excellent in high speed operation characteristics. In the formula below, by reducing the width of the base, by reducing the amount of time that electrons move to increase the critical frequency f _t, In addition, the base resistance R _b the base - it is possible to design small collector capacitance C _bc increase the maximum allowable frequency f _max.

That is, the threshold frequency f _t may be represented by Equation 2 below, and the maximum allowable frequency f _max may be represented by Equation 3 below.

Wherein, R _b is the sum of resistance (R _be) and internal resistance (R _bi) of the base of the outer base, R << _be because _bi R accounts for most of the resistance (1~10 ㏀) inside the base. That is, the doped shape in the base layer directly affects the time consumption due to the movement of electrons to determine the critical frequency f _t and the maximum allowable frequency f _max . Accordingly, as shown in FIG. 3A, a technique of doping a highly distributed impurity with a uniform distribution in a very thin base region can greatly improve the performance of the device.

Impurities due to continuous doping show a moderate distribution of slopes around peaks showing maximum values, while in the case of using multiple two-dimensional doping, the distribution of impurity concentration is controlled by subsequent heat treatment, so that it is evenly distributed in a very thin thickness with high concentration. Can be obtained.

On the other hand, Figure 3b is a four-dimensional two-dimensional doping is performed, but shows the distribution of impurities when the retrograde (retrograde) doping, as shown, by adjusting the concentration and position of the two-dimensional doping It is possible to obtain a distribution having a constant slope of a log raid shape.

On the other hand, as another big advantage of SiGe HBT can be obtained a large gain characteristics as shown in Equation 4 compared to silicon BJT.

That is, the current gain of the BJT is determined by the doping concentration of the base and the emitter and the width of the base as shown in Equation 5.

As described above, in the case of SiGe HBT, a gain of 200 to 3000 can be easily obtained according to the band gap difference between the Si emitter and the SiGe base, that is, ΔE _g (eV) = 0.74X _Ge . In particular, the ability to obtain the product of current gain and early voltage (ßxV _A ) of more than 25,000, which is an important feature of analog devices, is a very important advantage for applications as RF devices.

In FIG. 3B, the distribution of impurities doped in the base can be precisely controlled in a very thin region, whereby ΔE _g can be accurately and reproducibly controlled and the gain characteristic of the current can be precisely controlled. Therefore, the technique of accurately controlling the concentration of the doped impurities in the base by using two-dimensional doping greatly contributes to increasing the linearity and reliability of the device. In addition, in FIG. 3B, the concentration of the base may be increased in the emitter bonding direction, or the concentration of the base may be doped at a high concentration and the remaining base may be uniformly maintained. By controlling the characteristics of each junction and the modulation of the base.

4A through 4C illustrate the controllability of the electric field distribution obtained by using a plurality of two-dimensional doping, comparing the respective cases. The SiGe base epitaxial layer consisting of a Si seed layer, a SiGe epitaxial layer, and a Si cap layer is shown. Only the layer 10 and the emitter polycrystalline silicon film 11 thereon are shown.

First, FIG. 4A illustrates a conventional bipolar transistor manufactured by continuous doping, in which a distribution of an electric field is concentrated between an edge of an emitter and a base.

On the other hand, Figure 4b is a form of controlling the distribution of the electric field (refer to Figure 3a) with a number of high concentration two-dimensional doping layer remains, Figure 4c is a suitable time for the four two-dimensional doping layer produced by adjusting the difference in concentration The heat treatment is shown in the case of adjusting to a trapezoidal shape having a constant slope (see Fig. 3b), in both cases it shows that the distribution of the electric field is wide and evenly formed.

Diffusion distance ) And the number and concentration of two-dimensional doping inside the base layer should be determined.In this case, the low temperature low temperature to prevent the generation of defects due to intermixing or stress difference at the SiGe / Si interface It is preferable to perform a heat treatment time.

Impurity distribution increases the linearity of the device pupil by reducing the width of the base modulation to keep the early voltage high. That is, by using a plurality of doping layers formed in two dimensions, it is possible to form a base layer with a very thin thickness with a uniform and sharp distribution or a distribution having a constant inclination. Make it adjustable. In the junction of emitter and base, the electric field is concentrated at the edges, which reduces the collector current dependence, and the collector current can be controlled linearly in the junction area of the emitter-base. Lose. That is, since the collector current characteristic is proportional to the area of the emitter rather than the circumferential length of the emitter, the efficiency of the power gain of the high power device manufactured by the plurality of emitters can be increased, and the power characteristic is the area of the emitter. It is proportional to, increasing the reliability and lifetime of the device by ensuring that collector current and electric fields are not concentrated at the edges.

In particular, in order to linearly control the mole fraction of Ge in the SiGe base epi layer, the SiGe base epi layer may be grown by separating into several small steps. In the case of performing retrograde doping as shown in FIG. Since a two-dimensional coating layer can be inserted in between, it is very useful for the growth of a highly reproducible base epi layer. It is also advantageous in this case to increase the reproducibility of forming the emitter-base junction at a constant concentration and location. The highly doped two-dimensional layer can reduce the energy gap and increase the scattering of impurities, but the effect of the acceleration of the electric field gradient sufficiently offsets the decrease of mobility due to the scattering of impurities is negligible.

When the SiGe HBT is fabricated using this technique, the turn-on voltage is very low, below 0.05 V, the gain is about 100-1500, and the breakdown voltage is 2.5-9.0 V. Gummel characteristics can be obtained IV curves and gummel curves of the base voltage of 0.82 V, the saturation current of 2 mA / mm ² or more, and the uniform current gain characteristics in a wide range of voltage and current. The characteristic of the distribution of gain over the collector current is that the voltage between the emitter and the collector is between 1 V and 2 V, with the collector current ranging from 10 ^-10 A to about 8 mA as a whole over a wide range of collector currents. Ideal characteristics of distribution are possible. The uniform gain can be obtained at such a stable and wide collector current by forming accurate distribution characteristics in a very thin layer of impurity concentration in the heterojunction structure. The fabrication process technology and characteristics of the device described above are optimized for device structure and device parameters, secured reliability of operation characteristics, development of small / high-performance passive device, unit cell function RF cell design for application in the range of 1 to 100 GHz. It can be applied to the development of high frequency integrated circuit technology.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

For example, in the above-described embodiment, a case where a low-temperature oxide film is used as a mask layer for selectively growing a SiGe base epitaxial layer has been described as an example, but the present invention is also applied to a case where it is replaced by another insulating film capable of selective growth. .

In addition, in the above-described embodiment, the case of forming an n-type collector has been described as an example, but the present invention is also applicable to the case where the impurity polarities of the collector, the emitter, and the base are changed.

The above-described manufacturing technology of the SiGe HBT of the present invention interrupts the flow of leakage current while maintaining the existing device structure, and aligns the base and the collector to minimize the resistance component of the external base, and performs epitaxial growth or manufacturing process. It offers advantages such as diffusion prevention at high temperatures. In particular, the base made of several two-dimensional doping layers is used to uniformly control the flow of current injected into the emitter, while precisely adjusting the concentration in a very thin area, thereby reducing the degree of modulation of the base, thereby increasing reliability at high power. It increases the service life at the same time and improves the linear characteristics at high speed operation.

Claims (8)

In the method of manufacturing a heterojunction dipole transistor having a SiGe base epi layer, A method of manufacturing a heterojunction dipole transistor, characterized in that a plurality of two-dimensional doping is performed during the growth of the SiGe base epitaxial layer. Forming a lower collector and a collector Si epitaxial layer on a silicon substrate; Forming a device isolation film on the silicon substrate; A third step of forming a collector plug and a select ion implanted collector (SIC) in an active region of the silicon substrate; A fourth step of forming a mask insulating layer pattern on which the collector (SIC) region in which the selection ion implantation is opened is formed on the entire structure after the third step; A fifth step of selectively growing a Si epitaxial layer using the mask insulating layer pattern, wherein the Si epitaxial layer is also grown on the mask insulating layer pattern on the side surface to a certain degree; Growing a SiGe base epitaxial layer on the entire structure after the fifth step, and forming a plurality of two-dimensional doped layers in the SiGe base epitaxial layer; A seventh step of patterning the SiGe base epi layer to define a base region; and An eighth step of forming an emitter contacting the SiGe base epi layer Heterojunction dipole transistor manufacturing method comprising a. The method of claim 2, The eighth step, A ninth step of forming the emitter using a doped polysilicon film; A tenth step of performing the external base ion implantation; And And an eleventh step of forming a sidewall spacer insulating film on the emitter sidewalls. The method of claim 3, After performing the eleventh step, Selectively growing a SiGe or Si epi layer on the exposed doped polysilicon film and the exposed SiGe base epi layer surface; Forming a high melting point metal barrier layer along the entire structure surface of the twelfth step; Performing a heat treatment to form a silicide layer on surfaces of the doped polysilicon layer and the SiGe base epitaxial layer; And And a fifteenth step of removing the unreacted high melting point metal barrier layer. The method according to claim 2 or 3, The mask insulating film pattern is a low-junction oxide film, characterized in that the bipolar transistor manufacturing method. The method according to claim 2 or 3, The SiGe base epitaxial layer is a heterojunction dipole transistor manufacturing method characterized in that the laminated structure of the Si seed layer / SiGe epi layer / Si cap layer. The method of claim 6, The plurality of two-dimensional doped layer is a heterojunction bipolar transistor manufacturing method characterized in that formed in the SiGe epi layer at a predetermined concentration at a predetermined interval. The method of claim 6, The plurality of two-dimensional doped layer is a heterojunction dipole transistor manufacturing method characterized in that formed in the SiGe epi-layer having a concentration gradient and a predetermined interval.