KR20020011761A - Semiconductor manufacturing apparatus using plasma - Google Patents

Abstract

PURPOSE: An apparatus for manufacturing a semiconductor using plasma is provided to improve reliability by increasing uniformity of an etch rate in a radius direction regarding the entire surface of a wafer, and to increase work efficiency by arbitrarily controlling the etch rate in every positions of the wafer according to a process condition and a plasma type. CONSTITUTION: A plasma source supplies plasma to the wafer(44). The first lower electrode(40) is located in the lower center of the wafer, corresponding to the plasma source. The first bias power is applied to the first lower electrode. The second lower electrode(52) is so positioned in the lower portion of the wafer that the second lower electrode radially surrounds the first lower electrode, corresponding to the plasma source. The second bias power is applied to the second lower electrode.

Description

Semiconductor manufacturing apparatus using plasma

The present invention relates to a semiconductor manufacturing apparatus using plasma, and more particularly, to a structure of a lower electrode to which a bias power is applied at a lower part of a wafer.

The manufacturing process of semiconductor device using plasma can be classified into three types: dry etching process, chemical vapor deposition (CVD) process and sputtering film coating process. It is required to improve the uniformity of deposition and etching, and for this purpose, it is important to control the ions in the plasma to be uniformly incident on the substrate to be processed.

However, as chip size increases due to high integration and capacity of semiconductor devices, the size of the wafer also increases, and as a result, plasma uniformity, wafer uniformity, and loading effect in the film forming or etching process using plasma. Is becoming more and more important.

FIG. 1 is a view schematically showing an etching apparatus of a semiconductor device using a conventional plasma, and FIG. 2 is a plan view of the lower electrode 10 of FIG. 1 and 2, a plasma region 16 is formed on a wafer 14, a substrate to be etched, and an electrostatic chuck for loading and fixing a wafer below the wafer 14 is formed. As the Electro Static Chuck (ESC), the lower electrode 10 is formed in one body. A direct current (DC) power source 18 is connected to the lower electrode 10 to apply a DC voltage to the lower electrode 10 to fix the wafer 14 on the lower electrode 10 by electrostatic adsorption. In addition, a high frequency RF power supply 20 is connected to the lower electrode 10 via a capacitor C1 to bias the plasma. On the other hand, a shadow ring for preventing the plasma formed on the wafer 14 from flowing out of the wafer 14 by a bias power or an exhaust pump (not shown) provided below the outer electrode 10. 12) is installed.

However, when the etching process is performed using the etching apparatus as shown in FIG. 1, it is very difficult to apply the RF power applied to the lower electrode 10 to each part in the radial direction of the lower electrode 10. In particular, as the wafer 14 is large-cured, the lower electrode 10 is also large-cured, resulting in a difference in RF power at the center portion and the edge portion thereof. As a result, the etch rate of the object on the wafer 14 is etched. The rate varies dramatically in the radial direction.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art, and to provide a semiconductor manufacturing apparatus using a plasma which can improve the uniformity of the deposition rate or etching rate on the entire surface of the wafer on which the process is to be performed. To provide.

Another object of the present invention is to provide a semiconductor manufacturing apparatus using a plasma capable of arbitrarily controlling the deposition rate or etching rate for each position of a wafer to be processed.

1 is a schematic diagram of an etching apparatus of a semiconductor device using a conventional plasma.

FIG. 2 is a plan view of the lower electrode of FIG. 1.

3 is a schematic diagram of an etching apparatus of a semiconductor device using plasma according to an embodiment of the present invention.

4 is a plan view of the lower electrode of FIG. 3.

※ Description of the main parts of the drawings

40; A first lower electrode 42; Shadow ring

44; Wafer 46; Plasma area

48; DC power supply 50; RF power

52; Second lower electrode 54; Transformer

The semiconductor manufacturing apparatus using the plasma according to the present invention for achieving the objects of the present invention, the plasma source for providing a plasma on the wafer to be performed, the plasma source is located in the lower center of the wafer corresponding to the first, And a first lower electrode to which the bias power is applied and a first lower electrode to radially surround the lower side of the wafer in correspondence to the plasma source, and at least one second lower electrode to which the second bias power is applied.

Preferably, the first lower electrode is formed in a disk shape having a circular protrusion formed at the center thereof, and extends outward from the portion where the wafer is located by a predetermined length, and the second lower electrode is disposed at the lower side of the wafer. It is arranged to surround the protrusion. In addition, the first and second lower electrodes may be connected to the same high frequency power source, and a divided bias power may be applied to the first and second lower electrodes through a transformer in the middle.

According to the present invention, the lower electrode corresponding to the wafer is divided radially, and the radial force from the center of the wafer is also divided since the bias power applied to each divided lower electrode can be divided and controlled independently or under constant correlation with each other. Uniformity of the deposition rate or the etching rate can be ensured.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

The embodiments described below are not intended to limit the present invention to the embodiments, but to illustrate the present invention by way of example, various modifications may be made within the technical recognition range of those skilled in the art. In particular, although the present embodiment relates to an etching apparatus, the present invention is also applied to a film forming apparatus using plasma, and various forms may be applied as the plasma source.

3 is a view illustrating an etching apparatus of a semiconductor device using plasma according to an embodiment of the present invention, and FIG. 4 is a plan view of the lower electrodes 40 and 52 of FIG. 3. 3 and 4, a plasma region 46 is formed on the wafer 44, which is a substrate to be etched.

The plasma region 46 is generated by using an RF generator as an energy source in various types of plasma sources (not shown) according to process conditions. As such a plasma source and an RF generator applied thereto, a planar method for generating a plasma by applying RF power to an anode, and a RIE (Reactive) for generating a plasma by applying RF power to a cathode where a wafer is located. Ion Etching) method, MERIE (Magnetically Enhanced RIE) method to increase the density of plasma by installing magnet on the side of cathode electrode, CDE (Chemical Downstream Etching) method to supply plasma by supplying plasma to microwave power in advance. ECR (Electron Cyclotron Resonance) method to induce plasma by electron cyclone movement, Helicon method to form high density plasma by adding wave energy to electrons by coil, and in the plasma by current flowing in coil TCP (Transformer) to form a high density plasma by the induced inductance component Coupled Plasma), ICP (Inductivity Coupled Plasma), which accelerates electrons by inducing an electric field in the plasma by a magnetic field by a coil, and the like, as long as bias power is applied to the lower electrode where the wafer is located. Applicable

On the other hand, the first lower electrode 40 is formed under the wafer 44 as an electrostatic chuck (ESC) for loading and fixing the wafer. The first lower electrode 40 has a disk shape having a circular protrusion formed at the center thereof, and has an extended portion extending radially outwardly from the wafer 44. However, the length of the extension portion of the first lower electrode 40 may be perpendicular to the sidewall of the wafer 44 and may be reduced to less than that.

The second lower electrode 52 is electrically insulated from the first lower electrode 40 so as to surround the protrusion in the radial direction around the protrusion of the first lower electrode 40. Preferably, the first lower electrode 40 and the second lower electrode 52 are made of the same conductive material, and the heights of the upper surfaces thereof are maintained at the same level. The sidewall of the second lower electrode 52 may be positioned at a position perpendicular to the sidewall of the wafer 44. However, in some cases, the sidewall of the second lower electrode 52 may be projected outwardly or may be reduced inwardly from the radius of the wafer 44. In FIG. 3, the second lower electrode 52 is illustrated as one, but a plurality of radially divided portions may be used along the radial direction. The first lower electrode 40 and the second lower electrode 52 may also be further provided with cooling means to control the temperature of the wafer 44.

A shadow ring 42 is provided outside the second lower electrode 52, and the exhaust ring is provided with an exhaust pump mainly located at a lower end of a process chamber in which a deposition process or an etching process is performed by a bias power. This is to prevent the plasma from flowing out of the wafer 44 by the line.

On the other hand, a direct current (DC) power source 48 is connected to the first lower electrode 40 and the second lower electrode 52 to apply a direct current voltage to the lower electrodes 40 and 52 by electrostatic adsorption. The wafer 44 is fixed on the lower electrodes 40 and 52.

In addition, the first and second lower electrodes 40 and 52 have a single high-frequency RF power supply 50 via capacitors C1 and C2, respectively, to provide a variable power to each lower electrode in the middle of the transformer ( 54) to bias the plasma. The RF power source 50 may be provided with power having various frequencies according to the process target or the type of plasma source, and the first lower electrode 40 and the second lower electrode 52 respectively divided by the transformer 54. ) May be supplied with the same power or divided power at a constant rate. Each of the first lower electrode 40 and the second lower electrode 52 may be provided with an RF power source that is independently controlled and has an independent frequency. Power can be used.

Referring to the etching process of the etching apparatus of FIG. 3, when the RF power is divided and applied to the first and second lower electrodes 40 and 52 at a constant rate from the RF power supply 50, such alternating voltage is applied. As a result, the combined current of the current by ions and the current by electrons flows from the plasma to the wafer 44. At this time, since the current by the electrons that are more mobile than the ions is more likely to flow than the current by the ions, in order to equalize the total amount of positive charge flowing in the wafer 44 during one cycle of the RF power, that is, the current by the electrons. Negative self-bias voltage is generated on the surface of the wafer to reduce the current or increase the current caused by the ions, thereby efficiently injecting ions in the plasma into the wafer and performing an etching process with high anisotropy. .

In this case, the split ratio of the RF power divided into the first lower electrode 40 and the second lower electrode 52 is the ratio of the surface area occupied by the first and second lower electrodes 40 and 52 or the wafer ( This is determined in consideration of the plasma density of each position in the plasma region 46 formed on 44. The plasma density is generally increased toward the center of the wafer 44 but is not necessarily the case, and may be lowered toward the center depending on the source of the plasma. Meanwhile, the surface area ratios of the first and second lower electrodes 40 and 52 positioned below the wafer 44 are determined in consideration of the diameter of the wafer, the number of the lower electrodes, and the like. For example, the surface area ratio of the second lower electrode 52 may be maintained in a range of 20 to 30%, and RF power for each lower electrode may be divided based on this.

Although the embodiments have been described in detail as described above, the present invention is not limited thereto, and the present invention can be applied to various types of plasma sources as long as the bias power is applied to the lower electrode where the wafer is located. The ratio of the frequency or power of the RF power source to the lower electrode can be variously selected according to the process, and the dimensions or materials of the lower electrodes can be variously selected. In addition, the present invention can be widely applied to various types of physical or chemical film forming processes or etching processes using plasma.

According to the present invention, the uniformity of the deposition rate or etching rate can be improved in the radial direction with respect to the entire surface of the wafer on which the process is to be performed, thereby realizing a reliable semiconductor device, and forming the deposition rate or etching for each wafer position. The rate can be arbitrarily controlled according to the process conditions or the type of plasma, thereby improving workability.

Claims (3)

A plasma source for providing a plasma on the wafer on which the process is to be performed; A first lower electrode positioned at a lower center of the wafer to correspond to the plasma source and to which a first bias power is applied; And A semiconductor using a plasma, characterized in that it is positioned to radially surround the first lower electrode on the lower side of the wafer corresponding to the plasma source, and at least one second lower electrode to which a second bias power is applied. Manufacturing equipment. The method of claim 1, wherein the first lower electrode is formed in the shape of a disk with a circular protrusion formed in the center thereof, extends outward from the portion where the wafer is located by a predetermined length, the second lower electrode of the wafer The semiconductor manufacturing apparatus using the plasma is disposed on the lower side to surround the protruding portion, the shadow ring is further provided on the first lower electrode to the outside of the second lower electrode. The plasma display device of claim 1, wherein the first and second lower electrodes are connected to the same high frequency power source, and a divided bias power is applied to the first and second lower electrodes through a transformer in the middle. Semiconductor manufacturing apparatus using the.