KR20020002788A - Method for manufacturing a semiconductor chip package - Google Patents

Method for manufacturing a semiconductor chip package Download PDF

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Publication number
KR20020002788A
KR20020002788A KR1020000037085A KR20000037085A KR20020002788A KR 20020002788 A KR20020002788 A KR 20020002788A KR 1020000037085 A KR1020000037085 A KR 1020000037085A KR 20000037085 A KR20000037085 A KR 20000037085A KR 20020002788 A KR20020002788 A KR 20020002788A
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South Korea
Prior art keywords
semiconductor chip
printed circuit
circuit board
package
chip
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KR1020000037085A
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Korean (ko)
Inventor
박희진
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윤종용
삼성전자 주식회사
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Priority to KR1020000037085A priority Critical patent/KR20020002788A/en
Publication of KR20020002788A publication Critical patent/KR20020002788A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

PURPOSE: A method for manufacturing a semiconductor chip package such as a chip-on-board package used for an IC card is provided to reduce manufacturing cost and mounting area by reducing the size of the IC card. CONSTITUTION: A printed circuit board(130), preferably a reel type, is prepared. In the printed circuit board(130), a plurality of chip mounting parts are formed. A semiconductor chip(121) is mounted on each mounting part and then electrically connected to the printed circuit board(130) via a bonding wire(123). The chips(121) mounted on the printed circuit board(130) are entirely molded to form a unified molding part(125). The molding part(125) is then cut by using a rotating drill in H-beam shape, so that the semiconductor chip packages(120) are individually separated. During the separation of the packages(120), outer surfaces of the packages(120) are smoothed with the rotating drill.

Description

반도체 칩 패키지 제조 방법{Method for manufacturing a semiconductor chip package}Method for manufacturing a semiconductor chip package

본 발명은 반도체 칩 패키지 제조 방법에 관한 것으로서, 보다 구체적으로는 아이씨 카드로 사용되는 반도체 칩 패키지의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor chip package, and more particularly, to a method for manufacturing a semiconductor chip package to be used as an IC card.

전자 장치의 고밀도화, 소형화의 추세에 따라 리드 프레임을 사용하여 패키지를 구성한 후 인쇄회로기판에 실장하는 과정을 생략하여, 반도체 칩을 직접 인쇄회로기판 상에 실장하는 새로운 패키징 방법이 주목받고 있다. 이처럼 반도체 칩을 직접 인쇄회로기판 상에 실장한 패키지를 칩 온 보드(Chip On Board; COB) 패키지라 한다. 휴대용 정보단말기, 하드 디스크 대용, 디지털 스틸 카메라 및 게임기 등의 문자, 음성, 정지화상 등의 기록을 위한 메모리 카드(Memory Card)는 수개의 메모리 칩(Memory Chip)을 하나의 카드로 패키징함으로써 대용량의 기억 매체로 자리 잡고 있다.In accordance with the trend of higher density and miniaturization of electronic devices, a new packaging method of directly mounting a semiconductor chip on a printed circuit board by omitting a process of mounting a package using a lead frame and then mounting the printed circuit board has been attracting attention. Such a package in which a semiconductor chip is directly mounted on a printed circuit board is called a chip on board (COB) package. A memory card for recording text, voice, still images, etc., such as a portable information terminal, a hard disk substitute, a digital still camera, a game machine, etc., has a large capacity by packaging several memory chips into a single card. It is a storage medium.

메모리 카드에는 미니어쳐 카드(Miniature Card), 컴팩트 플래쉬(CompactFlash), 스마트 미디어(SmartMedia) 등이 있는데, 미니어쳐 카드와컴팩트 플래쉬는 콘트롤러(Controller) 내장 등으로 기억 매체 이외의 간접비(Overhead cost) 및 부피가 큰 단점이 있다. 하지만, 디지털 신호의 저장 장치로 사용되는 스마트 미디어 또는 SSFDC(Solid State Floppy Disc Card)와 같이 플래쉬 메모리 칩(Flash Memory Chip)이 내장된 칩 온 보드(COB) 패키지를 이용한 아이씨 카드(IC Card)는 기존의 메모리 카드에 비하여 크기가 작고, 세대간에 동일한 핀 수를 갖기 때문에 확장성이 높으며, 휴대가 간편하다는 장점이 있다. 그리고, 스마트 미디어는 디지털 스틸 카메라의 정보 저장용으로 착탈(Embedded or Removal) 형태로 사용되고, 디지털 게임기 및 휴대용 정보 단말기 등에 이용되는 문자, 음성, 정지화상 등의 기록을 위한 새로운 소형 카드이다.Memory cards include Miniature Cards, CompactFlash, and SmartMedia. Miniature Cards and CompactFlash are built-in controllers, which allow you to save overhead costs and volume. There is a big disadvantage. However, IC cards using chip-on-board (COB) packages with built-in flash memory chips, such as smart media or solid state floppy disc cards (SSFDC), are used as digital signal storage devices. Compared to the conventional memory card, it is small in size, has the same pin count among generations, has high scalability, and is easy to carry. In addition, smart media is a new compact card for recording texts, voices, still images, etc. used in an embedded or removed form for storing information of a digital still camera and used in digital game machines and portable information terminals.

또한 종래의 자기 테이프(Magnetic Tape)를 이용한 아이디 카드(ID Card)나 디스켓에 비하여 용량이 크고, 저장 및 보관이 용이하므로 그 활용 폭이 넓어질 것으로 전망된다. 따라서, 디지털 스틸 카메라나 기타 사용 설비들과 종전의 플로피 디스크(Floppy Disc)와 같은 개념으로 탈착(脫着)이 가능해야 하므로 외부에 전기적 접촉이 가능하도록 외부 접속 단자(Contact Pad)가 있어야 하고, 사용 업체 또는 사용 설비간의 규격화된 모양의 것이라야 한다. 즉, 해당 반도체 칩을 포함하는 칩 온 보드(COB) 패키지와, 칩 온 보드(COB) 패키지를 실장할 수 있는 수납 공간이 형성된 규격화된 베이스 카드 또는 카드 몸체의 결합으로 하나의 아이씨 카드가 완성되는 것이다.In addition, it is expected that its capacity will be wider than that of ID cards or diskettes using magnetic tapes, and its storage and storage will be easy. Therefore, it should be possible to attach and detach with a concept such as a digital still camera or other using equipment and a conventional floppy disk, so there must be an external contact terminal to allow electrical contact with the outside. It shall be of a standardized form between the entrepreneurs or the equipment used. That is, one IC card is completed by combining a chip on board (COB) package including the semiconductor chip and a standardized base card or card body having a storage space for mounting the chip on board (COB) package. will be.

여기서, 베이스 카드는 칩 온 보드(COB) 패키지만으로는 디지털 스틸 카메라와 같은 외부 전자 장치와 직접 전기적으로 연결시키거나 취급상 용이하지 않기 때문에, 칩 온 보드(COB) 패키지의 취급을 용이하게 하며, 칩 온 보드(COB) 패키지와 외부 전자 장치와의 전기적 연결을 보조하기 위해서 사용된다.Here, the base card facilitates the handling of the chip on board (COB) package, since the chip on board (COB) package alone is not directly connected or electrically handled with an external electronic device such as a digital still camera. It is used to assist the electrical connection between the on-board (COB) package and external electronics.

도 1은 종래 기술에 따른 아이씨 카드에 칩 온 보드 패키지가 조립되는 모습을 나타내는 분해 사시도, 도 2는 종래 기술에 따른 아이씨 카드의 일부를 나타내는 단면도, 도 3은 도 1에 도시된 칩 온 보드 패키지의 평면도, 도 4는 도 1에 도시된 칩 온 보드 패키지의 배면도, 도 5는 종래 기술에 따른 릴 인쇄회로기판을 나타내는 평면도이다.1 is an exploded perspective view showing a chip on board package assembled to an IC card according to the prior art, FIG. 2 is a cross-sectional view showing a part of the IC card according to the prior art, and FIG. 3 is a chip on board package shown in FIG. 4 is a rear view of the chip on board package shown in FIG. 1, and FIG. 5 is a plan view illustrating a reel printed circuit board according to the related art.

도 1 내지 5를 참조하면, 아이씨 카드(10)는 카드 몸체(11)에 칩 온 보드 패키지(20)가 조립되는 구조를 갖는다. 따라서, 카드 몸체(11)에는 칩 온 보드 패키지(20)가 접착되는 접착부(12)와 칩 온 보드 패키지(20)의 성형부(24)가 삽입되는 수납부(13; cavity)가 형성된다. 칩 온 보드 패키지(20)는 인쇄회로기판(30)을 사용하며, 반도체 칩(21)이 접착제(22)에 의하여 인쇄회로기판(30)에 직접 접착된다. 반도체 칩(21)과 인쇄회로기판(30)에 형성된 본딩 패드(31; bonding pad)들은 본딩 와이어(23; bonding wire)에 의하여 전기적으로 연결되며 성형수지(24)로 밀봉된다.1 to 5, the IC card 10 has a structure in which the chip on board package 20 is assembled to the card body 11. Accordingly, the card body 11 is formed with an adhesive part 12 to which the chip on board package 20 is attached and a cavity 13 into which the molding part 24 of the chip on board package 20 is inserted. The chip on board package 20 uses a printed circuit board 30, and the semiconductor chip 21 is directly bonded to the printed circuit board 30 by the adhesive 22. Bonding pads 31 formed on the semiconductor chip 21 and the printed circuit board 30 are electrically connected by bonding wires 23 and sealed with a molding resin 24.

인쇄회로기판(30)의 뒷면, 즉 아이씨 카드(10)의 외부로 노출되는 면에는 외부접속단자(33; contact pad)들이 형성되며, 관통구멍(32)을 통하여 앞면의 본딩 패드(31)들과 연결된다. 외부접속단자(33)들은 절연영역(34)에 의하여 서로 전기적으로 분리된다. 도 3의 도면 부호 35번은 댐(dam)으로서, 성형부(24)의 형성에 도움을 준다.External contact terminals 33 (contact pads) are formed on the back surface of the printed circuit board 30, that is, the surface exposed to the outside of the IC card 10, and the bonding pads 31 on the front surface thereof are formed through the through holes 32. Connected with The external connection terminals 33 are electrically separated from each other by the insulating region 34. Reference numeral 35 in FIG. 3 denotes a dam, which helps to form the forming part 24.

칩 온 보드 패키지(20)는 인쇄회로기판(30)의 구조 및 밀봉 방법에 따라 몇 가지 유형으로 구분된다. 그 중에서 특히 릴(reel) 타입의 인쇄회로기판을 사용하는 칩 온 보드 패키지는 제조 원가가 저렴하고 조립 생산성이 높아 대량 생산에 유리하다. 칩 온 보드 패키지의 제조에 사용되는 종래의 릴 인쇄회로기판이 도 5에 도시되어 있다.The chip on board package 20 is classified into several types according to the structure of the printed circuit board 30 and the sealing method. Among them, a chip-on-board package using a reel type printed circuit board is particularly advantageous for mass production due to low manufacturing cost and high assembly productivity. A conventional reel printed circuit board used in the manufacture of a chip on board package is shown in FIG.

도 5에 도시된 바와 같이, 릴 인쇄회로기판(40; reel PCB)은 다수개의 칩 온 보드 패키지들이 동시에 연속적으로 제조될 수 있도록 필름 형태로 되어 있다. 즉, 릴 인쇄회로기판(40)에는 앞서 인쇄회로기판에 대한 설명에서 언급했던 구성 요소들이 연속적으로 형성된다. 도면 부호 37은 릴 인쇄회로기판(40)의 뒷면에 형성되는 외부접속단자의 윤곽을 도시한 것이며, 도 3에 나타난 바와 같이 개별 칩 온 보드 패키지(20)의 외곽선 이기도 하다.As shown in FIG. 5, the reel PCB 40 is in the form of a film so that a plurality of chip on board packages can be continuously manufactured simultaneously. That is, in the reel printed circuit board 40, the components mentioned in the description of the printed circuit board are continuously formed. Reference numeral 37 denotes an outline of an external connection terminal formed on the back of the reel printed circuit board 40, and also as an outline of the individual chip-on-board package 20 as shown in FIG.

릴 인쇄회로기판(40)의 앞면에는 또한 댐(35)이 형성된다. 앞서 칩 온 보드 패키지는 밀봉 방법에 따라서도 구분된다고 언급한 바 있는데, 통상적으로 릴 인쇄회로기판(40)을 사용하는 칩 온 보드 패키지는 액상의 성형수지를 도포하는 코팅(coating) 방법을 적용한다. 이 때 댐(35)은 액상 성형수지의 흐름을 차단하여 성형부(24)가 원하는 영역에만 형성될 수 있도록 해 준다. 또 다른 밀봉 방법인 몰딩(molding) 방법을 적용할 경우에도 댐(35)은 사용될 수 있다. 한편, 릴 인쇄회로기판(40)에는 스프라켓 홀(41; sprocket hole), 방향지시 홀(42), 불량표기 홀(43a, 43b) 등이 형성된다.A dam 35 is also formed on the front side of the reel printed circuit board 40. As mentioned above, the chip-on-board package is also classified according to the sealing method. In general, the chip-on-board package using the reel printed circuit board 40 applies a coating method for applying a liquid molding resin. . At this time, the dam 35 blocks the flow of the liquid molding resin so that the molding part 24 can be formed only in a desired area. The dam 35 can also be used when applying a molding method, which is another sealing method. On the other hand, the reel printed circuit board 40 is formed with a sprocket hole 41 (sprocket hole), the direction indicating hole 42, the defective notation holes (43a, 43b) and the like.

이와 같이, 종래의 아이씨 카드(10)는 칩 온 보드(COB) 패키지(20)의 인쇄회로기판(30)이 카드 몸체(11)에 접착되어야 하므로, 성형부(24) 주위에 인쇄회로기판(30)의 여분 면적이 필요하다. 즉, 성형부(24) 주위에 인쇄회로기판(30)이 돌출되어 접착부(12)와 접착하게 된다. 따라서, 칩 온 보드(COB) 패키지(20)의 크기가 커지므로 릴 인쇄회로기판(40)으로부터 제조되는 칩 온 보드(COB) 패키지(20)의 수율이 작아서 제조 비용이 증가한다.As such, in the conventional IC card 10, since the printed circuit board 30 of the chip on board (COB) package 20 is to be bonded to the card body 11, the printed circuit board around the molding unit 24 ( 30) extra area is required. That is, the printed circuit board 30 protrudes around the molding part 24 to bond with the adhesive part 12. Therefore, since the size of the chip on board (COB) package 20 is increased, the yield of the chip on board (COB) package 20 manufactured from the reel printed circuit board 40 is small, thereby increasing the manufacturing cost.

또한, 칩 온 보드 패키지(20)가 카드 몸체(11)의 수납부(13)에 삽입되어 접착되는 과정에서 칩 온 보드 패키지(20)의 위치에 오차가 발생할 수 있다. 이러한 오차가 오차 한계를 초과하면 아이씨 카드(10)와 외부 장치의 연결에 불량이 발생한다. 이러한 오차 한계를 고려하여야 하므로 외부 접속단자(33)의 선폭을 일정 한도 이하로 줄일 수 없다. 더구나, 카드 몸체(11)를 사용하면 아이씨 카드(10)의 크기가 커지게 되므로 전자 장치의 고밀도화, 소형화 추세에 역행하게 된다.In addition, an error may occur in the position of the chip on board package 20 when the chip on board package 20 is inserted into and adhered to the housing 13 of the card body 11. If this error exceeds the error limit, a defect occurs in the connection between the IC card 10 and the external device. Since the error limit must be considered, the line width of the external connection terminal 33 cannot be reduced below a certain limit. In addition, when the card body 11 is used, the size of the IC card 10 is increased, thereby countering the trend of higher density and miniaturization of the electronic device.

따라서, 본 발명의 목적은 아이씨 카드의 크기를 줄여서 제조 비용과 실장 면적을 감소시키는 데 있다.Therefore, an object of the present invention is to reduce the size of the IC card to reduce the manufacturing cost and mounting area.

도 1은 종래 기술에 따른 아이씨 카드에 칩 온 보드 패키지가 조립되는 모습을 나타내는 분해 사시도,1 is an exploded perspective view illustrating a chip on board package assembled to an IC card according to the related art;

도 2는 종래 기술에 따른 아이씨 카드의 일부를 나타내는 단면도,2 is a cross-sectional view showing a portion of an IC card according to the prior art;

도 3은 도 1에 도시된 칩 온 보드 패키지의 평면도,3 is a plan view of the chip on board package shown in FIG.

도 4는 도 1에 도시된 칩 온 보드 패키지의 배면도,4 is a rear view of the chip on board package shown in FIG.

도 5는 종래 기술에 따른 릴 인쇄회로기판을 나타내는 평면도,5 is a plan view showing a reel printed circuit board according to the prior art;

도 6은 본 발명의 실시예에 따른 반도체 칩 패키지를 제조하는 공정을 나타내는 순서도,6 is a flowchart illustrating a process of manufacturing a semiconductor chip package according to an embodiment of the present invention;

도 7은 본 발명의 실시예에 따른 인쇄회로기판을 나타내는 평면도,7 is a plan view showing a printed circuit board according to an embodiment of the present invention;

도 8은 본 발명의 실시예에 따른 인쇄회로기판에 성형부를 형성한 모습을 나타내는 평면도,8 is a plan view showing a state in which a molded part is formed on a printed circuit board according to an exemplary embodiment of the present invention;

도 9는 인쇄회로기판에 형성된 성형부를 분리하는 모습을 나타내는 단면도,9 is a cross-sectional view showing a state in which a molded part formed on a printed circuit board is separated;

도 10은 본 발명의 실시예에 따른 반도체 칩 패키지를 나타내는 단면도이다.10 is a cross-sectional view illustrating a semiconductor chip package according to an embodiment of the present invention.

<도면의 주요 부호에 대한 설명><Description of Major Symbols in Drawing>

100, 130; 인쇄회로기판 102; 본체100, 130; A printed circuit board 102; main body

120; 반도체 칩 패키지 121; 반도체 칩120; Semiconductor chip package 121; Semiconductor chip

122; 접착제 123; 본딩 와이어122; Adhesive 123; Bonding wire

125; 패키지 몸체 131; 본딩 패드125; Package body 131; Bonding pads

132; 관통 구멍 133; 외부접속단자132; Through hole 133; External connection terminal

137; 칩 탑재부 140; 회전 드릴137; Chip mounting unit 140; Rotary drill

이러한 목적을 달성하기 위해서 본 발명의 실시예는 (A) 복수 개의 칩 탑재부가 형성된 인쇄회로기판을 준비하는 단계; (B) 칩 탑재부에 반도체 칩을 탑재하고, 반도체 칩과 인쇄회로기판을 전기적으로 연결하는 단계; (C) 복수 개의 반도체 칩을 일괄 성형하여 성형부를 형성하는 단계; 및 (D) 성형부를 개별 반도체 칩 패키지로 분리하는 단계를 포함하는 반도체 칩 패키지 제조 방법에 있어서, (D) 단계는 성형부를 반도체 칩 패키지로 분리하는 동시에 반도체 칩 패키지의 외관을 가공하는 공정을 진행하는 것을 특징으로 하는 반도체 칩 패키지 제조 방법을 제공한다.In order to achieve this object, an embodiment of the present invention comprises the steps of (A) preparing a printed circuit board having a plurality of chip mounting portion; (B) mounting a semiconductor chip on the chip mounting portion and electrically connecting the semiconductor chip and the printed circuit board; (C) forming a molded part by collectively molding a plurality of semiconductor chips; And (D) separating the molded parts into individual semiconductor chip packages, wherein step (D) separates the molded parts into semiconductor chip packages and simultaneously processes the appearance of the semiconductor chip packages. A semiconductor chip package manufacturing method is provided.

이하, 첨부 도면을 참조하여 본 발명의 실시예를 보다 상세히 설명하고자 한다. 도면 전반에 걸쳐서 동일한 도면 부호는 동일한 구성 요소를 나타낸다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout.

도 6은 본 발명의 실시예에 따른 반도체 칩 패키지를 제조하는 공정을 나타내는 순서도이다.6 is a flowchart illustrating a process of manufacturing a semiconductor chip package according to an embodiment of the present invention.

도 6을 참조하면, 반도체 칩 패키지를 제조하는 공정(50)을 진행하기 위해서 먼저 인쇄회로기판을 준비한다(52). 인쇄회로기판으로는 일반적으로 릴 인쇄회로기판을 사용한다. 인쇄회로기판에는 반도체 칩이 탑재될 칩 탑재부와 회로가 형성되어 있다. 칩 탑재부에 반도체 칩을 탑재하고, 반도체 칩과 인쇄회로기판의 회로를 전기적으로 연결한다(54). 여러 개의 반도체 칩과 이들의 전기적 연결 부분을 포함하도록 일괄 성형하여 성형부를 형성한다(56). 각각의 반도체 칩에 대해 성형부를 분리하여 개별 반도체 칩 패키지를 완성한다(58). 이때, 성형부를 분리하면서 반도체 칩 패키지의 외관을 가공하는 공정을 동시에 진행하여, 분리된 반도체 칩 패키지에 대한 추가적인 공정 없이 외관을 가공할 수 있다.Referring to FIG. 6, in order to proceed with the process 50 of manufacturing a semiconductor chip package, a printed circuit board is first prepared (52). As a printed circuit board, a reel printed circuit board is generally used. The printed circuit board is provided with a chip mounting portion and a circuit on which a semiconductor chip is to be mounted. The semiconductor chip is mounted on the chip mounting part, and the semiconductor chip and the circuit of the printed circuit board are electrically connected (54). The molding part is formed by collectively molding a plurality of semiconductor chips and electrical connection parts thereof (56). The molding is separated for each semiconductor chip to complete an individual semiconductor chip package (58). At this time, the process of processing the external appearance of the semiconductor chip package while separating the molding portion can be carried out at the same time, the external processing can be processed without additional process for the separated semiconductor chip package.

도 7은 본 발명의 실시예에 따른 인쇄회로기판을 나타내는 평면도이다.7 is a plan view illustrating a printed circuit board according to an exemplary embodiment of the present invention.

도 7을 참조하면, 인쇄회로기판은 도 5에 도시된 종래의 인쇄회로기판과 동일한 구조로 이루어진다. 자세히 설명하면 다음과 같다.Referring to FIG. 7, the printed circuit board has the same structure as the conventional printed circuit board shown in FIG. 5. The detailed description is as follows.

인쇄회로기판(100)에서 다수개의 반도체 칩 패키지, 즉 칩 온 보드 패키지는동시에 연속적으로 제조될 수 있는데, 인쇄회로기판(100)은 필름 형태로 되어 있는 것이 바람직하다. 인쇄회로기판(100)의 본체(102)에는 반도체 칩이 탑재되는 칩 탑재부(137)가 연속적으로 격자 형태로 배열된다. 칩 탑재부(137)에는 회로가 형성된다. 이러한 회로와 반도체 칩(121)은 본딩 와이어(123)에 의해 연결되는데, 본딩 와이어(123)의 한쪽 끝은 반도체 칩(121)과 연결되고 반대쪽 끝은 본딩 패드(131)와 연결된다. 본딩 패드(131)는 인쇄회로기판(100) 뒷면의 외부 접속단자(도 4의 133)와 연결된다.In the printed circuit board 100, a plurality of semiconductor chip packages, that is, a chip on board package, may be continuously manufactured at the same time, and the printed circuit board 100 is preferably in a film form. In the main body 102 of the printed circuit board 100, chip mounting units 137 on which semiconductor chips are mounted are continuously arranged in a lattice form. In the chip mounting unit 137, a circuit is formed. The circuit and the semiconductor chip 121 are connected by a bonding wire 123. One end of the bonding wire 123 is connected to the semiconductor chip 121 and the other end thereof is connected to the bonding pad 131. The bonding pad 131 is connected to the external connection terminal 133 of FIG. 4 on the back side of the printed circuit board 100.

본 발명에서는 성형부가 일괄 성형되므로 도 5에 도시된 인쇄회로기판과 달리 댐이 형성될 필요가 없다. 인쇄회로기판(100)에는 스프라켓 홀(141; sprocket hole), 방향지시 홀(도시되지 않음), 불량표기 홀(도시되지 않음) 등이 형성된다. 한편, 칩 탑재부(137)의 크기와 간격(a)은 종래의 릴 인쇄회로기판(도 5 참조)과 비교해서 더 작게 형성할 수 있다. 즉, 도 1을 참조하면 종래의 아이씨 카드에서는 칩 온 보드(COB) 패키지의 인쇄회로기판이 카드 몸체에 접착되어야 하므로, 성형부 주위에 인쇄회로기판의 여분 면적이 필요하다.In the present invention, since the molding part is molded in a batch, a dam does not need to be formed unlike the printed circuit board illustrated in FIG. 5. The sprocket hole 141, a spherical hole (not shown), a defective notation hole (not shown) is formed in the printed circuit board 100. On the other hand, the size and spacing a of the chip mounting portion 137 can be made smaller than that of the conventional reel printed circuit board (see FIG. 5). That is, in the conventional IC card, since the printed circuit board of the chip on board (COB) package should be bonded to the card body, an extra area of the printed circuit board is required around the molding part.

그러나, 본 발명의 인쇄회로기판(100)을 사용한 반도체 칩 패키지 또는 칩 온 보드 패키지에서는 카드 몸체를 사용하지 않으므로 이러한 여분 면적을 제거할 수 있다. 또한, 반도체 칩 패키지를 카드 몸체의 삽입부에 삽입하지 않으므로 이러한 과정에서 발생하는 오차도 제거된다. 따라서, 이러한 오차를 고려할 필요가 없으므로 외부 접속단자의 크기를 종래의 칩 온 보드 패키지와 비교해서 더 작게 만들 수 있다. 종래의 외부 접속단자에 대한 정밀도 오차는 ±0.20mm인데 반해서,본 발명에 따르면 칩 온 보드 패키지의 외부 접속단자에 대한 오차를 ±0.10 이하로 줄일 수 있다.However, since the card body is not used in the semiconductor chip package or the chip on board package using the printed circuit board 100 of the present invention, such an extra area can be removed. In addition, since the semiconductor chip package is not inserted into the insertion portion of the card body, an error generated in this process is also eliminated. Therefore, it is not necessary to consider such an error, so that the size of the external connection terminal can be made smaller than that of a conventional chip on board package. While the precision error of the conventional external connection terminal is ± 0.20mm, the present invention can reduce the error of the external connection terminal of the chip-on-board package to ± 0.10 or less.

도 8은 본 발명의 실시예에 따른 인쇄회로기판에 성형부를 형성한 모습을 나타내는 평면도이고, 도 9는 인쇄회로기판에 형성된 성형부를 분리하는 모습을 나타내는 단면도이다.8 is a plan view illustrating a molded part formed on a printed circuit board according to an exemplary embodiment of the present invention, and FIG. 9 is a cross-sectional view illustrating a separated part formed on a printed circuit board.

도 8 및 9를 참조하면, 인쇄회로기판 위에서 반도체 칩은 여러 개가 한꺼번에 일괄 성형된다. 실시예에서는 8개의 반도체 칩이 성형되는데, 일괄 성형되는 반도체 칩의 개수는 작업 환경 또는 제조 공정에 따라 변경이 가능하다. 성형부(124)는 회전 드릴(140)에 의해 개별 반도체 칩 패키지(120)로 분리된다. 원통형의 회전 드릴(140)이 칩 탑재부(137)를 따라 패키지 몸체(125) 및 인쇄회로기판(130)을 한꺼번에 잘라내어 반도체 칩 패키지(120)를 분리한다. 회전 드릴(140)은 도시된 바와 같이 측면이 H 빔 형상으로 되어 있으므로, 반도체 칩 패키지(120)를 잘라내는 동시에 외관을 매끈하게 다듬을 수 있다. 반도체 칩 패키지(120)는 칩 탑재부(137)와 동일한 평면 크기를 갖는다.8 and 9, a plurality of semiconductor chips are collectively formed on a printed circuit board at a time. In the embodiment, eight semiconductor chips are molded, and the number of semiconductor chips collectively formed may be changed according to a working environment or a manufacturing process. The molding part 124 is separated into the individual semiconductor chip package 120 by the rotary drill 140. The cylindrical rotary drill 140 cuts the package body 125 and the printed circuit board 130 at once along the chip mounting unit 137 to separate the semiconductor chip package 120. Since the rotary drill 140 has an H-beam shape as shown in the drawing, the external shape of the rotary drill 140 may be smoothed while cutting the semiconductor chip package 120. The semiconductor chip package 120 has the same planar size as the chip mounting part 137.

도 10은 본 발명의 실시예에 따른 반도체 칩 패키지를 나타내는 단면도이다.10 is a cross-sectional view illustrating a semiconductor chip package according to an embodiment of the present invention.

도 10을 참조하면, 반도체 칩 패키지(120)는 인쇄회로기판(130)과 패키지 몸체125)의 측면이 동일한 단면을 이룬다. 반도체 칩 패키지(120)의 구조를 살펴보면 다음과 같다.Referring to FIG. 10, the semiconductor chip package 120 has the same side surface of the printed circuit board 130 and the package body 125. Looking at the structure of the semiconductor chip package 120 as follows.

반도체 칩(121)은 접착제(122)에 의하여 인쇄회로기판(130)에 직접 접착된다. 반도체 칩(121)과 인쇄회로기판(130)에 형성된 본딩 패드(131)는 본딩와이어(123)에 의하여 전기적으로 연결된다. 반도체 칩(121), 본딩 와이어(123), 본딩 패드(131)를 포함하는 인쇄회로기판(130)의 전면이 성형수지로 밀봉되어 패키지 몸체(125)가 형성된다. 인쇄회로기판(130)의 뒷면에는 외부접속단자(133)가 형성되며, 관통구멍(132)을 통하여 앞면의 본딩 패드(131)와 연결된다. 외부접속단자(133)는 도 3에 도시된 바와 같이 절연영역에 의하여 서로 전기적으로 분리된다.The semiconductor chip 121 is directly bonded to the printed circuit board 130 by the adhesive 122. The bonding pads 131 formed on the semiconductor chip 121 and the printed circuit board 130 are electrically connected by the bonding wires 123. The front surface of the printed circuit board 130 including the semiconductor chip 121, the bonding wire 123, and the bonding pad 131 is sealed with a molding resin to form a package body 125. An external connection terminal 133 is formed on the rear surface of the printed circuit board 130 and is connected to the bonding pad 131 on the front surface through the through hole 132. The external connection terminals 133 are electrically separated from each other by an insulating region as shown in FIG. 3.

따라서, 본 발명에 따르면 인쇄회로기판에 형성되는 반도체 칩 패키지의 수율이 높아지고, 카드 몸체가 필요 없으므로 반도체 칩 패키지의 제조 비용을 줄일 수 있다.Therefore, according to the present invention, the yield of the semiconductor chip package formed on the printed circuit board is increased, and the cost of manufacturing the semiconductor chip package can be reduced since no card body is required.

또한, 반도체 칩 패키지를 아이씨 카드로 사용할 경우 아이씨 카드의 크기와 외부 접속단자의 크기를 줄일 수 있다.In addition, when the semiconductor chip package is used as an IC card, the size of the IC card and the size of the external connection terminal can be reduced.

Claims (3)

(A) 복수 개의 칩 탑재부가 형성된 인쇄회로기판을 준비하는 단계;(A) preparing a printed circuit board on which a plurality of chip mounting portions are formed; (B) 상기 칩 탑재부에 반도체 칩을 탑재하고, 상기 반도체 칩과 상기 인쇄회로기판을 전기적으로 연결하는 단계;(B) mounting a semiconductor chip on the chip mounting portion and electrically connecting the semiconductor chip and the printed circuit board; (C) 복수 개의 상기 반도체 칩을 일괄 성형하여 성형부를 형성하는 단계; 및(C) forming a molded part by collectively molding a plurality of the semiconductor chips; And (D) 상기 성형부를 개별 반도체 칩 패키지로 분리하는 단계를 포함하는 반도체 칩 패키지 제조 방법에 있어서,(D) a method of manufacturing a semiconductor chip package comprising separating the molded parts into individual semiconductor chip packages, 상기 (D) 단계는 상기 성형부를 상기 반도체 칩 패키지로 분리하는 동시에 상기 반도체 칩 패키지의 외관을 가공하는 공정을 진행하는 것을 특징으로 하는 반도체 칩 패키지 제조 방법.The step (D) of the semiconductor chip package manufacturing method characterized in that the process of separating the molded part into the semiconductor chip package and at the same time processing the appearance of the semiconductor chip package. 제 1항에 있어서, 상기 (D) 단계는 완성된 상기 반도체 칩 패키지의 측면에 대응하여 측면이 오목하게 가공된 원통형의 회전 드릴을 이용하여, 상기 반도체 칩 패키지를 분리하는 동시에 상기 반도체 칩 패키지의 외관을 가공하는 것을 특징으로 하는 반도체 칩 패키지 제조 방법.The semiconductor chip package of claim 1, wherein the step (D) is performed by separating the semiconductor chip package by using a cylindrical rotary drill having a concave side surface corresponding to the side surface of the completed semiconductor chip package. A method of manufacturing a semiconductor chip package, characterized by processing the appearance. 제 2항에 있어서, 상기 인쇄회로기판은 상기 인쇄회로기판에 형성된 상기 칩 탑재부 사이의 간격이 상기 회전 드릴의 직경과 동일한 것을 특징으로 하는 반도체 칩 패키지 제조 방법.The method of claim 2, wherein the printed circuit board has a spacing between the chip mounting parts formed on the printed circuit board and the diameter of the rotary drill.
KR1020000037085A 2000-06-30 2000-06-30 Method for manufacturing a semiconductor chip package KR20020002788A (en)

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