KR20020002053A - Fringe field switching mode lcd - Google Patents

Abstract

PURPOSE: An FFS-LCD(Fringe Field Switching mode Liquid Crystal Display) is provided to obtain an excellent aperture ratio and to prevent short between a gate bus line and a common signal line. CONSTITUTION: Counter electrodes(22) are formed in matrix form on a lower substrate(20). Each counter electrode is arranged with regular distances with near counter electrodes(22). Plural gate bus lines(23) are arranged among rows of the counter electrodes parallel. First and second common electrodes(24a,24b) are arranged at both upper ends of a counter electrode to connect counter electrodes each other. A gate insulating film is formed on the lower substrate, and a channel layer is formed thereon. The gate insulating film is etched to open a part of the first and second common electrodes contacted with the counter electrodes. Data bus lines(26) are formed across the gate bus lines to be arranged among the rows of the counter electrodes. Drain and source electrodes(26a,26b) are formed to be overlapped with both sides of a gate electrode. To prevent signal delay of the counter electrodes, an auxiliary common electrode(26c) is formed to connect the first and second common electrodes across the counter electrodes. Pixel electrodes(28) are formed at each unit pixel to be overlapped with the counter electrodes. The common electrodes are formed at both sides of the counter electrodes, and the auxiliary common electrode is formed to connect the common electrodes.

Description

Fringe field drive mode liquid crystal display device {FRINGE FIELD SWITCHING MODE LCD}

The present invention relates to a fringe field drive mode liquid crystal display device, and more particularly, to a fringe field drive mode liquid crystal display device capable of increasing the aperture ratio.

In general, a fringe field switching mode LCD (hereinafter referred to as FFS-LCD) is proposed to improve the low aperture ratio and transmittance of a general in-plane switching (IPS) LCD. 98-9243.

The FFS-LCD includes a top and bottom substrate spaced apart from each other with a predetermined cell gap, a liquid crystal interposed between the top and bottom substrates, and a counter electrode and a pixel electrode formed on the inner side of the bottom substrate. The counter electrode and the pixel electrode are formed of a transparent conductor, and the distance between the counter electrode and the pixel electrode is smaller than the cell gap. Accordingly, a fringe field is formed between the electrodes and over the electrodes.

1 is a plan view showing a lower substrate structure of an FFS-LCD.

Referring to FIG. 1, the gate bus line 3 and the data bus line 7 are intersected and arranged on the lower substrate 1 to define a unit pixel Pixel. The thin film transistor TFT is disposed near an intersection point of the gate bus line 3 and the data bus line 7. The counter electrode 2 is formed of a transparent conductor and is formed for each unit pixel pix. In this case, the counter electrode 2 may be formed in the shape of a square plate or in the form of a comb. The common signal line 30 is disposed in contact with the counter electrode 2 in order to continuously supply the common signal to the counter electrode 2. At this time, the common signal line 30 is formed of a metal film having excellent signal transmission characteristics, and is generally formed simultaneously with the gate bus line 3 as a metal film for a gate bus line. In addition, the common signal line 30 is formed to be in contact with a predetermined portion of the counter electrode 2 while being parallel to the gate bus line 3. The pixel electrode 9 is formed in the unit pixel pix so as to overlap the counter electrode 2 with a gate insulating film (not shown) therebetween. In this case, the pixel electrode 9 is formed to include several branches 9a. The branches 9a are arranged at equal intervals, and the width of the branches 9a is determined in a range in which a fringe field can be formed between the exposed counter electrode 2 and the branches 9a. In addition, the pixel electrode 9 overlaps with a predetermined portion of the counter electrode 2 to form a storage capacitance Cst.

In addition, a predetermined portion of the pixel electrode 9 is in contact with a predetermined portion of the thin film transistor TFT so that a data bus line signal is applied to the pixel electrode 9 when the gate bus line 3 is selected. On the other hand, although not shown in the figure, the upper substrate facing the lower substrate 1 is opposed and replaced with a width larger than the distance between the pixel electrode 9 and the exposed counter electrode 2.

The FFS-LCD having such a configuration operates as follows.

When an electric field is formed between the counter electrode 2 and the pixel electrode 9, the distance between the counter electrode 2 and the pixel electrode 9 is smaller than the distance between the upper and lower substrates, so that the pixel electrode 9 and the branch ( A fringe field is formed between 9a) and the exposed counter electrode 2 and above the electrode. Accordingly, a fringe field is applied between the counter electrode 2 and the pixel electrode 9 as well as on the electrode to operate most liquid crystal molecules (not shown) in the pixel. Thereby, a high opening rate and a high transmittance can be realized.

However, the conventional FFS-LCD has the following problems.

Since both the counter electrode 2, the gate bus line 3, and the common signal line 30 are formed on the surface of the lower substrate 1, insulation of the gate bus line 3 and the common signal line 30 is required. It is becoming. Accordingly, conventionally, as shown in FIG. 1, the gate bus line 3 and the common signal line 30 are spaced apart from each other by a predetermined distance d.

For this reason, the aperture ratio is encroached because the width of the black matrix formed at the portion opposite to the upper portion of the gate bus line 3 and the common signal line 30 must be increased for light blocking before the electric field is applied.

In addition, since the ITO material constituting the counter electrode 2 is not so excellent in etching characteristics, an etching residue is likely to be generated during an etching process for forming the counter electrode 2. In particular, when the etching residues remain in the portion between the gate bus line 3 and the common signal line 30, the gate bus line 3 and the common signal line 30 are shorted.

Accordingly, an object of the present invention is to solve the above-mentioned conventional problems, and to provide a fringe field drive mode liquid crystal display device capable of preventing short circuits of gate bus lines and common signal lines while ensuring an aperture ratio.

1 is a plan view showing a typical fringe field driving mode liquid crystal display device.

2A to 2C are plan views illustrating a fringe field drive mode liquid crystal display device according to the present invention;

(Explanation of symbols for the main parts of the drawing)

20-lower substrate 22-counter electrode

23-gate bus lines 24a, 24b-first and second common electrode

26-Data bus lines 26a, 26b-Source, drain

26c-auxiliary common electrode 28-pixel electrode

28a-slit

In order to achieve the above object of the present invention, the present invention, the lower substrate; A transparent counter electrode arranged in a matrix form on the lower substrate; Gate bus lines respectively disposed between the rows of the counter electrodes; First and second common electrodes formed on the same material and on the same plane as the gate bus line and disposed on both sides of the counter electrode to connect the counter electrodes adjacent to each other; A gate insulating layer covering an upper portion of a lower substrate on which the counter electrode, the gate bus line, and the first and second common electrodes are formed; A data bus line formed on the gate insulating layer and formed between the columns and the columns of the counter electrode while being orthogonal to the gate bus lines; An auxiliary common electrode formed on the same material and on the same plane as the data bus line and connecting the first and second common electrodes; A thin film transistor disposed at an intersection of the gate bus line and the data bus line, respectively; A passivation layer covering an upper portion of the lower substrate on which the data bus line and the auxiliary common electrode are formed; And a pixel electrode formed on the passivation layer and in contact with a predetermined portion of the thin film transistor and forming the counter electrode and the fringe field, wherein the counter electrode and the pixel electrode are formed of a transparent conductive layer. .

(Example)

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

2A to 2C are plan views of the fringe field driving mode liquid crystal display according to the present invention.

Referring to FIG. 2A, a counter electrode 22 is disposed in a matrix on the lower substrate 20. At this time, the counter electrode 22 is formed of a transparent conductor, for example, an ITO layer, and is formed in a plate shape. The counter electrode 22 is spaced apart from the adjacent counter electrodes 22 by equal intervals. The plurality of gate bus lines 23 are arranged in rows and events of the counter electrodes 22, respectively, and are arranged in parallel with each other. In this case, the gate bus line 23 may include a gate electrode 23a protruding toward each counter electrode 22, and the shape of the counter electrode 22 may be partially modified due to the protrusion of the gate electrode 23a. Can be. In addition, at the same time as the gate bus line 23 is formed, the first and second common electrodes 24a and 24b connecting the left and right adjacent counter electrodes 22 are disposed on both upper ends of the counter electrodes 22, respectively.

Then, referring to FIG. 2B, a gate insulating film (not shown) is covered on the lower substrate 20 on which the counter electrode 22, the gate bus line 23, and the common electrode 24 are formed. In addition, a channel layer (not shown) is formed on a predetermined portion of the gate insulating film including the gate electrode 23a. Thereafter, the gate insulating film is etched such that predetermined portions of the first and second common electrodes 24a and 24b in contact with the counter electrode 22 are opened. In this case, although the etching of the gate insulating film is not shown in the drawing, the etching is performed at the same time as the etching process for opening the pad formed on the outer substrate. Subsequently, the data bus lines 26 are formed so as to intersect the gate bus lines 23 and are disposed between the rows and the columns of the counter electrodes 22, respectively. In this case, the data bus line 26 is spaced apart from the counter electrode 22 by a predetermined interval, and at the same time as the data bus line 26 is formed, the drain and source 26a may overlap with both sides of the gate electrode 23a. 26b) is formed. In addition, in order to prevent the signal delay of the counter electrode 22 at the same time as the data bus line 26 is formed, the first common electrode 24a and the second common electrode 24b are disposed to cross the counter electrode 22. The auxiliary common electrode 26c to be connected is formed. Reference numeral c denotes a contact portion of the auxiliary common electrode 26c and the first and second common electrodes 24a and 24b.

Next, as shown in FIG. 2C, a protective film (not shown) is covered on the lower substrate 20 on which the data bus lines 26, the drains, the sources 26a and 26b, and the auxiliary common electrode 26c are formed. . Then, the protective film is etched to expose the source 26b. Thereafter, the pixel electrode 28 is formed in each of the unit pixels so as to contact the exposed source 26b while overlapping the counter electrode 22 on the gate insulating film (not shown). In this case, the pixel electrode 28 includes a plurality of branches 28a exposing the counter electrode 22. The branches 28a are arranged at equal intervals, and the width of the branches 9a is such that a fringe field can be formed between the exposed counter electrodes 22. In addition, each of the branches 28a is connected at one end, is in electrical contact, and is also in electrical contact with the source 26b. In addition, the pixel electrode 28 is formed to overlap a predetermined portion with the auxiliary common electrode 26c and the counter electrode 22 to form a storage capacitance Cst.

As such, the common electrodes 24a and 24b for transmitting the common signal to the counter electrode 22 are formed on both sides of the counter electrode 22, and the auxiliary common electrode 26c for connecting the common electrodes 24a and 24b to each other. Since it is formed on the gate insulating film, it is possible to ensure insulation between the common electrodes 24a and 24b and the gate bus line. In addition, in order to ensure insulation between the gate bus line and the common electrode, it is not necessary to space the predetermined distance, thereby increasing the opening area.

As described in detail above, according to the present invention, the counter electrode is extended and arranged adjacent to the gate bus line, and common electrodes for transmitting a common signal to the counter electrode are formed on both sides of the counter electrode and the gate insulating film. Accordingly, in order to ensure insulation between the common electrode and the gate bus line, there is no need to space the common electrode and the gate bus line apart by a predetermined distance, thereby increasing the opening area. Therefore, the aperture ratio is greatly improved. In addition, since the auxiliary common electrode and the gate bus line are formed on different planes, a short between the auxiliary common electrode and the gate bus line can be prevented.

Claims (2)

Lower substrate; A transparent counter electrode arranged in a matrix form on the lower substrate; Gate bus lines respectively disposed between the rows of the counter electrodes; First and second common electrodes formed on the same material and on the same plane as the gate bus line and disposed on both sides of the counter electrode to connect the counter electrodes adjacent to each other; A gate insulating layer covering an upper portion of a lower substrate on which the counter electrode, the gate bus line, and the first and second common electrodes are formed; A data bus line formed on the gate insulating layer and formed between the columns and the columns of the counter electrode while being orthogonal to the gate bus lines; An auxiliary common electrode formed on the same material and on the same plane as the data bus line and connecting the first and second common electrodes; A thin film transistor disposed at an intersection of the gate bus line and the data bus line, respectively; A passivation layer covering an upper portion of the lower substrate on which the data bus line and the auxiliary common electrode are formed; And A pixel electrode formed on the passivation layer, contacting a predetermined portion of the thin film transistor, and forming a fringe field with the counter electrode; And the counter electrode and the pixel electrode are formed of a transparent conductive layer. The fringe field driving mode liquid crystal display of claim 1, wherein the counter electrode is formed in a plate shape, and the pixel electrode is formed in a plate shape and includes a plurality of slits for opening a predetermined portion of the counter electrode. .