KR200196610Y1 - Frame analysis unit for image signal processing - Google Patents

Abstract

The present invention relates to a frame analysis apparatus for processing a video signal, comprising: a sync separation circuit for separating a complex video signal into a video signal and a sync signal and generating horizontal sync, vertical sync and field segmentation signals using the sync signal; Address and control signal generation logic for generating a storage position and a control signal of the image data currently input by the signal transmitted from the synchronization separation circuit; An A / D converter for quantizing the composite video signal according to a sampling frequency and converting the composite video signal into digital video data; A memory for individually storing even field images, odd field images, and frame images; A correlation processor for comparing temporal differences between images; It is composed of interface unit for outputting video signal to external controller. The frame analysis apparatus for image signal processing having such a structure separates and outputs a composite video signal into an even field image, an odd field image, and a frame image, and removes afterimages and reduces hardware burden.

Description

Frame Analysis Unit for Image Signal Processing

The present invention relates to image frame analysis, and more particularly, converts a composite image signal, divides it into an even field and an odd field, and analyzes the motion correlation for each field and analog. And an apparatus for digitally outputting an even field image, an odd field image, and a frame image.

In general, an image signal processing system receives a composite image signal using a charge coupled device (CCD) camera to display an image frame through image processing. Such a system is an image signal processing apparatus for implementing a digital image processing algorithm, and is applied to image morphology, neural network, natural color image processing, image recognition, and knowledge based image analysis. In addition, block-based motion compensation is applied to reduce temporal redundancy of image frames, and applied to a compression algorithm based on DCT (Discrete Cosine Transform) to reduce spatial redundancy.

Figure 1 shows a block diagram of a conventional video signal processing system.

As shown in FIG. 1, a conventional video signal processing system includes an analog / digital converter (hereinafter referred to as an A / D converter) 30, a microcomputer 40, a first memory 50, and a second memory 60. It consists of).

Referring to the operation of the device configured as described above in more detail. First, an A / D converter 30 for receiving a composite video signal through an image pickup device camera 20 with a lens 10 and converting it into a digital signal; The A / D converter 30 separates a signal into a video signal and a synchronous signal through a synchronous separation circuit, and generates a horizontal synchronous, vertical synchronous and field separation signal using the synchronous signal to store a frame image in a memory. A first memory 50; A second memory 60 for storing consecutive frame images; A microcomputer 40 connected to the A / D converter 30 and connected to the first memory 50 and the second memory 60 and controlling the entire circuit part; The microcomputer 40 is configured to output a digital video signal by controlling an interface.

However, such a conventional technology outputs a digital video signal by controlling a video signal converted through an A / D converter on a frame basis, so that two field images (even field images) are captured when a video signal of a moving object is captured. , Odd-field images) are staggered due to the time difference between them.

The present invention was devised to solve the conventional problems as described above, by converting a composite video signal into an even field and an odd field, and analyzing the motion correlation for each field and analog and digital. An apparatus for outputting an even field image, an odd field image, and a frame image is provided.

Another object of the present invention is to provide an apparatus capable of developing an image processing algorithm using an even field image, an odd field image, and a frame image.

The frame analysis apparatus for image signal processing having such a configuration converts a composite video signal into an even field and an odd field, and analyzes the motion correlation for each field, and an analog and digital even field image and odd number. The effect of outputting a field image and a frame image can be obtained.

1 is a block diagram showing a configuration for the prior art.

2 is a block diagram showing the configuration of a frame analysis apparatus for processing image signals according to an embodiment of the present invention.

3 is a detailed circuit diagram of a synchronous separation circuit according to the present invention.

4 is a detailed circuit diagram of an image signal output according to the present invention.

♣ Explanation of symbols for the main parts of the drawing ♣

100: image pickup device camera 110: synchronous separation circuit

120: logic for generating address and control signal 130: A / D converter

140: frame memory 150: even field memory

160: odd field memory 170: correlation processing unit

180: interface unit

The present invention to solve the above object is to convert the composite video signal into an even field and an odd field, and to analyze the motion correlation for each field and the analog and digital even field image, odd field image, frame A frame analysis apparatus for processing an image signal for outputting an image, comprising: an imaging device camera, a synchronous separation circuit, an address and control signal generation logic, an analog-to-digital converter (hereinafter, referred to as an A / D converter), a frame memory, and an even number It consists of a field memory, an odd field memory, a correlation processing unit and an interface unit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing a configuration of a frame analyzing apparatus for processing image signals according to an embodiment of the present invention. As illustrated in FIG. 2, the image pickup device camera 100 receives a predetermined image as an input and outputs a composite image signal.

The synchronizing separation circuit 110 is connected to the image pickup device camera 100 and the address and control signal generating logic 120, and separates the composite image signal into the image signal and the synchronizing signal and uses the synchronizing signal to perform horizontal sync (Hsync). ), Vsync and Findex signals are generated. Horizontal synchronization is separated by pulse signals appearing at regular intervals from the synchronization signal, and vertical synchronization is separated from equalization pulses that appear when the field changes. The field separation signal separates the even / odd number of the current field by the duty ratio of horizontal synchronization and vertical synchronization in the equalization pulse.

The address and control signal generation logic 120 is connected to the synchronous separation circuit 110, and the image data currently input by the vertical synchronous, horizontal synchronous, and field division signals transmitted from the synchronous separation circuit 110. Generates the storage position and control signal. When the sampling clock is input, the horizontal address is increased according to the clock. When the vertical synchronization is input, the horizontal address is initialized to 0 and the vertical address is increased. At this time, whether the even field or the odd field is classified by the Findex signal is determined whether the vertical address is stored in the even address or the odd address. Therefore, the vertical address is increased by 2 lines by horizontal synchronization, and the storage positions of even and odd addresses are determined by Findex. Vertical sync is used to initialize the vertical position.

The A / D converter 130 is connected to the imaging device camera 100 and converts the composite video signal into digital image data by quantization by a sampling frequency.

The frame memory 140 is interconnected with the address and control signal generation logic 120 and the A / D converter 130, and stores the even and odd addresses determined by the address and control signal generation logic 120. The frame image in which the even field and the odd field are combined is stored in the digital image data output through the A / D converter 130 at the position.

The even field memory 150 is interconnected with the address and control signal generation logic 120 and the A / D converter 130, and the image data when Findex is even in the address and control signal generation logic 120. Stores even field data and increases the horizontal address by 1 according to the horizontal synchronization signal.

The odd-field memory 160 is interconnected with the address and control signal generation logic 120 and the A / D converter 130, and the image data when Findex is odd in the address and control signal generation logic 120. Odd field data is stored and the horizontal address is increased by 1 according to the horizontal synchronization signal.

The correlation processor 170 is connected to the even field memory 150 and the odd field memory 160, and the even field image and the odd field are output through the even field memory 150 and the odd field memory 160. Compare the temporal differences between the images.

The interface circuit 180 is interconnected to the frame memory 140, the even field memory 150, and the odd field memory 160, and stores stored image data according to a request of an external controller. Multiplexing the address and data to the host to transmit the data, and digitally frame image data, even field image data, and odd field image data using USB (Universal Serial Bus), RS-232, and RS-422 ports. Output In addition, analog frame image data, even field image data, and odd field image data are output through the external RS-170.

The overall configuration of the frame analysis apparatus for processing the image signal according to the embodiment of the present invention was described above with reference to FIG. 2, and the main processing for each part thereof is described in detail with reference to FIGS. 3 and 4 as follows.

3 is a detailed circuit diagram of a synchronous separation circuit of a composite video signal according to the present invention, which is interconnected with the image pickup device camera 100 of FIG. 2 and an address and control signal generation logic 120, and converts a composite video signal into a video signal. And sync signal and generate horizontal sync (Hsync), vertical sync (Vsync) and field index (Findex) signals. Horizontal synchronization is separated by pulse signals appearing at regular intervals from the synchronization signal, and vertical synchronization is separated from equalization pulses that appear when the field changes. The field separation signal separates the even / odd number of the current field by the duty ratio of horizontal synchronization and vertical synchronization in the equalization pulse.

4 is a detailed circuit diagram of the analog interface output and the digital interface output to the interface unit 180 of FIG. 2, wherein the analog video signal output receives an 8-bit digital signal, and the upper two beads are input to the processing unit 340. The remaining 6 bits are input to the first decoder 310 and the second decoder 320 by 3 bits, and then transmitted to the processor 340 through a predetermined process. The processor 340 converts a signal input through the upper two bits and the first decoder 310 and the second decoder 320 into a video signal and outputs the video signal to the analog port 350. In addition, as a detailed circuit diagram of the digital interface output to the interface unit 180 of FIG. 2, the controller 360 sequentially receives the input of a digital signal, and may be a USB (Universal Serial Bus: USB), RS-232, or RS-422 port. And, the port interface 370 is interconnected with the controller 360 and the digital port 380, the USB port, RS-232 port, connected to the digital port 380 through the controller 360, Digital video signal is output to external controller through RS-422 port.

As described above, according to the frame analysis apparatus for image signal processing according to the present invention, one frame image is divided into an even field image and an odd field image, and the correlation of moving objects using the time difference of the separated field image Has the effect of comparing

In addition, the present invention has the effect of reducing the burden on the hardware and the execution time by outputting the even field image and the odd field image, respectively, and processing the frame image output, which is a combination of the fields, by a single board.

In addition, when capturing an image signal of a moving object, there is an effect of removing an afterimage generated due to a time difference between two field images (even field image and odd field image).

Claims (1)

It converts a composite video signal into an even field and an odd field, analyzes the correlation of each field, and outputs a field image and a frame image. In It is connected to the image pickup device camera and the logic for generating the address and control signal, and separates the composite video signal into the video signal and the sync signal, and extracts the horizontal sync (Hsync) by extracting the pulse signal appearing at regular intervals from the sync signal. Separating vertical sync (Vsync) by extracting equalization pulse that appears when is changed, and separating the even / odd field division (Findex) signal of current field by classifying duty ratio of horizontal sync and vertical sync in equalizing pulse. ; The synchronization circuit is connected to an address and control signal generation logic and an A / D converter. The findex is an even number in the address and control signal generation logic, and the even field data of the image data is separately stored in the even field memory. Save and read that Findex is odd, and store odd field data among the image data in the odd field memory separately configured, make sure that the image data is stored in the even field and the odd field, and combine each field data in the frame to separate frame memory. An even field memory, an odd field memory and a frame memory including a frame memory for storing an image; A correlation processor interconnected to the even field memory and the odd field memory, and comparing a temporal difference between an even field image and an odd field image output through the even field memory and the odd field memory; And an interface unit interconnecting the correlation processing unit and the frame memory and separately outputting a frame image, an even field image, and an odd field image to an external controller through an interface unit.