KR200190099Y1 - A combined cache with memory - Google Patents

Abstract

The present invention is to provide a memory combined cache of associative mapping cache structure that can use the cache as main memory by adding only a minimum control circuit in the associative mapping cache structure. The present invention responds in advance to the cache / memory bits representing the cache performance operation of the microprocessor stored in the storage means of the system flag for controlling the microprocessor itself hardware in the conventional associated mapping cache structure, when the cache operates as main memory in advance. It further comprises a plurality of selection means for setting the tag register by selecting the address value of the set cache memory mapping area, and setting the tag register by selecting the value loaded on the address bus when the cache operates as the cache itself, Each of the above validity when the cache operates as main memory Set all the bit registers to valid so that the internal cache can be used as main memory.

Description

Memory Combination Cache

The present invention is a device designed to utilize the microprocessor's internal cache as main memory, and more particularly relates to a full associative mapped memory combined cache.

High-performance microprocessors include a large cache inside the processor to improve processor performance. The cache improves the performance of the system by storing frequently used data in the slow access media (ie, main memory) in the cache, which is a faster access media, and delivering the necessary data to the microprocessor faster. In most computer systems, main memory uses DRAM (Dynamic Random Access Memory (DRAM)), which is inexpensive and easy to implement, and cache memory, which is expensive, but has fast access speed. Static Random Access Memory (SRAM). In the case of personal computers (PCs), high-performance PCs such as Pentium have large cache memory inside the microprocessor, 16K bytes for Pentium, and Pentium-Pro. In addition to the internal 16K byte cache, it also has a 512K byte SRAM cache.

When you fetch some data from memory, it is called a cache hit when the data is in the cache and can be used without access to main memory. This is called a cache hit. In the case of a cache miss (if no data is in the cache), the main memory (external memory module) is accessed to retrieve data. At this time, if there is a free space in the cache, the data near the currently accessed data is read and stored in the cache as appropriate (in consideration of the locality of the process). Then, if there is no free space in the cache, a replacement algorithm (a new block is copied from main memory). When it comes up into cache memory, the content that originally existed at that location is lost, choosing which block is best to be lost, for example random, LRU-Least Recently Used-, FIFO-First In First Out. Replace blocks of data deemed unnecessary by such a method and load them into the block.

The fully associative mapped cache structure is a cache structure that uses all of the address bits as a tag, and stores the address of the data in the tag register of the cache when loading the data into the cache. For convenience of explanation, it is assumed that the address is 16 bits, the data bus is 8 bits, and the cache capacity is 2 bytes.

Fig. 1 shows a conventional fully associative mapping cache structure used only as a cache function, in which an address input via an address bus is associated with a value stored in each tag register (tag registers 0,1-10,11). Compared via the first comparator 12 and the second comparator 13, a tag hit latch 14 is set which indicates a tag hit when a value equal to the input address is present in one of the tag registers. Then, the valid bit of the 1-bit valid bit register (indicating that the data value stored in each data register is a useful value) corresponding to the tag register that generated the tag hit is checked, and the bit is " valid ". Check if it is set. If the tag hit latch 14 is " 1 " and the valid bit is " 1 ", a cache hit is generated, and the value of the data register that caused the tag hit in the data register is loaded or read on the data bus.

In the conventional fully associative cache having the above structure, the capacity of the cache is gradually increasing, and the operation of the microprocessor and the microcontroller requires a RAM for storing data, that is, a memory module capable of reading and writing. When a microprocessor with built-in memory is used as a central processing unit (CPU) in a computer system (that is, a system that requires very large memory capacity), the cache is used for cache-specific purposes. When used for system control that requires high-speed processing, a large cache is allocated and used to improve the processing speed of the system and maximize the utilization of the cache.

The present invention has been devised based on the above requirements. In the fully associative mapping cache structure, the cache can be used as the main memory by adding only a minimum control circuit, so that the fully associative mapping cache can maximize the utilization of the cache. Its purpose is to provide a memory-compatible cache.

Is a block diagram illustrating a conventional fully associative mapping cache structure used only as a cache function.

2 is a conceptual diagram of a memory combined cache.

3 is a diagram illustrating an algorithm that is a concept of the present invention.

4 is a block diagram showing a fully associated mapping cache structure as an embodiment of the present invention.

The present invention for achieving the above object is a plurality of tag registers, a plurality of data registers, a plurality of comparators for comparing the tag value of the address bus and the value of each tag register, and a plurality of indicating the validity of each data register A fully associative mapping scheme comprising a valid bit register, the cache in response to a cache / memory bit indicating a cache performing operation of the microprocessor stored in a storage unit of a system flag for controlling the microprocessor itself hardware. When the cache operates as the main memory, the tag register is set by selecting an address value of a preset cache memory mapping region, and when the cache operates as the cache itself, the tag register is set by selecting a value loaded on the address bus. Multiple selection means And a cache of fully associative mapping scheme that combines memory that sets each valid bit register as all valid when the cache operates as main memory.

Hereinafter, with reference to the accompanying drawings looks at the present invention in detail.

Fig. 2 conceptually illustrates a memory-compatible cache, which includes a microprocessor 22 comprising an X-byte sized internal cache 20 and a system control register 21 for controlling the microprocessor itself hardware. Is composed of a memory area 24 accessible by a microprocessor. Each bit of the conventional system control register 21 is designed to control the controllable portion of the hardware constituting the microprocessor, the appropriate bit among the unused bits of the system control register in the present invention. Select one to set the cache / memory bit 23. The cache memory is written into the cache or the main memory according to the value set in the cache / memory bit 23. If the value is "1", it is assumed to be used as main memory, and if it is "0", it is used as a cache. The X value of the size X bytes of the cache memory 20 is determined as a value that the microprocessor can most efficiently operate when designing the microprocessor, and the value of the size S bytes of the accessible memory area is micro. This is determined by the number of bits in the processor's address bus. For example, if the number of address bits is 10 bits, the value of S is 10 power of 2, that is, 1024.

The hatched cache memory area refers to the area where the cache memory exists among the accessible address areas when the cache is used as the memory. As shown in the drawing, the cache memory area becomes the cache memory size from the cache memory mapping start point. That is, when the cache memory mapping start point is "0", addresses 0 to (X-1) become cache mapping areas.

In addition, when the microprocessor is used for system control, in order to utilize the microprocessor internal cache as main memory, the operation algorithm of the memory controller is changed to the algorithm shown in FIG. 3, and FIG. 3 illustrates an algorithm for obtaining data from the memory. As shown, what is shown in the block BL is an algorithm that becomes the concept of the present invention. Specifically, referring to FIG. 3, the first step 31 of checking the cache / memory bit 23 of the system control register 21 in the microprocessor, that is, the cache / memory bit 23 is “1”, namely, A second step (32) of checking if an address exists in the cache memory area if the cache is used as memory, fetching data from an external memory module (34) if it does not exist in the memory area, and the address in the cache memory area If present, the third step is to fetch 33 data from the cache memory. In the first step, when the cache / memory bit 23 is " 0 ", i.e., when the cache memory is used as a cache, an algorithm for checking whether a cache hit has occurred (35) is used. In the case where the value of the cache / memory bit 23 is " 0 ", since the cache memory is widely known as a conventional technology using the cache memory as a cache, the detailed description is omitted here.

The present invention is based on the algorithm described above, in order to use the microprocessor internal cache as main memory when the microprocessor is used for system control, the data is accessed from the cache memory when the data existing in the cache memory mapping area is accessed. When accessing data outside of the cache memory mapping area, the memory structure of the fully associated mapping method is implemented by adding only a few control circuits to the conventional fully associated mapping hardware to access the data from the external main memory. do.

FIG. 4 illustrates the fully associative mapping cache structure of the present invention, and further includes first and second 2x1 multiplexers 45 and 46 to set a tag register in a conventional fully associative mapping cache structure. . When the first multiplexer 45 receives a cache / memory bit as a selection signal and operates as a cache (when the cache / memory bit is “0”), the first multiplexer 45 selects an address input through an address bus as in the prior art and uses a tag register. When inputting to 0 (40) and operating as main memory (when the cache / memory bit is "1"), a value set to a value of "0" is selected and input to the tag register 0 (40). At this time, "0" is an address value corresponding to the start point of the cache memory mapping area. When the second multiplexer 46 receives a cache / memory bit as a selection signal and operates as a cache (when the cache / memory bit is “0”), the second multiplexer 46 selects an address input through an address bus as in the prior art and uses a tag register. When inputting to 1 (41) and operating as main memory (when the cache / memory bit is "1"), a value set to a value of "1" is selected and input to the tag register 1 (41). At this time, "1" is an address value corresponding to the second cache memory mapping area. If you want to set the starting address of the mapping address to something other than 0, change the value stored in each tag register properly when operating as main memory. For example, if you want to map from hexadecimal 1000H to 1001H, set the value of tag register 0 to "1000H" and the value of tag register 1 to "1001H".

In addition, the 1-bit valid bit registers 0, 1 (47, 48) always have a value of "1" when the cache / memory bit is "1" with reference to the cache / memory bit. The circuit for setting the register to have a value of "1" is easily implemented as a known technique, and thus the description thereof is omitted.

Referring to the drawings will be described the operation of one embodiment when the cache memory of the present invention operates as the main memory.

In the case of accessing data existing in address 1 of the cache memory mapping area, the cache / memory bit is "1", the tag value of "0" in tag register 0, and the tag value of "1" in tag register 1 The first bus is compared with the address bus (address 1) input through the first comparator 42 and the second comparator 43 so as to match the tag value of the tag register 1 to the value of "1" through the second comparator 43. After outputting the value, the value is passed through the OR gate 49 and stored in the tag hit latch 44. In this case, the signal output from the second comparator 43 is input and the value of the data register 1 51 is output to the data bus through the third multiplexer 50. When the cache operates as the main memory, each of the 1-bit valid bit registers 47 and 48 is set to "1". Therefore, a value of "1" is output through the fourth multiplexer 52, so that the tag hit latches. A cache hit is generated by logically multiplying by the value of " 1 "

In the case of accessing data existing in the 100H address outside the cache memory mapping area, the tag of the 100H address does not match any preset tag value. Thus, no cache hit occurs and the microprocessor reads or writes data from the external memory module.

The present invention is not limited to the 16-bit address bus, the 8-bit data bus, and the two-byte cache memory, but is scalable to the n-bit address bus, the m-bit data bus, and the k-byte cache.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention, as described above, adds a minimum control circuit to a conventional fully associated mapping cache, so that when a microprocessor equipped with a large, fully associated mapping cache is used as a general-purpose central processing unit in a computer system, the cache is used for cache-specific purposes. When used for system control, a large amount of cache is allocated and used for memory control, which maximizes the utilization of the cache and lowers the price when configuring the system control board. Also, the capacity of the cache inside the microprocessor is sufficient. If it is large, the system control board can be configured without a separate memory module. Even if the capacity of the cache is smaller than the required memory size, the size of the memory to be separately configured can be greatly reduced, which can bring a great effect in terms of cost.

Claims (3)

Fully associative mapping comprising a plurality of tag registers, a plurality of data registers, a plurality of comparators for comparing the tag values of the address bus and the value of each tag register, and a plurality of valid bit registers indicating the validity of each data register In the cache, In response to a cache / memory bit indicating a cache performing operation of the microprocessor stored in a storage unit of a system flag for controlling the hardware of the microprocessor itself, the start address value of the cache memory mapping area when the cache operates as main memory. Selects the tag register and sets the tag register, and when the cache operates as the cache itself, a plurality of selection means for selecting the value loaded on the address bus to set the tag register, A fully associative mapping scheme that combines memory that sets each valid bit register as valid when the cache operates as main memory. The method of claim 1, A cache of a fully associative mapping scheme that uses a memory capable of arbitrarily changing a start address value of the cache memory mapping region. The method of claim 2, The start address value of the cache memory mapping area is A fully associative mapping cache that combines memory with "0" for minimal hardware additions.