KR200152536Y1 - A circuit of normalization - Google Patents

Abstract

The present invention relates to a normalization circuit. In the related art, a continuous zero is detected from an input stage, and then a shift is performed and a zero is found from the result of the shift. The final result is obtained by sequential zero discovery and shift. As it was determined, there was a problem with a late delay time. In order to find a continuous zero, the present invention divides the upper three parts into the upper three parts, detects whether each substring is zero, and calculates whether the current stage is shifted by the zero detection. By calculating whether the substring is zero and determining whether the current stage is shifted through the multiplexer, it is possible to calculate the shift from the front stage to the next stage.

Description

Normalization circuit

1 is a conventional 2 ⁿ bit normalization circuit diagram.

2 is a normalized circuit diagram when 2 ⁿ bits (n is odd) of the present invention.

3 is a normalized circuit diagram when 2 ⁿ bits (n is even) of the present invention.

4 is a detailed circuit diagram of a 2 ⁿ bit 2 level zero detector according to the present invention.

* Explanation of symbols for main parts of the drawings

1A-1,1A-2: 2 ^N-2 bit 2-level zero detector

1N-1: 1-bit level zero detector 1N-2: 1-bit 2 level zero detector

2A-1,2A-2: 2 ^N-1 Bit Left Shifter

2B-1,2B-2: 2 ^N-2 Bit Left Shifter

2N-1,2N-2: 1-bit left shifter 2M-2: 2-bit left shifter

The present invention relates to the normalization of numbers resulting from the real addition of real numbers. In particular, the conventional normalization circuit finds zero at the input stage, determines whether to shift, and finds continuous zeros with the next data shifted. However, the present invention relates to a normalization circuit that is suitable for having a fast delay time with the addition of a small circuit by calculating the shift from the front end to the next stage.

2 ^N-bit normalization circuit of jolae is a top 2 ^N-1-bit comparison, and an inverter (I1) to zero applied by heat to the NOR gate (NR1) of a first of the input terminals, as shown in the accompanying drawings FIG. 1 by receiving the output (Sn- ^₁₎ 2 ^_N-1 bit zero detector (1A) and the 2 ^N-1 bit zero detector (1A) output signal (Sn- ₁₎ a selection stage (Sn- ₁₎ in which zero when compared to zero applied by the heat of the high-2 ^N-1 bits to 2 ^N-1 bit shift to left left shifter (2A) and a top of the input stage ^{2 N-2} bits to the NOR gate (NR2) and the inverter ( I2) through the output (Sn- ₂₎ 2 ^N-2 bit zero detector (1B) and an output signal (Sn- selection stage a ₂₎ in 2 ^N-2 bit zero detector (1B) to (Sn- ₂₎ Is inputted to the select terminal Sn- ₂ , and if it is zero, a 2 ^N-2 bit left shifter 2B for shifting and shifting the upper 2 ^N-2 bits and a row of upper 1 bits are zeroed by the inverter Im. To On the other hand, the 1-bit zero detector 1N outputted through the inverter In and the output signal So of the 1-bit zero detector 1N are inputted to the selection terminal So, and the upper 1 bit is zero. It consists of a 1-bit left shifter (2N) for shifting and shifting, where reference numeral i in the figure is information to be normalized at the input stage, o is normalized information at the output stage, and S is a normalized number (in the most significant bit). Number of consecutive O).

The conventional ^2N bit normalization circuit configured as described above operates in the following order.

That is cheotdan is 2 ^N-1 bit zero detector (1A) to the output (Sn- ₁₎ as compared to zero by applying a sequence of high-2 ^N-1 bits from the NOR gate (NR1) wherein 2 ^N-1-bit left shifter (2A) is the 2 ^N-1 bit zero detector (1A) output signal (Sn- ₁₎ if the received input to the selection stage (Sn- ₁₎ by the inverter (I1) to zero left upper 2 bits of the ^N-1 Shift to the next level without shifting.

In addition, as compared to zero by applying a sequence of the following steps in the ^{2 N-2} bit zero sawooyi ^{2 N-2} bits from the detector (1B) to the NOR gate (NR2) output (Sn- ₂₎ ^{2 N-2} bits in this case a left shifter (2B) is zero if receiving a selection stage (Sn- ₂₎ by an output signal (Sn- ₂₎ of the ^{2 N-2} bit zero detector (1B) to the inverter (I2) the ^{2 N-2} bits Left is shifted to shift or left as it is.

As described above, the process of continuously processing and comparing the upper 1 bits is finally processed. That is, the 1-bit zero detector 1N outputs the strings of the upper 1 bits by comparing the zero applied by the inverter Im so that the 1-bit left shifter 2N is output from the 1-bit zero detector 1N. Since the signal So is input to the selection terminal So by the inverter In and is zero, the upper 1 bit is left to shift.

However, such a conventional ^2N bit normalization circuit finds a continuous zero from the input stage, then performs a shift and finds zero in the result of performing the shift, and finally the result is obtained by sequential zero discovery and shift. As it was determined, there was a problem with a late delay time.

In order to find the continuous zeros, the present invention divides the upper three parts into the upper three parts, detects whether each substring is zero, and calculates whether the current stage is shifted by the zero detection. By calculating whether the substring is zero and determining whether the current stage is shifted through the multiplexer, the normalization circuit is designed to have a faster delay time with the addition of fewer circuits. The present invention will be described in detail with reference to the accompanying drawings.

2 is a normalized circuit diagram when 2 ^N bits (n is an odd number) according to the present invention. As shown in FIG. 2, the output is compared by comparing whether the current and next higher bits are zero in the column of the upper 2 ^N-2 bits. 2S ^-2 bit zero level detection unit 1A-1 and S0 output signal S1 and S0 of the ^2N-2 bit two level zero detection unit 1A-1. - _1, Sn- ₂₎ when receiving a zero top 2 ^N-1 bits or the upper ^{2 N-2} bits to left to shift the 2 ^N-1, and ^{2 N-2} bit left shifter (2A-1, 2B-1 ), A 1-bit zero detector 1N-1 for comparing the application of the 1-bit string to zero by the inverter Im and outputting it through the inverter In, and the 1-bit zero detector 1N−. The output signal So of 1) is input to the selection terminal So, and if it is zero, it consists of a 1-bit left shifter 2N-1 which shifts the upper 1 bit by shifting. , m) is k = 2 ^N -2 ^N-1 -2 ^N-2 , 1 = 2 ^N -2 ^N-1 _, m = 2 ^N -2 ^N-1 -2 ^N-2 .

3 is a normalized circuit diagram when 2 ^N bits (n is an even number) of the present invention, as shown in FIG. 3, compares whether the current bit is higher than the next bit in the column of the upper 2 ^N-2 bits and compares the output signal with zero. ^{_{Sn- 1, Sn- 2) 2 N}} -2 bit 2-level zero detector (1A-2) with the two ^N-2, 2-bit output signal (Sn- of the level detector (1A-2) _{1, 2} to Sn- ) Is input to each of the select terminals Sn- ₁ and Sn- ₂ , and if it is zero, 2 ^N-1 bits and 2 ^N-2 bits left to shift by shifting the upper 2 ^N-1 bits or the upper 2 ^N-2 bits One-bit two-level zero detection unit 1N-2 for comparing the shifters 2A-2 and 2B-2 and the upper bits of the current stage and the next stage in the string of 1 bits and outputting them (S _1, So). And two bits for outputting the output signals S1 and SO of the one-bit two-level zero detection unit 1N-2 to the selection terminals S1 and S0, and shifting the upper two bits or the upper one bit if it is zero; 1-bit left shifter (2M-2 2N-2).

FIG. 4 is a detailed circuit diagram of the two-level zero detection unit in FIGS. 2 and 3, and as shown therein, the first NOR gate NR11 for determining the zero of the upper two ^N-2 bits at the input terminal is ₁ , and second the third NOR gate, which determines the NOR gate (NR12), and then the input stage (is ₃₎ zero of the upper 2 ^N-2 bits in which the next input stage (is ₂₎ to determine the zero of the upper 2 ^N-2 bits in the NR13, the NAND gate ND11 for determining the zero of the current stage by the outputs of the second and third nodal gates NR12, NR13, and outputting the output S1 through the inverter I11, and the first, 3 The zero of the next stage is determined by the output of the NAND gate ND11 input to the selection terminal S with the outputs of the NOA gates NR11 and NR13 as inputs D0 and D1, and the inverters I12 are used. It consists of a multiplexer (MUX) to output (SO).

When described in detail with reference to Figures 2 to 4 of the operation, effects of the present invention configured as described above.

First, the present invention can cover whether the current stage and the next stage are shifted at about the same time by the two-level zero detector of FIG.

That is, the first and then input quinoa through a gate (NR11) input stage (is ₁₎ determining the zero of the upper 2 ^N-2 bits in haejugo via a second NOR gate (NR12) (is ₂₎ in 2 ^N-2 bits It determines the zero of and determines the zero of the upper two ^N-2 bits at the next input terminal (is ₃ ) through the third NOR gate (NR13). In addition, the current stage and the next stage zero are discriminated from the 1-3 NOA gates NR11-NR13, and the zero discrimination of the current stage is performed by the NAND gate ND11 outputting the outputs of the second and third NOA gates NR12 and NR13. Input to the output of the NAND gate ND11 to the output terminal S1 through the inverter I11, and the determination of the next stage is to output the outputs of the first and third NOR gates NR11 and NR13 to the multiplexer MUX. Input to the input terminals D0 and D1 and the output of the NAND gate ND11 to the selection terminal S of the multiplexer MUX, thereby outputting the output of the multiplexer MUX through the inverter I12. (SO) to determine.

On the other hand, the shifter between the first and second stages is driven by the outputs S1 and S0 of the second-level zero detector of FIG. 4, and the shifters of the third and fourth stages are operated by the next two-level zero detector. In the 2 ^N- bit normalization circuit, when n is even, the selection value of the last shift is operated by the output signal SO of the last two-level zero detector as in FIG. Likewise, the value of the shift is selected by the inverters Im and In.

That is, in FIG. 2, when n is an odd number, the 2 ^N-2 bit 2 level zero detection unit 1A-1 compares whether the current and next higher bits are zero in the string of upper 2 ^N-2 bits. The outputs Sn- ₁ and Sn- ₂ , and the ^2N-1 and ^2N-2 bit left shifters 2A ^-1 and 2B-1 are connected to the ^2N-2 bit 2-level zero detection unit 1A-1. If the output signal Sn- ₁ , Sn- ₂ is input to each of the select terminals Sn- ₁ , Sn- ₂ , the upper two ^N-1 bits or the detector 1N-1 receives a string of upper one bits. Since zero is compared by the inverter Im and is output through the inverter In, the last 1-bit left shifter 2N-1 outputs the output signal So of the 1-bit zero detector 1N-1. ) Is input to the selection terminal So, and if it is zero, the upper 1 bit is left to shift.

In FIG. 3, when the normalization circuit has an even number, the ^2N-2 bit 2-level zero detector 1A-2 checks whether the current and next higher bits are zero in the string of upper ^2N-2 bits. Compared to the output (Sn- ₁ , Sn- ₂ ), 2 ^N-1 bit and 2 ^N-2 bit left shifter (2A-2, 2B-2), the 2 ^N-2 bit two-level zero detection unit (1A) -2) input signal (Sn- ₁ , Sn- ₂ ) to each select terminal (Sn- ₁ , Sn- ₂ ), and if it is zero, the upper 2 ^N-1 bit or the upper 2 ^N-2 bit are left 2 bit and 1 bit left shifter since the last 1 bit 2-level zero detector 1A-2 outputs (S _1, So) by comparing whether the current bit and the next bit are higher in the string of the upper 1 bit. 2M-2 and 2N-2 receive the output signals S1 and SO of the one-bit two-level zero detection unit 1N-2 from the selection terminals S1 and S0, and if they are zero, the upper two bits or the upper one bit. Left to shift.

As described in detail above, the present invention divides the upper three parts to find a continuous zero, detects whether each substring is zero, and calculates whether the current stage is shifted by the zero detection. By calculating this zero application and determining whether the current stage is shifted by the multiplexer, it is possible to calculate the shift from the front stage to the next stage, so that the effect of having a short delay with the addition of fewer circuits is obtained.

Claims (3)

2 ^N bits in the normalization circuit of the (n is an odd number) when, 2 ^N to the upper 2 ^N-2 eseo sequence of bits are compared to the applied high order bits of the end and then only the zero output (Sn- _1, Sn- ₂₎ ^-2 and two levels of zero-bit detector (1A-1), the two ^N-2, 2-bit zero level detector (1A-a) output signal (Sn- _1, Sn- ₂₎ for each stage selection (Sn- ₁ of _, Sn- ₂₎ when receiving a zero top 2 ^N-1 bits or the upper 2 ^N-2 bit 2 to a left to shift the ^N-1 and 2, ^N-2-bit left shifter (2A-1, 2B-1 ) and And a 1-bit zero detector 1N-1 comparing the application of the 1-bit string to zero by the inverter Im and outputting it through the inverter In, and the 1-bit zero detector 1N-1. And a 1-bit left shifter (2N-1) for shifting the high order 1 bit by FP shifting the output signal (So) of the input signal to the selection terminal (So). In a normalization circuit when 2 ^N bits (n is even), 2 (Sn- ₁ , Sn- ₂ ) are output by comparing whether the current or next higher bit in the string of 2 ^N-2 bits is zero. and ^N-2 bit 2-level zero detector (1A-2), the second ^N-2 bit 2-level zero detector (1A-2) output signal (Sn- _1, Sn- ₂₎ the end of each selection (Sn- ₁ , Sn- ₂ ) 2 ^N-1 and 2 ^N-2 bit left shifter (2A-2,2B-2) which left and shifts the upper 2 ^N-1 bit or upper 2 ^N-2 bit if it is zero And a one-bit two-level zero detector (1N-2) that compares whether the current and next bits are zero in the string of upper one bits and outputs (S _1, So), and the one-bit two-level zero detector ( 2-bit and 1-bit left shifter (2M-2,2N) that receives the output signals (S1, SO) of 1N-2) from the selection terminals (S1, S0) and shifts the upper two bits or the upper one bit by shifting it to zero. -2) normalization times, characterized in that . According to 2, wherein the second level zero detector comprises an input terminal (is _1), which determines the zero of the upper 2 ^N-2 bits of the first NOR gate (NR11), and then the input stage (is _{²⁾ 2 ^N-2} bits in the A second NOR gate NR12 for discriminating zero, a third NOR gate NR13 for discriminating zero of the upper 2 ^N-2 bits at the next input terminal is ₃ , and the second and third NOR gates NR12 The output of the first and third NOR gates NR11 and NR13 is input to the NAND gate ND11 for determining the zero of the current stage by the output of NR13 and outputting the output S1 through the inverter I11. And a multiplexer (MUX) for discriminating the next stage zero by the output of the NAND gate ND11 input to the selection terminal S as D1, and outputting it through the inverter I12. Normalization circuit.