KR20010111668A - A Digital Modulation/Demodulation Method and System - Google Patents

Abstract

The present invention transmits digital data obtained by sampling sinusoidal signals using the principle of processing gain used in spread spectrum communication to enable reliable communication even in a poor channel environment.

The modulation system of the present invention includes a digital signal generator, a multiplier and a D / A converter.

The digital signal generator samples the sinusoidal signal having the first symbol period for each symbol period in synchronization with the sampling frequency clock signal and outputs the sampled value as a digital signal. A multiplier multiplies the data value having the same magnitude as the first symbol period by the output value of the digital sinusoidal signal generator. The D / A converter modulates the digital signal output from the multiplier into an analog signal.

Description

Digital Modulation / Demodulation Method and System

The present invention relates to a digital modulation and demodulation method and system, and more particularly, to a digital modulation and demodulation method and system for enabling reliable communication even in a very poor channel environment such as a power line.

Recently, there has been a growing interest in home networks and subscriber networks using power lines. However, home networks and subscriber networks using such power lines are very poor in channel environment, and there are many difficulties in practical use.

Home network simply means that all the PCs and home appliances in the house are organized into one network. The home network can be divided into two types, wireless and wired. Home RF (radio frequency) and Bluetooth (bluetooth) correspond to the former, and the latter use the telephone line and the power line. do.

In the case of a home network using power lines, it is easier to construct a home network because the power lines are more evenly distributed in the house than any other, but it is not easy to develop a system using the power lines due to the poor channel environment of the power lines.

Power line channels have the following problems.

First, since the power line generally has a random tree structure in the house, when the frequency increases, the influence of the reflected wave generated by the impedance mismatch cannot be ignored.

Second, the power line changes the overall load impedance depending on the operation of home appliances and lighting devices in the house, which means a change in signal level and causes performance degradation.

Third, because of devices that affect power lines, such as refrigerators and fans, power lines are always full of noise, surge, and tone jamming signals that correspond to harmonics of AC power. Because of this, most power line channels in a home have a very bad signal-to-noise ratio.

In order to construct a home network using such a power line channel, the conventional system has largely used the following modulation and demodulation method.

First is analog frequency shift keying (FSK).

This method is very simple to implement and is mainly used for low speed systems. However, it is an optimal solution for high speed power line channels because the minimum signal-to-noise ratio needs to be about 10dB at the receiving end for low frequency efficiency and demodulation. Can't.

Second, DPL (Digital Power Line) modem technology. This is a technology that directly transmits the square wave of the Ethernet standard, and the transmission distance is limited due to the dispersion of the square wave with distance. This method is inadequate where the noise is greater than the signal, since the waveform itself can only be seen by the receiver when the minimum signal is greater than the noise in the powerline channel. In addition, this method uses an equalizer to compensate for distortion at the receiving end. The higher the speed, the higher the cost and difficulty of implementing the equalizer.

On the other hand, even though the above two methods transmit signals with a very high signal-to-noise ratio, it is difficult to build a reliable network because the signal itself is not only small but also buried in noise due to the characteristics of the power line channel mentioned above. Therefore, there is no system that transmits high-speed data using power lines in the home yet.

The present invention is to solve the above problems, the present invention is to provide a new modulation and demodulation method and system to overcome the poor channel environment, such as the power line channel mentioned above.

Another object of the present invention is to provide a modulation and demodulation method and system for recovering a signal even in a situation where a signal is buried in noise, thereby enabling reliable communication even in a poor channel environment.

1 is a diagram illustrating the principle of the present invention.

2A and 2B show that the bit energy-to-noise ratio is greater than the signal-to-noise ratio according to an embodiment of the present invention.

3 is a diagram illustrating an example of a sinusoidal signal used in an embodiment of the present invention.

4 is a diagram showing an example of a signal arrangement of a sine wave signal used in the embodiment of the present invention.

Fig. 5 shows a plurality of sinusoidal signals used in the embodiment of the present invention in the frequency domain.

6 is a diagram illustrating an example of frequency components having orthogonality.

7 is a diagram showing an example of a modulation system according to the first embodiment of the present invention.

8 and 9 are timing diagrams and signal diagrams of the modulation system of FIG. 7, respectively.

10 is a diagram showing an example of a demodulation system according to the first embodiment of the present invention.

11 is a diagram showing an example of a modulation system according to the second embodiment of the present invention.

12 is a diagram illustrating an example of a QAM generator of a modulation system according to a second embodiment of the present invention.

FIG. 13 shows a signal diagram of the QAM generator of FIG.

Modulation system according to one aspect of the present invention for achieving the above object is

A digital sine wave signal generator for sampling a sine wave signal having a first symbol period for each symbol period in synchronization with a sampling frequency clock signal and outputting the sampled value as a digital signal; A multiplier for multiplying a data value having the same magnitude as the first symbol period by an output value of the digital sinusoidal signal generator; And a D / A converter for modulating the digital signal output from the multiplier into an analog signal.

On the other hand, the demodulation system according to one aspect of the present invention

An A / D converter converting the received analog signal into a digital signal; A correlator for correlating one data symbol output from the A / D converter with a sinusoidal signal; A sampler sampling a value output from the correlator in units of data symbol intervals; And a comparison block that determines a sampled data value by comparing the value output from the sampler with a reference value.

On the other hand, the modulation system according to another aspect of the present invention

A serial-to-parallel converter for converting serially input input data bits into N parallel data; After receiving N parallel data output from the serial-to-parallel converter, and generating sinusoidal signals corresponding to a plurality of frequencies having orthogonality to each other to generate sampled digital data for each input data for each symbol section. N digital signal generators for outputting; A synthesizer for synthesizing digital data respectively output from the N digital signal generators; And a D / A converter for converting digital data output from the synthesizer into an analog signal.

On the other hand, the digital modulation method according to an aspect of the present invention

A first step of sampling a sinusoidal signal having a first symbol period for each symbol period in synchronization with a sampling frequency clock signal and outputting the sampled value as a digital signal; A second step of multiplying a data value having the same size as the first symbol period by a digital signal output in the first step; And a third step of modulating the digital signal output in the second step into an analog signal.

On the other hand, the digital modulation and demodulation method according to another feature of the present invention

A first step of sampling a sinusoidal signal having a first symbol period for each symbol period in synchronization with a sampling frequency clock signal and outputting the sampled value as a digital signal; A second step of multiplying a data value having the same size as the first symbol period by a digital signal output in the first step; A third step of modulating and transmitting the digital signal output in the second step into an analog signal; A fourth step of receiving the analog signal transmitted in the third step and converting the analog signal into a digital signal; A fifth step of correlating one data symbol converted in the fourth step with a sinusoidal signal; A sixth step of sampling the value correlated in the fifth step in data symbol interval units; And a seventh step of determining the sampled data value by comparing the value sampled in the sixth step with a reference value.

Here, the fifth step is

An eighth step of sampling a sine wave signal having a first symbol period in synchronization with a sampling frequency clock signal for each one symbol and outputting the sampled value as a digital signal; A ninth step of multiplying the digital signal output in the third step and the digital signal output in the eighth step; And a tenth step of accumulating and adding the digital signal output in the ninth step in one data symbol unit.

Hereinafter, with reference to the drawings will be described an embodiment of the present invention;

First, the principle of the modulation and demodulation method proposed by the present invention will be described. 1 is a view for explaining the principle of the present invention.

Assume a sinusoidal curve of one period as shown in FIG. If there are N Ts sample intervals during the sinusoidal period Tb, Tb = NTs. Here, one period Tb of the sine curve represents final data information, hereinafter referred to as a symbol. In addition, hereinafter, the number N of samples in one symbol is referred to as processing gain.

In Fig. 1, each sample value, although each has a different amplitude value, can be said to have an average Ec / 2 energy over the entire period. Thus, average amplitude = Becomes Therefore, if N such samples are integrated in the symbol period Tb, the value is N. Becomes If the noise power in such a sample signal Since the noise components added to each sample value are independent of each other, the total noise integrated during the symbol period Tb is Becomes Bit energy ( ) To noise ratio ( ) Is as shown in Equation 1 below.

It can be seen from Equation 1 that the larger the processing gain N, the larger the bit energy to noise ratio. This is the same principle of processing gain in spread spectrum communication.

However, the spread spectrum communication uses a pseudo noise (PN) code, and the use of a sinusoidal curve is different in the embodiment of the present invention. Specifically, in spread spectrum communication, a PN code is used not only for processing gain but also for diversity in a multipath channel using encryption and correlation characteristics. However, in an embodiment of the present invention, an encryption and multipath diver Since we don't use a concert, we don't use PN code, but we use a sine function.

As described above, according to the embodiment of the present invention, since the energy of one bit (symbol) is divided into several independent samples, even if a signal is buried in the channel, it is possible to recover sufficiently by using the processing gain at the receiving end. At this time, the processing gain is determined by how many samples are added in one bit interval.

2A and 2B are diagrams showing that the bit energy-to-noise ratio becomes larger than the signal-to-noise ratio due to the processing gain according to the embodiment of the present invention.

2A is a diagram illustrating a signal-to-noise ratio (S / N) at a receiving end, and FIG. ).

As can be seen from Figs. 2A and 2B, according to the embodiment of the present invention, even though the signal S is buried in the noise N at the receiving end, since the bit energy may be larger than the noise due to the processing gain, The signal can be fully recovered.

The following describes the use of the principles of the present invention described above in actual communication.

Since the present invention uses a value obtained by sampling a sinusoidal function (sinusoidal wave) as a transmission signal, as shown in FIG. 3, QPSK (quadrature phase shift keying) modulation having orthogonality or opposite signs from each other having the same frequency is shown. It can be implemented by applying the method. As shown in FIG. 3, when the QPSK modulation scheme is applied, two bits of information may be loaded in one sinusoidal symbol in coherent communication.

On the other hand, the modulation method of the present invention can carry information not only in phase but also in amplitude as shown in FIG. 4 shows a constellation of signals in the form of 16 QAM (quardrature amplitude modulation).

In addition, the modulation scheme of the present invention can be applied not only to QPSK and 16 QAM, but also to BPSK, 64 QAM, and 256 QAM according to channel conditions.

On the other hand, since the embodiment of the present invention uses a sinusoidal wave as a transmission signal, a plurality of frequency components having orthogonality to each other can be used in the frequency domain. 5 is a view showing sinusoidal signals of a plurality of frequencies f1, f2, f3 having orthogonality to each other used in the embodiment of the present invention in a frequency domain. It can be seen from FIG. 5 that each of the sinusoids f1, f2 and f3 has no orthogonality to each other during one symbol period, so that there is no interference. In FIG. 5, the sinc-type spectrum occurs due to frequency transitions as in QPSK in each symbol period.

As described above, the present invention may use a plurality of frequency components having orthogonality to each other. In this case, each frequency has a relationship as shown in Equation 2 below.

6 is a diagram illustrating an example of frequency components having orthogonality. Each frequency component shown in Fig. 6 is basically as large as n times the lowest frequency component.

Hereinafter, an example of a demodulation system implementing the principles of the present invention described above will be described.

First, the modulation system according to the first embodiment of the present invention will be described with reference to FIGS. 7 is a diagram illustrating a modulation system according to a first embodiment of the present invention, and FIGS. 8 and 9 are diagrams showing timing diagrams and signal diagrams of the modulation system of FIG. 7, respectively.

The modulation system according to the first embodiment of the present invention shows a binary phase shift keying (BPSK) system having a sampling frequency of 12 MHz and a period of data symbols of 100 kHz.

As shown in FIG. 7, the modulation system according to the first embodiment of the present invention includes a sampling clock signal generator 10, a digital sign generator 20, a multiplier 30, and a D / A converter 40. As shown in FIG.

The sampling clock signal generator 10 generates a clock signal having a sampling frequency of 12 MHz as shown in FIG. As shown in FIG. 9B, the digital sine generator 20 outputs a sine function having a data symbol period of 100 kHz in synchronization with the sampling clock signal as an n-bit digital signal. In this case, according to the first embodiment of the present invention, since the frequency corresponding to the data symbol period Tb is 100 KHz and the sampling clock frequency is 12 MHz, the number of samplings per data symbol period, that is, the number of processing gains is 120 (12 MHz / 100 KHz). That is, the number of samplings per symbol shown in B of FIG. 9 is 120.

9B illustrates a sample value output from the digital sign generator 20 for convenience of explanation, the sample value output from the digital sign generator 20 is n bits as shown in FIG. Is represented by a digital signal. In this case, 120 consecutive sample values form one symbol.

The multiplier 30 multiplies the digital sine value shown in B of FIG. 9 output from the digital sine generator 20 by a data bit value having a frequency of 100 KHz as shown in A of FIG. Output the values shown. 9C shows a sample value output from the multiplier 30 for the convenience of explanation, the sample value output from the actual multiplier 30 is represented by an n-bit digital signal.

The D / A converter 40 converts the digital signal output from the multiplier 30 into an analog signal.

FIG. 10 is a diagram showing a demodulation system corresponding to the modulation system of the present invention shown in FIG.

As shown in Fig. 10, the demodulation system according to the first embodiment of the present invention includes an A / D converter 50, a correlator 60, a sampler 70, and a decision block 80.

The A / D converter 50 converts the received analog signal into digital data. The correlator 60 includes a sine generator 62, a multiplier 64, and an accumulator 66 to correlate one data symbol output from the A / D converter with a sine value.

The sine generator 62 outputs a sample of a sine function having a data symbol period of 100 kHz, as in the digital sine generator 20 described with reference to Fig. 7, as an n-bit digital signal. The multiplier 64 multiplies the digital signal output from the A / D converter 50 with the signal output from the sine generator 62. The accumulator 66 accumulates and adds the signals output from the multiplier 64 in one data symbol unit.

The sampler 70 samples the value output from the accumulator 66 in the data symbol interval Tb and outputs the result to the decision block 80. The decision block 80 determines the sampled data value for each data symbol section based on the zero value.

The following describes the modulation system when using QAM and multicarrier by extending the modulation principle of the present invention.

11 is a diagram showing a modulation system according to a second embodiment of the present invention.

As shown in FIG. 11, the modulation system according to the second embodiment of the present invention includes a serial-to-parallel converter 100, a plurality of QAM generators 200a, 200b, and 200c, a synthesizer 300, and a D / A converter 400. It includes.

The serial-to-parallel converter 100 converts input data bits serially input in parallel and outputs them to each QAM generator. For example, assuming that each QAM generator 200a, 200b, 200c is a 16 QAM generator, each QAM generator will require 4 bits of input data. In this case, the serial-to-parallel converter 100 divides 12-bit input data inputted in series into 4 bits each (that is, converts them in parallel) and outputs them to each QAM generator.

The QAM generators 200a, 200b, and 200c generate and output sampled digital data for each input data for each symbol section by using sinusoidal signals having frequencies f1, f2, and f3 having orthogonality to each other. .

The summer 300 synthesizes and outputs sampled digital data output from each QAM generator. The D / A converter 400 converts digital data output from the synthesizer into an analog signal and outputs the analog signal.

FIG. 12 is a diagram illustrating a 16 QAM generator, which is an example of the QAM generator of FIG. As shown in FIG. 12, the QAM generator according to the embodiment of the present invention includes a digital sine generator 230, a digital cosine generator 250, a sine amplitude lookup table 220, a cosine amplitude lookup table 210, and a first one. And second multipliers 240 and 260 and adders 270.

Since 16 QAMs have one symbol of four bits, four bits of data are input from the serial-to-parallel converter 100. At this time, the first two bits Bit 0 and Bit1 of the four input bits are used to determine the amplitude of the sine curve, and the second two bits Bit2 and Bit3 are used to determine the amplitude of the cosine curve.

The sine amplitude lookup table 220 and the cosine amplitude lookup table 210 output amplitude values corresponding to two bits of data, respectively. For example, the sine amplitude lookup table 220 outputs amplitude values having sizes 3, 1, and -3, respectively, when two bits of input data are 00, 01, and 10 as shown in FIG. 13A. .

The digital sine generator 230 and the digital cosine generator 250 output the sampled values of the sine and cosine curves having the frequency f1 as n-bit digital signals. In this case, the number of samplings is determined as a value obtained by dividing the sampling clock frequency by the frequency corresponding to the symbol period, as described with reference to FIG. 7. 13B shows a signal output from the digital sign generator 230. 13B illustrates a sample value output from the digital sign generator 230 for convenience of description, but the sample value output from the digital sign generator 230 is represented by an n-bit digital signal.

The first multiplier 240 outputs a value obtained by multiplying the output value of the sine amplitude lookup table 220 by the output value of the digital sine generator 230, and likewise, the second multiplier 260 outputs the cosine amplitude lookup table 210. A value obtained by multiplying the output value by the output value of the digital cosine generator 250 is output. C of FIG. 13 illustrates a signal output from the first multiplier 240. The adder 270 sums output values output from the first and second multipliers 240 and 260.

Next, the frequency efficiency of the modulation system according to the second embodiment of the present invention will be described. For example, suppose that the symbol interval is 1/100 kHz, and 16 QAM using four frequencies of 100 KHz, 200 kHz, 300 kHz, and 400 kHz. If the sampling frequency at the receiver is 32 MHz, the processing gain is 32000/100 = 320 = 25 [dB]. In addition, the frequency efficiency is (1.6 Mbps / 400 kHz) = 4 bit / s / Hz because the frequency band up to 400 kHz is used and four frequency components with 4 frequency components each use 100 kHz symbols. . This is much more efficient than traditional analog FSK. If you use more frequency components or more amplitude levels, the frequency usage efficiency will be even higher.

In the above, embodiments of the present invention have been described in detail, but the present invention may be variously modified or modified in addition to the above embodiments.

For example, the modulation method and system described in the embodiment of the present invention can be used in the subscriber network power line channel and the telephone line channel in addition to the power line channel constituting the home network, and can also be used in various other channels.

In addition to the BPSK, QPSK, and QAM methods, the present invention can also be used in a communication method using a sine wave.

As described above, according to the modulation and demodulation method of the present invention, using the principle of the processing gain used for spread spectrum communication, even if a signal is buried in noise, it can be recovered by this processing gain, so that reliable communication is performed in a poor power line channel. This is possible.

In addition, since the present invention does not require the use of an equalizer in the transmitting FIR filter and the receiving end, the present invention has a simpler implementation than the conventional method.

In addition, the present invention enables high-speed data transmission in a low frequency band because the frequency efficiency is very good.

Claims (16)

A digital sine wave signal generator for sampling a sine wave signal having a first symbol period for each symbol period in synchronization with a sampling frequency clock signal and outputting the sampled value as a digital signal; A multiplier for multiplying a data value having the same magnitude as the first symbol period by an output value of the digital sinusoidal signal generator; And And a D / A converter for modulating the digital signal output from the multiplier into an analog signal. The method of claim 1, And a clock signal generator for generating said sampling clock signal. The method of claim 1, And wherein the first symbol period coincides with a period of the sinusoidal wave. The method according to any one of claims 1 to 3, And a frequency of the sampling clock signal is greater than a frequency of the sinusoidal signal. An A / D converter converting the received analog signal into a digital signal; A correlator for correlating one data symbol output from the A / D converter with a sinusoidal signal; A sampler sampling a value output from the correlator in units of data symbol intervals; And And a comparison block for comparing a value output from the sampler with a reference value to determine a sampled data value. The method of claim 5, The correlator A digital sine wave signal generator for sampling a sine wave signal having a first symbol period in synchronization with a sampling frequency clock signal for each one symbol and outputting the sampled value as a digital signal; A multiplier for multiplying the digital signal output from the A / D converter and the digital signal output from the digital sine wave signal generator; And And a accumulator for accumulating and adding the digital signals output from the multiplier by one data symbol unit. A serial-to-parallel converter for converting serially input input data bits into N parallel data; After receiving N parallel data output from the serial-to-parallel converter, and generating sinusoidal signals corresponding to a plurality of frequencies orthogonal to each other to generate sampled digital data for each input data for each symbol section. N digital signal generators for outputting; A synthesizer for synthesizing digital data respectively output from the N digital signal generators; And And a D / A converter for converting the digital data output from the synthesizer into an analog signal. The method of claim 7, wherein And the digital signal generator outputs the sampled digital data using one sine function. The method of claim 7, wherein And the digital signal generator outputs sampled digital data using a sine function and a cosine function having the same amplitude. The method of claim 7, wherein And the digital signal generator outputs sampled digital data using a sine function and a cosine function having different amplitudes. The method of claim 10, The digital signal generator A digital sine generator for outputting a digital signal sampled from a sine function; A digital cosine generator for outputting a digital signal obtained by sampling a cosine function having the same frequency as the sine function; A sine amplitude lookup table for outputting an amplitude value corresponding to an upper (or lower) bit of data input from the serial-to-parallel converter; A cosine amplitude lookup table for outputting an amplitude value corresponding to a lower (or higher) bit of data input from the serial-to-parallel converter; A first multiplier for multiplying an output value of the sine amplitude lookup table with an output value of the digital sine generator; A second multiplier that multiplies an output value of the cosine amplitude lookup table by an output value of the digital cosine generator; And And an adder for adding output values of the first multiplier and the second multiplier. A first step of sampling a sinusoidal signal having a first symbol period for each symbol period in synchronization with a sampling frequency clock signal and outputting the sampled value as a digital signal; A second step of multiplying a data value having the same size as the first symbol period by a digital signal output in the first step; And And a third step of modulating the digital signal output in the second step into an analog signal. The method of claim 12, And wherein the first symbol period coincides with a period of the sinusoidal wave. The method according to claim 12 or 13, And the frequency of the sampling clock signal is greater than the frequency of the sinusoidal signal. A first step of sampling a sinusoidal signal having a first symbol period for each symbol period in synchronization with a sampling frequency clock signal and outputting the sampled value as a digital signal; A second step of multiplying a data value having the same size as the first symbol period by a digital signal output in the first step; A third step of modulating and transmitting the digital signal output in the second step into an analog signal; A fourth step of receiving the analog signal transmitted in the third step and converting the analog signal into a digital signal; A fifth step of correlating one data symbol converted in the fourth step with a sinusoidal signal; A sixth step of sampling the value correlated in the fifth step in data symbol interval units; And And a seventh step of determining a sampled data value by comparing the value sampled in the sixth step with a reference value. The method of claim 15, The fifth step is An eighth step of sampling a sine wave signal having a first symbol period in synchronization with a sampling frequency clock signal for each one symbol and outputting the sampled value as a digital signal; A ninth step of multiplying the digital signal output in the third step and the digital signal output in the eighth step; And a tenth step of accumulating and adding the digital signals output in the ninth step in units of one data symbol.