KR20010109958A - Method of fabricating via hole for copper wiring of semiconductor device - Google Patents

Abstract

A method of forming a via hole for copper wiring of a semiconductor device is disclosed. One aspect of the present invention forms an etch termination barrier layer covering a lower copper wiring on a semiconductor substrate. An insulating layer having a trench is formed on the etching termination barrier layer. A photoresist pattern is formed on the insulating layer to expose the bottom of the trench. The bottom of the trench exposed by the photoresist pattern is selectively first etched using the surface of the etch stop barrier layer as an etch stopper to form via holes. The surface of the lower copper interconnection is protected by being exposed to the etching termination barrier layer, and the first polymer layer generated by the photoresist pattern and the first dry etching is removed using an oxygen plasma. A portion of the etching termination barrier layer exposed by the via hole is removed by a second dry etching using a fluorocarbon plasma to expose the surface of the lower copper wiring. The semiconductor substrate is maintained at about 100 ° C. or less and an oxygen plasma is used to remove the second polymer layer generated by the second dry etching.

Description

Method for fabricating via hole for copper wiring of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method of forming via holes for copper (Cu) wiring.

As semiconductor devices become highly integrated and high-speed operation, attempts have been made to introduce copper wiring. Copper wiring is mainly made by patterning using a damascene process, and interconnection between copper wirings is also performed by a via hole process accompanying the damascene process.

Unlike conventional aluminum (Al), copper wiring exhibits properties that are susceptible to diffusion and oxidation of copper. Therefore, when performing the via hole process involving the damascene process, it is necessary to secure an etching process and a process related thereto that can overcome the above-mentioned weakness of diffusion and oxidation.

In order to prevent diffusion and oxidation of copper in the via hole process, damascene process, and the like, a barrier layer is introduced on the surface of the lower copper wiring patterned by the damascene process. In addition, an insulating layer is introduced on the barrier layer, and a via hole for exposing the lower copper wiring through the trench, the trench bottom, and the barrier layer is formed by dry etching.

However, such a dry etching process is performed to expose the surface of the lower copper interconnection described above, which may cause damage by ion sputtering on the exposed surface of the lower copper interconnection. In particular, as described above, since the copper wiring has a property that is vulnerable to oxidation, a defect in which the surface of the lower copper wiring is seriously oxidized may occur in addition to the above damage.

In addition, since the photoresist pattern is introduced into the dry etching process as the etching mask, a strip process for removing the photoresist pattern after forming the via hole is required. This stripping process includes removing a polymer generated during the dry etching process. The strip process may be performed using an existing high temperature oxygen plasma of about 250 ° C. or more, but in this case, a defect may occur in which the surface of the exposed lower copper wiring is very rapidly oxidized.

In order to prevent this, the strip may be performed by a wet process using an organic chemical solution. However, since the wet process must use a separate device from the dry etching process for forming the via hole, it is impossible to perform the wet process in-situ in association with the dry etching process. Accordingly, a defect such as oxidization of the exposed lower copper interconnection may occur between the dry etching process and the stripping process by the wet process.

In addition, the strip using the above wet process may generate an under cut in the via hole. This undercut may act as a cause of a filling failure in the upper copper wiring forming process of filling the via holes. In detail, in order to form the upper copper wiring, a step of forming a barrier metal layer and then forming a copper seed layer is involved. At this time, the barrier metal layer or the seed layer is disconnected by the undercut, and the upper copper wiring formed by electroplating or the like on the seed layer is not grown in the disconnected portion. Therefore, a failure may occur in which the upper copper wiring is not filled in the disconnected portion.

SUMMARY OF THE INVENTION A technical problem to be solved by the present invention is to prevent undercuts from occurring in via holes and to prevent damage or oxidation from occurring on the surface of the exposed lower copper wirings, thereby ensuring a via resistance of the copper wirings. The present invention provides a method for forming a via hole for copper wiring.

1 to 6 are cross-sectional views schematically illustrating a method of forming a via hole for copper wiring of a semiconductor device according to an exemplary embodiment of the present invention.

<Brief description of the major symbols in the drawings>

10; Semiconductor substrate, 20; Bottom insulation layer,

31; Barrier metal layer, 35; Bottom copper wiring,

40; Etching termination barrier layer, 50; Insulation Layer,

55; Trench, 57; Via Hole.

One aspect of the present invention for achieving the above technical problem is to form an etch termination barrier layer covering a lower copper wiring on a semiconductor substrate. An insulating layer having a trench is formed on the etching termination barrier layer. A photoresist pattern exposing the bottom of the trench is formed on the insulating layer. A first dry etching is selectively performed using the bottom of the trench exposed by the photoresist pattern using the surface of the etch termination barrier layer as an etch termination point to form a via hole. The surface of the lower copper interconnection is prevented and exposed to the etch stop barrier layer, and the photoresist pattern and the first polymer layer generated by the first dry etching are removed using an oxygen plasma. A portion of the etching termination barrier layer exposed by the via hole is removed by a second dry etching using a fluorocarbon plasma to expose the surface of the lower copper wiring. The semiconductor substrate is maintained at about 100 ° C. or less and an oxygen plasma is used to remove the second polymer layer generated by the second dry etching.

Here, the insulating layer is made of silicon oxide, and the etch finish barrier layer is made of silicon nitride or silicon carbide having an etching selectivity with the insulating layer. In addition, the first dry etching is C _x F _y (x, y is an integer) system having a C / F ratio of at least 0.3 or more of the group consisting of C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₈ and C ₅ F ₈ to any one of the gas or the C _x F _y type gas selected from the gas CH ₂ F ₂ and CH ₃ F any one of the gas or, is selected from the group of CH _x F _y type gas consisting of CO, O _2, It is carried out using a gas in which N ₂ or Ar gas is mixed as a reaction gas. The second dry etching is performed without applying a bias to the back surface of the semiconductor substrate by using a reaction gas including CHF ₃ or CF ₄ or a reaction gas added with CO to the reaction gas.

According to the present invention, the occurrence of undercut in the via hole can be suppressed, and damage or oxidation can be prevented from occurring on the surface of the lower copper wiring exposed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. In addition, where a layer is described as being "on" another layer or semiconductor substrate, the layer may exist in direct contact with the other layer or semiconductor substrate, or a third layer therebetween. May be interposed.

1 to 6 are cross-sectional views schematically illustrating a method of forming a via hole for copper wiring of a semiconductor device according to an exemplary embodiment of the present invention.

1 schematically illustrates a step of forming a trench 55 in an insulating layer 50 on a semiconductor substrate 100.

Specifically, after forming the lower insulating layer 20 on the semiconductor substrate 100, the lower copper wiring 35 is formed using a damascene process. In detail, after the trench is formed in the lower insulating layer 20, a copper layer filling the trench is applied and planarized by CMP (Chemical Mechanical Polishing) or the like to form the lower copper wiring 35 limited to the trench. . At this time, at the interface between the lower copper wiring 35 and the lower insulating layer 20, a barrier such as tantalum nitride (TaN) to prevent diffusion of copper into the lower insulating layer 20 made of silicon oxide (SiO ₂ ) or the like. The metal layer 31 is introduced.

An etch termination barrier layer 40 is formed on the lower copper interconnection 35 and on the exposed lower insulating layer 20. The etching termination barrier layer 40 may be made of an insulating material capable of preventing copper diffusion, for example, a non-silicon based insulating material such as silicon carbide (SiC) or silicon nitride (SiN). The etch stop barrier layer 40 may be formed by chemical vapor deposition in a plasma enhanced manner.

Thereafter, an insulating layer 50 is formed on the etch stop barrier layer 40. The insulating layer 50 is formed of an insulating material such as silicon oxide, for example, a TEOS (TetraEthylOrthoSilicate) film. The trench 55 is formed in the insulating layer 50 to be aligned with the lower copper wiring 35. Such a trench may be performed by an optional etching process such as a photolithography process. The trench 55 is introduced to form the upper copper wiring by applying a damascene process.

2 schematically illustrates forming a photoresist pattern 60 exposing the bottom of trench 55.

Specifically, after the photoresist is applied on the insulating layer 50 on which the trench 55 is formed, a photoresist pattern 60 exposing the bottom of the trench 55 is formed by a photo development process. The photoresist pattern 60 is formed such that the exposed portion is aligned with the lower copper wiring 35.

3 schematically illustrates a step of forming the via hole 57 using the photoresist pattern 60 as an etch mask.

Specifically, the first dry etching of a portion of the insulating layer 50 forming the bottom of the trench 55 exposing the photoresist pattern 60 as an etching mask is performed. The first dry etching is performed by using the etching termination barrier layer 40 under the insulating layer 50 as the etching termination. Accordingly, the first dry etching is performed to have an etching selectivity between silicon oxide constituting the insulating layer 50 and silicon nitride or silicon carbide constituting the etch stop barrier layer 40.

For example, the first dry etching is performed using an plasma excited by a fluorinated carbon (C _x F _y ; x, y is an integer) gas having a high C / F ratio. It is preferable that the ratio of C / F is at least 0.3 or more, and examples of the C _x F _y -based gas having a high C / F include C ₂ F ₆ , C ₃ F ₈ , C ₄ F _8, or C ₅ F ₈ . Can be mentioned. In addition, the first dry etching may be performed using a plasma excited from a reaction gas in which a hydrogen fluoride carbon (CH _x F _y ) gas is further included in the C _x F _y gas having a high C / F ratio. . At this time, examples of the CH _x F _y -based gas include CH ₂ F ₂ or CH ₃ F. In addition, plasma excited by the reaction gas in which any one of oxygen gas (O ₂ ), nitrogen gas (N ₂ ), carbon monoxide gas (CO), and argon gas (Ar) is further mixed with the C _x F _y- based gas. May be used for the first dry etching. In addition, a plasma excited from the reaction gas in which the above gases are variously mixed may be used for the first dry etching.

As described above, the first dry etching using the plasma excited from the reaction gas containing the high C / F ratio C _x F _y -based gas is applied to the silicon nitride or silicon carbide forming the etching termination barrier layer 40. In contrast, the silicon oxide forming the insulating layer 50 is allowed to be etched with a high selectivity.

Therefore, the first dry etching uses the etching termination barrier layer 40 as the etching termination of the insulating layer 50 using the selectivity ratio of the etching termination barrier layer 40 as described above. That is, the first dry etching is performed such that the etching is terminated on the surface of the etching termination barrier layer 40. Accordingly, when the first dry etching is performed, the surface of the lower copper wiring 35 is not exposed to the reactive gas or plasma used for the first dry etching. Therefore, the surface of the lower copper wiring 35 can be prevented from being damaged by the first dry etching. Via holes 57 are formed in the insulating layer 50 by the first dry etching process.

In addition, since the first dry etching process uses the etching termination barrier layer 40 as the etching termination as described above, it is possible to prevent the polymer from being generated as a by-product by the first dry etching of the etching termination barrier layer 40. have. Therefore, since the by-product polymer by the first dry etching is mainly generated from the insulating layer 40, the absolute amount of the first polymer layer 65 by the adsorption of the polymer is reduced.

4 schematically illustrates the step of removing the remaining photoresist pattern 60.

Specifically, the photoresist pattern 60 remaining after being used in the first dry etching is stripped and removed. At this time, the strip is performed by high temperature ashing using oxygen plasma. For example, the photoresist pattern 60 may be ashed by using an oxygen plasma excited from a reaction gas containing oxygen gas or ozone (O ₃ ) at a high temperature of about 250 ° C.

In this case, the etching termination barrier layer 40 may cover and protect the lower copper wiring 35 from the oxygen plasma. Accordingly, the lower copper wiring 35 may be prevented from being oxidized or violated from the process of high temperature ashing the photoresist pattern 60. Meanwhile, by the stripping process of the photoresist pattern 60, the first polymer layer 65 generated in the first dry etching process may also be removed.

5 schematically illustrates removing the portion of the etch stop barrier layer 40 that is exposed.

In detail, the portion of the etch termination barrier layer 40 exposed by the via hole 57 is removed by performing second dry etching on the insulating layer 50 using an etching mask. This is to expose the surface of the lower copper wiring 35. Since the etch finish barrier layer 40 is made of silicon nitride or silicon carbide as described above, the etching termination barrier layer 40 is selectively subjected to second dry etching to have an etching selectivity with silicon oxide constituting the insulating layer 50.

For example, an etch termination barrier exposed using a plasma excited from a reaction gas comprising a hydrogen trifluoride carbon (CHF ₃ ) gas or a carbon tetrafluoride (CF ₄ ) gas or a reaction gas further comprising a CO gas to such gas. A portion of the layer 40 is etched using the surface of the lower copper interconnect 35 as the end of etching. In this case, the second dry etching process may be performed without minimizing or accelerating the acceleration of the plasma. For example, a very low bias power, such as a low bias power of less than approximately 500 W, is applied to the backside of the semiconductor substrate 10 or is performed without applying the bias power to the semiconductor substrate 10.

As described above, when the second dry etching is performed without applying the bias to the semiconductor substrate 10, the sputtering effect due to the ion acceleration effect due to the bias application can be suppressed, so that the lower copper is removed by the etching. Damage to the surface of the wiring 35 can be minimized. In addition, it is possible to minimize the loss of the insulating layer 50 by the above-described etching.

On the other hand, by removing the portion of the etching termination barrier layer 40 exposed by using the second dry etching process as described above, it is possible to suppress the occurrence of undercut in the via hole 57. When the above etching termination barrier layer 40 is removed by wet etching, the bottom edge of the via hole 57, that is, the portion adjacent to the etching termination barrier layer 40 is isotropic due to the isotropic etching characteristic of the wet etching. Etching can cause undercuts. However, since the second dry etching process is performed using the insulating layer 50 as an etching mask, the undercut is prevented by the characteristics of the dry etching process.

Since the occurrence of undercut is suppressed, when the barrier metal layer (not shown), copper seed layer (not shown), or upper copper wiring (not shown) or the like is formed on the via hole 57, the via hole ( 57, it is possible to prevent the filling failure that does not fill completely.

On the other hand, by the process of removing the etching termination barrier layer 40 as described above, the CF _x- based polymer which is the _by -product of the etching reaction may be adsorbed to generate the second polymer layer 45.

6 schematically illustrates a step of removing the second polymer layer 45.

Specifically, the second polymer layer 45 generated as described above is dry stripped by a low temperature ashing method using oxygen plasma. At this time, the dry strip method is performed in a state in which the temperature of the semiconductor substrate 10 is cooled to a low temperature of about 100 ° C. or less, preferably about −10 ° C. or less. In this case, when the dry strip method is performed using an induced coupled plasma (ICP) device, only the source power, that is, the power applied for plasma excitation, is applied to the semiconductor substrate 10. The bias power is zero.

As described above, when the second polymer layer 45 is ashed by using an oxygen plasma, the surface of the exposed lower copper wiring 35 is oxidized or damaged as compared to the ashing at a high temperature of about 250 ° C. It can be suppressed. In addition, since the second polymer layer 45 is generated only in the process of removing the exposed etch finish barrier layer 40 as described above, the absolute amount thereof is minimized. The exposed lower copper wiring 35 can be more suppressed from being oxidized or damaged.

Each process step described in the embodiment of the present invention as described above may be performed using a separate chamber (chamber), but because all of the dry process in-situ process in the same chamber sequentially Can be performed.

Meanwhile, after the via hole 57 is formed as described above, an upper copper wiring (not shown) may be further formed to fill the via hole 57. For example, after forming a barrier metal layer and forming a Cu seed layer, a copper layer is formed using an electroplating method. Thereafter, the copper layer may be planarized with CMP or the like to form an upper copper interconnection defined in the trench 55.

As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, It is clear that the deformation | transformation and improvement are possible by the person of ordinary skill in the art within the technical idea of this invention.

According to the present invention described above, the first dry etching for forming the via holes is performed using the surface of the etching termination barrier layer as the etching termination, and the surface of the lower copper wiring is protected by the remaining etching termination barrier layer and the first dry etching is performed. The photoresist pattern used for etching can be removed by ashing. Accordingly, the surface of the lower copper wiring can be prevented from being oxidized or damaged.

After the remaining etch stop barrier layer is removed by a second dry etch that minimizes or does not apply a bias to accelerate the plasma, the semiconductor substrate is cooled to a temperature of about 100 ° C. or less and generated in the second dry etch using an oxygen plasma. The prepared second polymer layer can be removed. Accordingly, the surface of the exposed lower copper wiring can be effectively prevented from being oxidized or damaged.

In addition, since all of the processes for forming the via holes do not use the wet process, it is possible to prevent the occurrence of undercuts in the via holes. Therefore, when forming the upper copper wiring filling the via hole, it is possible to prevent the occurrence of the via hole filling defect.

Claims (3)

Forming an etch stop barrier layer overlying the lower copper interconnect on the semiconductor substrate; Forming an insulating layer having a trench on the etch stop barrier layer; Forming a photoresist pattern exposing a bottom of the trench on the insulating layer; Forming a via hole by selectively dry etching the bottom of the trench exposed by the photoresist pattern using the surface of the etch finish barrier layer as an etch stop; Preventing and protecting the surface of the lower copper interconnection from being exposed to the etch stop barrier layer, and removing the photoresist pattern and the first polymer layer generated by the first dry etching using an oxygen plasma; Removing a portion of the etching termination barrier layer exposed by the via hole by a second dry etching using a fluorine carbide plasma to expose a surface of the lower copper wiring; And Removing the second polymer layer generated by the second dry etching using an oxygen plasma while maintaining the semiconductor substrate at about 100 ° C. or less. . The method of claim 1, wherein the first dry etching is Any one gas selected from C _x F _y -based gases having a C / F ratio of at least 0.3 or more comprising a group of C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₈ and C ₅ F ₈ , or To the C _x F _y type gas CH ₂ F ₂ and CH ₃ in the group consisting of F CH _x F _y type gas either a gas or, CO, O _2, N ₂ or a gas mixture of Ar gas is selected from A via-hole forming method for copper wiring of a semiconductor device, characterized in that carried out using the reaction gas. The method of claim 1, wherein the second dry etching is Via hole formation for copper wiring of a semiconductor device, characterized in that is performed without applying a bias to the back surface of the semiconductor substrate using a reaction gas containing CHF ₃ or CF ₄ or a reaction gas added with CO to the reaction gas Way.