KR20010106988A - Clock signal controling method of inter integrated circuit control device - Google Patents

Abstract

The method of controlling a serial clock signal in the internal integrated circuit control device disclosed herein automatically disables the generation of the serial clock signal after transmitting / receiving serial data. After reading the data stored in the data register, the generation of the serial clock signal is enabled. According to this method, the serial clock signal generation is automatically suppressed without depending on the interrupt signal. Therefore, bus control logic generates an enable level interrupt source signal to operate the IIC device, so that no separate control is needed to enable the control bits in the serial clock signal control register. Moreover, there is no problem of operating the IIC device in an interrupt disable state.

Description

CLOCK SIGNAL CONTROLING METHOD OF INTER INTEGRATED CIRCUIT CONTROL DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal integrated circuit control (ICC) device, and more particularly to a method of controlling a clock signal of an internal integrated circuit control device.

An IIC device is a module that supports two or more devices connected to a bus to transmit information using wires, that is, serial data (SDA) and serial clock signal (SCL).

Each of the IIC devices is identified by a unique address and acts as a transmitter or receiver over the wire. In addition, each of the IIC devices performs a transmitter or receiver operation as a master and a slave, where the master generates a serial clock signal (SCL) to initialize and synchronize data on the bus. Other devices perform operations as slabs.

In order for the master to pass information to the IIC device bus, the clock is generated by the serial clock signal (SCL), and the clock signal generated by each device is wired and connected to the serial clock signal (SCL). and) the synchronization of the clock signal is generated.

That is, the change from the high level to the low level of the serial clock signal SCL depends on the low level period of the associated IIC device, and the IIC device having the short low level period of the serial clock signal SCL is a serial clock signal. It enters the wait state of SCL and is affected by the IIC device with the longest low level period to generate a serial clock signal SCL.

Serial data SDA transmission and reception is performed after the generation of the serial clock signal SCL by the master while the start condition, that is, the serial clock signal SCL is at a high level, while the serial data SDA is at a high level to a low level. When transitioning to, the transmission and reception of the serial data SDA starts. The serial data SDA is transmitted and received in 8-bit units, and an acknowledgment bit is generated in succession so that the receiver informs the transmitter whether the serial data SDA is received.

Therefore, the receiver cannot receive serial data (SDA) while performing other operations. In this case, the serial clock signal (SCL) is kept at a low level so that the transmitter can transmit the serial data (SDA) while waiting for transmission. Make a reservation. When the transmission standby state of the transmitter is released, a serial clock signal is generated again and serial data SDA is transmitted.

As such, after the 8-bit data and the admission data are transmitted and received, the IIC interrupt is generated and the information transmitted / received is used. When an IIC interrupt is generated, the generation of the serial clock signal (SCL) is suppressed by the interrupt source so that the transmitted / received data remains unchanged in the data register of the IIC device.

1 is a block diagram showing a circuit configuration of a conventional IIC device.

Referring to FIG. 1, the IIC device includes a prescaler register 10, a serial output signal prescaler 20, a bus control logic 30, a shift data register 40, an address register 50, and a serial output signal control register ( 60) and a serial data control register 70.

The serial clock signal control register 60 includes control bits set by the interrupt source. The control bits of the serial clock signal control register 60 are enabled when the IIC device is in operation and disabled when an interrupt source is generated in the bus control logic 30.

If the IIC device is operated in the IIC interrupt disable state, the serial clock signal (SCL) is continuously generated even after 1 byte data transmission / reception, and the serial data transmitted / received is stored. This changes the value stored in the IIC data register, making the IIC module meaningless.

Therefore, there is a need for an IIC device in which a serial clock signal is not generated in an IIC interrupt disable state.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide an IIC device in which a serial clock signal is not generated after a transmission / reception operation is completed.

1 is a block diagram showing a circuit configuration of a conventional IIC device; And

2 is a block diagram showing a circuit configuration of an IIC device according to a preferred embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

110: prescaler register 120: serial output signal prescaler

130: bus control logic 140: shift data register

150: address register 160: serial clock signal control register

170: serial data control register

According to a feature of the present invention for achieving the object of the present invention as described above, a method for controlling a serial clock signal in an internal integrated circuit control device comprises: transmitting / receiving serial data, generating the serial clock signal. Disabling includes reading data stored in a data register, and enabling generation of the serial clock signal.

(Action)

In this way, an IIC device can be implemented in which the generation of the serial clock signal is automatically suppressed without depending on the interrupt signal.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Interrupts in an IIC device occur in three cases:

First, when the one-byte data transmission or reception operation ends,

Second, when a general call or slab address is matched, and

Third, when bus arbitration fails.

In the case described above, when an interrupt is generated, the generation of the serial clock signal SCL must be suppressed so that the transmitted / received serial data can be used in the main program.

In the present invention, a method for automatically suppressing serial clock signal generation without depending on the interrupt signal is provided.

2 is a block diagram showing a circuit configuration of an IIC device according to a preferred embodiment of the present invention.

Referring to FIG. 2, the IIC device includes a prescaler register 110, a serial output signal prescaler 120, a bus control logic 130, a shift data register 140, an address register 150, and a serial output signal control register ( 160 and serial data control register 170.

The serial clock signal control register 160 includes control bits set by an interrupt source. The control bits of the serial clock signal control register 160 are automatically disabled after sending / receiving serial data to disable the generation of the serial clock signal SCL. The user (programmer) reads the data stored in the serial data control register 70. Next, to enable the generation of the serial clock signal SCL, the control bit of the serial clock signal control register 60 is enabled.

Conventionally, bus control logic 130 generated an enable level interrupt source signal prior to operating the IIC device to enable control bits in serial clock signal control register 160. If the IIC device is operated in the interrupt disable state, the serial clock signal SCL is continuously generated even after transmitting / receiving 1-byte data, thereby changing the serial data SDA stored in the serial data control register 70. Because it becomes.

However, in the present invention, the serial clock signal SCL is not generated by automatically disabling the control bit of the serial clock signal control register 160 after transmitting / receiving 1 byte data. After the user reads and uses the state value stored in the serial clock signal control register 60, the serial data is continuously transmitted / received by enabling the control bit of the serial clock signal control register 160.

Therefore, bus control logic 130 generates an enable level interrupt source signal to operate the IIC device, so that no separate control is needed to enable the control bits in serial clock signal control register 160. Moreover, there is no problem of operating the IIC device in an interrupt disable state.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

According to the present invention as described above, the serial clock signal generation is automatically suppressed without depending on the interrupt signal. Therefore, bus control logic generates an enable level interrupt source signal to operate the IIC device, so that no separate control is needed to enable the control bits in the serial clock signal control register. Moreover, there is no problem of operating the IIC device in an interrupt disable state.

Claims (1)

A method of controlling a serial clock signal in an internal integrated circuit control device: Transmitting / receiving serial data; Disabling generation of the serial clock signal; Reading data stored in a data register; And Enabling the generation of said serial clock signal.