KR20010094695A - Digital frequency shift keying modulation apparatus having feedback structure in communication system - Google Patents

Abstract

PURPOSE: A digital frequency modulator with a feedback structure of a communication system is provided to realize CPFSK(Continuous Phase Frequency Shift Keying) by using Gaussian filtering and reduce the complexity by using a feedback structure. CONSTITUTION: The first register(103) is one-bit register and the second register(102) is two-bits register. Initial values of the first and the second registers(103,102) are 0, respectively. The second register(102) receives symbol data and buffers the received symbol data. The first register(103) and the second register(102) output buffered bits whenever the first symbol data are inputted into the second register(102). The bits are inputted into a logic portion(104) and the second logic portion. The logic portion(104) stores an output data lookup table for register output data and searches the output bits for the input bits from the output lookup table when three-bits data are received from the first and the second registers(103,102). The searched output bits for the input bits are outputted to the first register(103).

Description

DIGITAL FREQUENCY SHIFT KEYING MODULATION APPARATUS HAVING FEEDBACK STRUCTURE IN COMMUNICATION SYSTEM}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a digital frequency shift keying (GFSK) or Gaussian Filtered Minimum Shift Keying (GMSK) modulator, in particular a digital modulation device having a feedback structure. It is about.

In general, a method for performing digital modulation in a communication system includes a GFSK using a Gaussian filter, a GMSK, and a continuous phase frequency shift keying (CPFSK) modulation scheme. The GFSK or GMSK modulation is a modulation method that performs pulse shaping using a Gaussian filter, and is widely used in wireless communication systems such as WLAN, Home RF, Bluetooth, and GSM. . The CPFSK scheme includes a GMSK modulation scheme.

1 is a diagram showing the configuration of a general digital modulation device, which is a block diagram of an all-digital quadrature modulator for performing continuous phase frequency shift keying.

The all digital quadrature modulator is composed of a data formatter 120 and a digital modulator 140. The data formatter 120 receives the input data 201, the 1-bit clock and the M-bit clock, and arranges the input data in a predetermined format to output addressing data. The digital modulator 140 receives the formatted addressing data and digitally performs CPFSK modulation for output. The data formatter 120 includes a shift register 202, an up / down counter 206, and an interpolation counter 204, and the digital modulator 140 typically includes a numerically controlled oscillator 208 configured of a lookup table memory. And 210, 216, and 218, multipliers 212 and 214 and adder 222 for up-modulation.

The digital quadrature modulator requires bits that are overlapped for digital modulation. Therefore, the shift register 202 has a capacity of L bits capable of memory for several bit times, and shifts by one bit for each serial input data 201 input. Each time one bit of the serial data 201 is inputted, the L bit input data 201 buffered in the shift register 202 is output to the node 203. The L bit input data output from the shift register 201 is input to the first numerically controlled oscillator 208 and the second numerically controlled oscillator 210. The up / down counter 206 receives a bit value of the most significant bit from the shift register 202 as an up / down terminal, receives a clock of 1 bit, and outputs up / down information into 2 bits. 208 and the second numerical control oscillator 210. The interpolation counter 204 receives a clock of M bits and performs log M bit counting to output log M bits to the first and second numerically controlled oscillators 208 and 210. For example, with an input coupled at M = 16 times the clock frequency 1 / T, the log M bits would be 4 bits. The first numerically controlled oscillator 208 is composed of a cosine ROM that stores waveform values of the sampled cosine possible for T time, and according to the addressing data input from the formatter 120, an in-phase: Outputs the baseband modulated waveform value of the " I (t) " That is, the bits output from the shift register 202, the up / down counter 206, and the interpolation counter 204 are input to a predetermined format, and the waveform values stored in the address are read and output. The second memory 210 includes a sine ROM for storing sine waveform values sampled at T time intervals and is quadrature according to addressing data output from the formatter 120. Outputs the baseband modulated waveform value of the axis.

The carrier generation counter 220 receives a clock N times the carrier frequency and modulates the log N bits to modulate the desired frequency so that the log N bits are converted into the third numerical control oscillator 216 and the fourth numerical control oscillator 218. ) The third numerically controlled oscillator 216 is composed of a cosine ROM that stores in-phase waveform values of carrier waves sampled at T time intervals. Specifically, the third numerical control oscillator 216 receives the log N bits of data as addressing data, and reads and outputs a carrier in-phase waveform value in the address region. The fourth numerically controlled oscillator 218 is composed of a sine ROM which stores quadrature waveform values of a carrier sampled at T time intervals. In detail, the fourth numerically controlled oscillator 218 receives the log N-bit data as addressing data and reads and outputs a carrier quadrature waveform value stored at the address.

The first multiplier 212 multiplies the output of the first numerically controlled oscillator 208 by the output of the third numerically controlled oscillator 216 and outputs the multiplier 222 to the adder 222. The second multiplier 215 multiplies the output of the second numerically controlled oscillator 210 by the output of the fourth numerically controlled oscillator 218 and outputs the multiplier 222 to the adder 222. The adder 222 adds and outputs the output of the first multiplier 212 and the output of the second multiplier 214.

The output of the adder 222 is input to the D / A converter 250 to convert the up-modulated digital signal output from the digital modulator 140 into an analog signal. The signal converted into an analog signal by the D / A converter 250 is low-pass filtered through the low pass filter 254 and output as a CPFSK output signal.

The digital modulator may be implemented by a simple logic operation circuit including a plurality of counters and memories in implementing the continuous phase frequency shift modulator. There is a problem that a separate pulse shaping filter must be provided.

In addition, there is a problem in that it is difficult to obtain a constant filter characteristic required by the characteristics of the analog design.

Accordingly, an object of the present invention is to provide a digital modulation device having a simple hardware structure using a ROM that stores a simple lookup table when implementing continuous phase frequency shift modulation using a pulse shaping filter including a Gaussian frequency shift modulator.

Another object of the present invention is to provide a digital modulation apparatus having a simple hardware structure by constructing a simple look table using a feedback structure when implementing a Gaussian frequency shift modulation scheme.

In order to achieve the above object, the present invention provides a digital modulation device of a communication system, comprising: a second register having a plurality of shift registers and outputting the values of the respective shift registers in parallel for each symbol data input, and at least one shift; A first register having a register and receiving feedback data and outputting a value of each shift register each time the symbol data is input, and a lookup table having feedback data for continuously maintaining a waveform with respect to the input symbol data; A logic unit configured to receive the symbol data output from the first register and the second register, find feedback data of the symbol data in the lookup table, and output the feedback data to the first register; and a plurality of bits each time the symbol data is input. There are multiple samples Gaussian-filtered waveform values for the interpolation counters outputting the data, and address data configurable by the symbol data and sample data output from the first and second shift registers and the interpolation counter. And a memory for outputting the waveform value of the corresponding address when the address data is input, and a numerically controlled oscillator for receiving the waveform value and outputting in-phase and quadrature waveform values.

In order to achieve another object of the present invention, the present invention provides a digital modulation device of a communication system, comprising: a second register having a plurality of shift registers and outputting the values of the respective shift registers in parallel for each symbol data input; A lookup table having one or more shift registers and receiving feedback data and outputting a value of each shift register each time the symbol data is input, and a lookup table having feedback data for continuously maintaining a waveform with respect to the input symbol data. And a logic unit configured to receive symbol data output from the first register and the second register, find feedback data for the symbol data in the lookup table, and output the feedback data to the first register, and the first and second registers. Multiple symbol data that can be input from the register And a lookup table having a size of each of the plurality of symbol data, and information indicating whether the data is a negative waveform or a positive waveform and having the same magnitude when the symbol data is a negative waveform. A second logic unit for converting the symbol data into a positive waveform having the positive waveform and outputting the same together with the first selection signal, and outputting the symbol data together with the second selection signal in the case of the positive waveform; An interpolation counter for outputting a plurality of pieces of sample data consisting of four bits, and respective Gaussians for address data that may be configured by symbol data and sample data that can be output from the second logic unit and the interpolation counter. Saves the filtered waveform values and outputs the waveform values of the corresponding address when the address data is input. A memory to receive the waveform value and output the negative waveform value, a waveform value output from the memory and a waveform value output from the inversion part, and according to the first and second selection signals. And a selector for selecting and outputting any one, and a numerically controlled oscillator for receiving the selected waveform values and outputting in-phase and quadrature waveform values.

1 is a block diagram of a general modulation device.

2 is a block diagram of a modulation device according to a first embodiment of the present invention;

3 is a waveform diagram of a Gaussian filtered signal according to a first embodiment of the present invention;

4 is a block diagram of a modulation device according to a second embodiment of the present invention;

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in adding the reference numerals to the components of each drawing, the same components have the same reference numerals as much as possible even if displayed on different drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

2 is a block diagram illustrating a modulation device of a communication system according to a first embodiment of the present invention, and shows a configuration of a baseband modulation device in which an upconversion unit, a D / A converter, and the like are omitted.

Referring to FIG. 2, the digital modulation device according to the present invention includes a first register 103, a second register 102, a logic unit 104, a memory 111, an interpolation counter 106, and numerical values. A control oscillator (Numerically Control Oscillator: NCO) 113 and the second NCO (116). The first register 103 is a 1-bit register, and the second register 102 is a 2-bit register. The initial values of the first register 103 and the second register 102 are "0". The second register 102 receives and buffers symbol data. Each time one symbol data is input into the second register 102, the first register 103 and the second register 102 output the buffered bits. The bits output from the first register 103 and the second register 102 are input to the logic unit 104 and the second logic unit 405. The logic unit 104 stores an output data lookup table for register output data, and outputs the output bit data for the input bits when 3-bit data is input from the first register 103 and the second register 102. The look-up table is searched for and output to the first register 103 at the next clock. As shown above, it can be seen that the first register 103, the second register 102, and the logic unit 104 have a feedback structure. The lookup table stored in the logic unit 104 is shown in Table 1 below.

Address value Feedback value 000 One 001 0 010 0 011 One 100 One 101 0 110 0 111 One

It can be seen that the 1-bit first register 103 is determined as the value of the next state according to the 3-bit register values of the entire first register 103 and the second register 102 in the previous state. This is determined by the waveforms stored in the memory 111 having eight forms as shown in FIG. That is, the size of the last sample of the waveform which may occur in the previous waveform stored in the memory 111 is indicated. This bit is used to maintain the continuous phase characteristics of the previous waveform and to determine the waveform at the next symbol timing. A waveform mapping corresponding to a three bit address value determined by the three bit registers of the first and second registers 103 and 102 is illustrated as an example in FIG. 3. Referring to FIG. 3, when Gaussian filtering is performed, all eight shapes, waveforms 305, waveforms 306, waveforms 308, waveforms 309, waveforms 310, and waveforms according to symbol intervals are used. 311, waveform 312, and waveform 313. It is an address bit input to 108, 109, 110 from the left most of each of the three bits. The bit input to 108 indicates the final magnitude of the previous waveform as mentioned above. For example, if A is 1, this value has three sizes: 1, 0, and -1. Since the filtered waveform has a continuous phase characteristic, since the waveform 309, the waveform 310, the waveform 312, and the waveform 313 cannot come after the waveform of 305, there is redundancy that never occurs. Therefore, if you use 1, 0, -1 to display the bits that indicate the size, but do not use 1 bit that displays only 0, 1, -110, -111, 100, 101 will never occur. However, if -100 and -101 are present and replaced with 100 or 101 which does not occur, only one bit of address bits can represent the optimal size of the previous waveform. In other words, change the value corresponding to the size of -1 to 1. This generated address updates the value of the 1-bit register representing the size at the next symbol clock, indicating ROM. That is, waveform 305, waveform 306, waveform 310 and waveform 313 end in zero magnitude, waveform 308 and waveform 309 are 1, waveform 311 and waveform 312 are- Ends with 1 -1 can be replaced with 1, so if the address value of 3 bits is 000, as shown in Table 1, the 1-bit register in the next symbol clock is 1, 001 is 0, 010 is 0, 011 is 1, 100 It is updated to 0 if 1, 101, 0 if 110, or 1 if 111.

The interpolation counter 106 outputs to perform log N (Log ₂ N) to the second down receives the sampling clock of N times the input clock frequency of the symbol data. For example, when the sampling frequency N is 4, the number of bits output from the interpolation counter is 2 bits. The values of two bits output from the interpolation counter 106 are "00", "01", "11", and "10".

The bits output from the interpolation counter 106 and the first and second registers 103 and 102 indicate an address of the first memory 111 in a predetermined format. The memory 111 stores and stores a level value of a waveform that may be generated by a predetermined method, and receives an address input from the first and second registers 103 and 102 and the interpolation counter 106. Outputs the level value of the waveform stored in. The arrangement order of bits output from the first and second registers 103 and 102 and the interpolation counter 106 is output from the interpolation counter 106 according to a method of storing and addressing the first memory 111. The bit may come first or later. For example, the value output from the interpolation counter is "00" and the bits output from the first and second registers 103 and 102 are 001. First, two bits output from the interpolation counter 106 are described. In the case of arranging first, store the first sampled waveform value of the 001 waveform at 00 001, and store the first sampled waveform value of the 001 waveform at 001 00 when the 2 bits are placed later. The waveform level values filtered and output from the memory 111 are input to the first numerically controlled oscillator 113 and the second numerically controlled oscillator 114. The first numerical control oscillator 113 stores a look-up table that stores cosine waveform sample values according to possible waveform level values, and stores the cosine waveform sample values corresponding to the waveform level values filtered from the memory 111. Output The second numerical control oscillator 112 stores a lookup table that stores sine waveform sample values according to possible waveform values, and outputs a sine waveform sample value corresponding to the filtered waveform level value from the memory 111. do.

Values output from the first and second numerically controlled oscillators 113 and 112 are input to the multipliers 212 and 214 of FIG. Since the carrier modulation configuration and operation are the same as those in FIG. 1, description thereof will be omitted.

FIG. 4 is a block diagram illustrating a digital modulation device according to a second embodiment of the present invention. In the embodiment of FIG. 2, the second logic unit 405, the inverting unit 403, and the selector 404 are provided. Has an added structure. The second embodiment of the present invention has a structure for further simplifying the lookup table stored in the memory 111.

Hereinafter, referring to FIG. 4, the eight waveforms shown in FIG. 3 have a negative magnitude and a positive magnitude, except that the magnitudes are exactly the same except that the magnitudes are the same.

The second logic unit 405 has a table of positive symbol data having the same size as that of 3 bits of symbol data representing a negative waveform, and the first register 103 and the second register 102. 3 bits of symbol data are received from the apparatus, and it is determined whether the input 3-bit symbol data is a negative waveform or a positive waveform. If the input 3-bit symbol data is a negative waveform, the same magnitude as that of the negative waveform is read and output from the table, and if it is a positive waveform, it is output as it is. The second logic unit 405 converts the positive waveform into a positive waveform and outputs the first selection signal "1" or "0" to the selector 404 when outputting the negative waveform. Outputs a second selection signal " 0 " or " 1 "

On the contrary, the second logic unit 405 may convert the negative waveform into a negative waveform having the same magnitude as the positive waveform and output the negative waveform as it is.

The memory 111 receives a 3-bit symbol for the positive waveform from the second logic unit 405 through the line 406 and outputs a filtered waveform value for the positive waveform. The filtered waveform value is input to the inverting unit 403 and the selector 404. The inverting unit 403 converts the filtered positive waveform value into a negative waveform value and inputs it to the selector 404. The selector 404 then inputs a negative waveform value input through the inverting unit 403 and a positive waveform value directly input from the memory 111. The selector 404 selects and outputs a negative waveform value or a positive waveform value according to a selection signal input from the second logic unit 405. The signal selected and output by the selector 404 is output to the first numerically controlled oscillator 115 and the second numerically controlled oscillator 114. Since the operations of the first numerically controlled oscillator 115 and the second numerically controlled oscillator 114 are the same as in FIG. 2, description thereof will be omitted.

In the above description, only the case where the first register 103 is a 1-bit register is described, but it should be noted that the present invention can be applied to the case where the register is 1 bit or more.

As described above, a Gaussian filter function can be performed as a small memory by using a simple lookup table without using a separate Gaussian filter.

In addition, since it has a general-purpose structure, it is applicable to a pulse shaping filter other than a Gaussian filter by changing the number of waveforms and input register bits stored in the memory when the continuous phase frequency shift modulator is implemented. There is an advantage.

Claims (10)

In a digital modulation device of a communication system, A second register having a plurality of shift registers and outputting the values of the shift registers in parallel for each symbol data input; A first register having at least one shift register and receiving feedback data and outputting a value of each shift register each time the symbol data is input; Having a lookup table having feedback data for maintaining a waveform continuously with respect to input symbol data, receiving symbol data output from the first register and the second register, and receiving feedback data for the symbol data. A logic unit that finds a table and outputs the first register; An interpolation counter for outputting a plurality of sample data composed of a plurality of bits each time the symbol data is input; Storing respective Gaussian filtered waveform values for address data configurable by symbol data and sample data output from the first and second shift registers and the interpolation counter, and inputting the address data. Memory to output the waveform value of the corresponding address And a numerically controlled oscillator configured to receive the waveform value and output an in-phase and quadrature waveform value. The method of claim 1, And the first register has a two bit shift register. The method of claim 2, And the second register has a shift register of 1 bit. The method of claim 3, And the logic unit outputs one bit of feedback data to the first register with respect to three bits output from the first and second registers. The method of claim 4, wherein And said memory stores eight Gaussian filtered waveform values. In a digital modulation device of a communication system, A second register having a plurality of shift registers and outputting the values of the shift registers in parallel for each symbol data input; A first register having at least one shift register and receiving feedback data and outputting a value of each shift register each time the symbol data is input; Having a lookup table having feedback data for maintaining a waveform continuously with respect to input symbol data, receiving symbol data output from the first register and the second register, and receiving feedback data for the symbol data. A logic unit that finds a table and outputs the first register; The symbol data may include information indicating whether the plurality of symbol data input from the first and second registers are a negative waveform or a positive waveform, and a lookup table having a size of each of the plurality of symbol data. When the symbol data is a negative waveform, the symbol data is converted into symbol data for a positive waveform having the same magnitude and output together with a first selection signal. A second logic unit to output together; An interpolation counter for outputting a plurality of sample data composed of a plurality of bits each time the symbol data is input; Stores Gaussian filtered waveform values of address data constituting symbol data and sample data output from the second logic unit and the interpolation counter, and inputs the corresponding address when the address data is input. Memory to output waveform values of An inversion unit for receiving the waveform value and outputting the negative waveform value; A selection unit which receives a waveform value output from the memory and a waveform value output from the inversion unit, and selects and outputs one of the waveform values according to the first and second selection signals; And a numerically controlled oscillator for receiving the selected waveform value and outputting an in-phase and quadrature waveform value. The method of claim 6, And the first register has a two bit shift register. The method of claim 7, wherein And the second register has a shift register of 1 bit. The method of claim 8, And the logic unit outputs one bit of feedback data to the first register with respect to three bits output from the first and second registers. The method of claim 9, And said memory stores eight Gaussian filtered waveform values.