KR20010084282A - Method For Ion Implantation - Google Patents

Abstract

PURPOSE: An ion implanting method is to form uniform drain and source regions by determining defected drain and source regions and implanting the regions with different amount of ions depending upon the defected degree of the regions. CONSTITUTION: It determines a thickness of a gate oxide film, and by controlling a scanning speed and implanting energy of an ion beam according to a thickness of the gate oxide film, a substrate is implanted with ion using the gate and a capped gate oxide film as a mask. At a thick portion of the gate oxide film, the ion beam scanning speed is slow, and the ion beam implanting energy is raised. At a thin portion of the gate oxide film, the ion beam scanning speed is quick, and the ion beam implanting energy is lowered. A pad oxide film is formed on an outer surface of a gate electrode, thereby electrically insulating the gate electrode from the exterior. The gate electrode is carried out through chemical vapor deposition to form a spacer on a side of the gate electrode. After a borophosphosilicate glass(BPSG) passivation layer is formed on a thermal oxide film, the BPSG passivation layer is carried out through sacrificial planarization to form a contact hole. After it determines a defected degree of a drain region and a source region, the scanning speed and implanting energy are controlled according to the defected degree.

Description

Method For Ion Implantation

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS transistor of a semiconductor device, and more particularly, to determine the thickness of a gate oxide film that serves as a buffer for ion implantation, and to control ion beam scanning speed and ion beam implantation energy to control ions under different conditions. Implant to form drain and source regions implanted with low concentration impurity, and closely measure the drain region and the source region lost by over-etching in the Self Align Contact process (hereinafter referred to as SAC process). The present invention relates to a method of manufacturing a MOS transistor of a semiconductor device, which makes it possible to form a uniform drain and source region by compensating a loss part by injecting a quantity.

In general, before the ion implantation process, the oxide film is grown to reduce impact due to loss due to physical or radiation of the silicon substrate and to filter impurities on the oxide film surface.

In addition, in the semiconductor DRAM device, a plug concept ion implantation process is performed in order to prevent loss of the silicon substrate and junction leakage caused by the plasma etching process. This ion implantation process completes the P-N junction structure and device characteristics that are the basis of the transistor. Such an ion implantation process has an advantage of obtaining an accurate doping profile.

However, it is difficult to form an accurate doping level due to external change factors such as the thickness of the oxide film or the loss of the silicon substrate. In particular, the conventional ion implantation process has a disadvantage in that it changes the overall device characteristics and increase the dispersion by proceeding to the same ion implantation process on the silicon substrate without considering the external change factors as described above.

1 is a diagram showing an imbalance according to a region of a typical silicon substrate.

1, the thickness of the oxide film formed as a shock mitigating role on the silicon substrate is not constant for each T, L, C, R, F region.

2 is a view illustrating a MOS transistor manufacturing process of a semiconductor device using a conventional ion implantation method.

Referring to FIG. 2A, a field oxide film 103 and a gate oxide film 105 are formed on the lightly doped (P ⁻ ) silicon substrate 101 to form active and isolation regions. The gate oxide film 105 is formed of a nitride film, GOX, and GPOX.

Referring to FIG. 2 (b), a polysilicon (not shown) and a capgate oxide film (not shown) are sequentially applied on the gate oxide film 105, and then a photosensitive agent (not shown) is applied to the entire surface, thereby performing a conventional photolithography process. Next, the gate electrode 107 and the capgate oxide film pattern 109 having a stacked structure are formed.

Referring to FIG. 2C, lightly doped drain regions (N ⁻ ) and sources are lightly doped by performing ion implantation using the gate electrode 107 and the cap gate oxide pattern 109 as a mask. After forming the region N ⁻ , the pad oxide layer 111 is formed on the outer surface of the gate electrode 107 of polysilicon by heat treatment in an oxidizing atmosphere to electrically insulate the surroundings.

Referring to FIG. 2D, an oxide film 113 for forming spacers on the side of the gate electrode 107 is formed by chemical vapor deposition.

Referring to FIG. 2E, the sidewall spacer 115 is formed on the side of the gate electrode 107 by performing reactive ion etching using the gate oxide film 105 as an etch stopping layer. Form.

Referring to FIG. 2 (f), ion implantation is performed at a high concentration while using the gate electrode 107, the pad oxide layer 111, and the sidewall spacer 115 as a mask, so that the heavily doped drain region N ⁺ and the source region ( N ⁺ ).

Referring to FIG. 2 (g), the implanted ions are sufficiently diffused by performing post-diffusion (Drive-In) of the heavily doped drain region N ⁺ and the source region N ⁺ . Then, a thermal oxide film 117 is formed of an insulating film for protecting the device.

Referring to FIG. 2 (h), after the BPSG passivation layer 119 is formed to reduce the step difference of the thermal oxide film 117, the BPSG passivation layer 119 is subjected to sacrificial planarization.

Referring to FIG. 2 (i), the metal wiring (not shown) is formed after the contact hole 121 is formed by the SAC process to expose the drain regions N ^{+ and} N ⁻ and the source regions N ^{+ and} N ⁻ . Form.

In the conventional method, as shown in FIG. 2 (c), the gate oxide film 105 serving as a buffer to reduce the loss of the silicon substrate 101 during ion implantation is diffused by a conventional oxidation process. Tube oxide film 105 in a dry oxygen atmosphere.

However, the thickness of the gate oxide film 105 formed on the silicon substrate 101 is not constant for each region as shown in FIG. Therefore, when ions are implanted into the silicon substrate 101 under the gate oxide film 105 with the same doping energy and ion amount in the ion implantation device, the silicon oxide film 101 has a low concentration due to the non-uniform thickness of the gate oxide film 105. There is a disadvantage in that the level of the doped drain region N ⁻ and the source region N ⁻ may not be uniformly achieved.

In addition, although the lightly doped drain region N ⁻ and the source region N ⁻ are formed at 307 μs ± 130 μs, the BPSG passivation layer 119 is planarized by an ion plasma etching process, and then contact holes in the SAC process. In the process of forming 121, the drain region N ⁻ and the source region N ^{− that} are over-etched to the lower silicon substrate and are lightly doped, are reduced to 200 μs to 300 μs and are lost. Therefore, in order to compensate for the lost lightly doped drain region N ⁻ and the source region N ⁻ , after forming the contact hole 121 to expose the silicon substrate 101 as shown in FIG. Plug ion implantation process is performed.

However, it is different for the loss portions of the lightly doped drain region N ⁻ and the source region N ⁻ . Therefore, injecting the same amount of ions into the loss portion during the plug ion implantation process may not achieve uniform levels of the doped drain region N ⁻ and the source region N ⁻ .

Therefore, the present invention was created to solve the above-mentioned problems, and an object of the present invention is to determine the thickness of the gate oxide film that serves as a buffer during ion implantation, and to adjust the ion beam scanning speed and ion beam injection energy to different conditions for each part. Ions are implanted to form drain and source regions implanted with low concentration impurity, and the drain and source regions lost by over-etching in the SAC process are closely measured, and the amount of ions are injected differently to compensate for the loss, thereby ensuring a uniform drain. And an ion implantation apparatus for forming a source region.

1 shows an imbalance along a region of a typical silicon substrate.

2 is a view showing a MOS transistor manufacturing process of a semiconductor device using a conventional ion implantation method.

Figure 3 is a flow chart showing an ion implantation method according to the present invention.

In the ion implantation method according to the present invention for achieving the above object, the step of measuring the imbalance according to the region of the silicon substrate before the ion implantation step and the ion beam implantation energy to compensate for the imbalance according to the region of the silicon substrate according to the measurement result Implanting ions onto the silicon substrate at a dose, dose, ion beam scan rate, or a combination thereof.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

3 is a flowchart illustrating an ion implantation method according to the present invention.

Referring to FIG. 3, the thickness of the oxide film formed on the silicon substrate of FIG. 1 is measured, and ions are implanted into the silicon substrate under the oxide film by adjusting the ion beam scanning speed and the ion beam implantation energy.

In addition, it is possible to know whether or not the loss is obtained by measuring the junction level of the drain region and the source region, and by adjusting the ion beam scanning speed and the ion beam implantation energy, ions are implanted to reduce the uniform drain region and source region. Form.

Hereinafter, reference numerals and symbols of detailed descriptions of the configuration of the present invention are the same as those of (a) to (i) of FIG. 2.

Referring to FIG. 2A, a field oxide film 103 and a gate oxide film 105 are formed on the lightly doped (P ⁻ ) silicon substrate 101 to form active and isolation regions. The gate oxide film 105 is formed of a nitride film, GOX, and GPOX.

Referring to FIG. 2 (b), a polysilicon (not shown) and a capgate oxide film (not shown) are sequentially applied on the gate oxide film 105, and then a photosensitive agent (not shown) is applied to the entire surface, thereby performing a conventional photolithography process. Next, the gate electrode 107 and the capgate oxide film pattern 109 having a stacked structure are formed.

3 is a flowchart illustrating a process of manufacturing a MOS transistor of a semiconductor device using the ion implantation method according to the present invention.

In FIG. 3, the thickness of the gate oxide film 105 of FIG. 2B is measured by a measuring device. Thereafter, the control unit of the ion implantation apparatus adjusts the ion beam scanning speed and the ion beam implantation energy according to the thickness of the gate oxide film 105, and performs ion implantation using the gate 107 and the capgate oxide pattern 109 as a mask. Conduct. The thick portion of the gate oxide film 105 slows the ion beam scanning speed, increases the ion beam injection energy, and implants the ions, and the thin part of the gate oxide film increases the ion beam scanning speed, and lowers the ion beam injection energy, thereby implanting ions. The lightly doped drain region N ^_ and the source region N ^_ are uniformly formed on the silicon substrate 101.

Thereafter, as shown in FIG. 2C, the pad oxide film 111 is formed on the outer surface of the gate electrode 107 of polysilicon to be electrically insulated from the surroundings.

Referring to FIG. 2D, an oxide film 113 for forming spacers on the side of the gate electrode 107 is formed by chemical vapor deposition.

Referring to FIG. 2E, the sidewall spacer 115 is formed on the side of the gate electrode 107 by performing reactive ion etching using the gate oxide film 105 as an etch stopping layer. Form.

Referring to FIG. 2 (f), ion implantation is performed at a high concentration while using the gate electrode 107, the pad oxide layer 111, and the sidewall spacer 115 as a mask, so that the heavily doped drain region N ⁺ and the source region ( N ⁺ ).

As shown in FIG. 2 (g), the implanted ions are sufficiently diffused by performing post-diffusion of the heavily doped drain region N ⁺ and the source region N ⁺ . Then, a thermal oxide film 117 is formed of an insulating film for protecting the device.

Referring to FIG. 2 (h), after the formation of the BPSG passivation layer 119 to reduce the step difference of the thermal oxide film 117, the BPSG passivation layer 119 is subjected to sacrificial planazation.

Referring to FIG. 2I, the contact holes 121 are formed by SAC fixing to expose the drain regions N ^{+ and} N ⁻ and the source regions N ^{+ and} N ⁻ . However, in the SAC process, the silicon substrate is overetched to give a loss of the lightly doped drain region N ^_ and the source region N ^_ .

Therefore, the measures as shown in Figure 3 the loss degree of the contact hole, the lightly doped drain regions exposed to the (121) (N ^_), and a source region (N ^_). Thereafter, the control unit of the ion implantation apparatus adjusts the ion beam scanning speed and the ion beam implantation energy according to the loss of the lightly doped drain region N ^_ and the source region N ^_ . The portion of the lightly doped drain region N ^_ and the source region N ^_ which have a high loss slow the ion beam scanning speed, increase the ion beam implantation energy to inject a large amount of ions, and the portion of the low doped drain region N ^{_ that} has a low loss is ion beam scanning speed. By lowering the ion beam implantation energy by decreasing the ion beam implantation rate and reducing the ion beam implantation energy, the lightly doped drain region N ^_ and the source region N ^_ are uniformly formed on the silicon substrate 101.

Thereafter, metal wires (not shown) are formed in the contact hole 121.

In the drawings and detailed description, preferred techniques of the invention have been described, which are not intended to limit the scope of the invention as set forth in the claims below. Therefore, the present invention is not limited to the claims, and modifications and improvements are possible at the level of those skilled in the art.

According to the present invention described above, by measuring the thickness of the gate oxide film and the impurity region lost due to the SAC process, by implanting ions by adjusting the ion beam scanning speed and ion beam implantation energy, it is possible to form a uniform impurity region.

Claims (2)

Measuring an imbalance according to a region of the silicon substrate in a pre-ion implantation step; And Implanting ions onto the silicon substrate at ion beam implantation energy, dose, ion beam scan rate, or a combination thereof to compensate for imbalances according to the region of the silicon substrate according to the measurement results. Way. The method of claim 1, The measurement of the imbalance according to the region of the silicon substrate is characterized in that for measuring the thickness of the oxide film provided to the screen oxide film during ion implantation, the dose loss of the impurity region in the silicon substrate by the plasma etching.