KR20010076636A - data bus drive circuit for use in semiconductor memory device - Google Patents

Abstract

PURPOSE: A data bus driving circuit for a semiconductor memory device is provided to perform the original functions which improves driving speed and to reduce the power consumption, and easily embody and minimize additional control signals since elements of a bus system are not complicated. CONSTITUTION: A couple of bus lines(L1 and L2) include a real line and a complementary line. The first and second driver(10 and 11) drive input signals from the couple of bus lines(L1 and L2) into a half swing pulse formation. A first and second receivers(30 and 31) receive the output signals from the first and second driver(10 and 11) and output with a full half swing pulse formation. A first and second equalizers(20 and 21), connected to the each bus lines(L1 and L2), equalize the signal of an equalization period with the half power voltage level. A control signal generating section(40) generates control signals for equalization control signal(EQ) and the first and second driver(10 and 11) after receiving a clock signal(CLK), a real data(DIN_T) and a complementary data(DIC_C).

Description

Data bus drive circuit suitable for semiconductor memory device {data bus drive circuit for use in semiconductor memory device}

TECHNICAL FIELD The present invention relates to the field of semiconductor memory, and in particular, to a data bus driver circuit suitable for semiconductor memory devices.

Increasingly, semiconductor manufacturers are under pressure to produce low-power semiconductor chips that operate at high speeds in response to various demands of consumers.

By the way, it is known that a large part of the speed delay and power consumption of a semiconductor chip are generated in the part which drives the bus with large load capacity inside a chip. Therefore, there is absolutely a need to reduce the power consumption required to drive the bus and to reduce the signal delay inevitably generated by the transmission of signals through the bus. Various methods for improving are disclosed in the art.

One such technique is, for example, Hiebbe. US Patent No. 5,369,315 to Hief V. Tran. The patent discloses that the driver supplies the half power supply voltage, thereby reducing the voltage swing of the signal line, thereby improving signal transmission speed and reducing power consumption. Another such technique is to precharge the data bus to a half supply voltage to improve speed and reduce power consumption, which is disclosed in US Patent No. 5,742,185 to Jaejin.

However, even if the power consumption is reduced when the bus line is driven by reducing only the swing width of the bus, the receiver side amplifies using a sense amplifier or the like, thus increasing power consumption and reducing the overall power consumption. Even if a sense amplifier is not used, if the receiver requires a control signal other than the bus signal, it also drives the control signal, which adds additional power consumption and provides a mutual timing margin between the bus signal and the control signal to prevent malfunction. Because it must be secured, it can be a factor of slowing down the signal transmission speed. In addition, when the bus is driven with a small swing, a section in which the bus signal is equalized is generally required. If the waveform of the bus signal is too complicated, not only it is difficult to precisely control timing, but also many control signals are added. In addition, there is a problem that power consumption is inevitable in order to drive the control signal.

Therefore, while driving the half swing pulse to achieve the original inherent function of increasing speed and reducing power consumption, the components of the bus system are simple, easy to implement, and additional control signals can be minimized. It must be fantastic.

An object of the present invention is to provide a circuit that can solve the above problems of the prior art.

Another object of the present invention is to drive the bus with a half swing pulse to achieve the original purpose of improving speed and reducing power consumption, while simplifying the components of the bus system to facilitate implementation and minimizing additional control signals. In providing the furnace.

According to one aspect of the present invention for achieving the above objects and other objects, the data bus drive circuit,

A pair of bus lines comprising a seal line and a complementary line;

The bus line is connected to the bus line, and the bus line is connected to the bus line from the level of the half power voltage in response to the seal line and complement line pull up / pull control signals obtained by logically combining the clock with the applied real data and the complementary data. Or a driver for driving at the signal level of the second power supply voltage;

An equalizer connected between the pair of bus lines, the equalizer maintaining the potential of the seal line and the complementary line at the half power voltage in an equalization section in response to an equalization control signal applied according to the clock cycle; And

A first power supply voltage level to a second power supply voltage level or a second power supply voltage level, in response to only the signal levels on the busline that are connected to the pair of buslines and transition to a half swing in a signal transmission section; And a receiver for generating an output in the form of a full swing pulse transitioning to the first power supply voltage level.

1 is a block diagram of a data bus driving circuit according to an embodiment of the present invention;

FIG. 2 is a signal waveform diagram of a half swing pulse type shown in the bus line of FIG.

3A, 3B, and 3C are detailed circuit diagrams showing implementation examples of the equalizer shown in FIG.

4A and 4B are detailed circuit diagrams showing implementation examples of the receiver of FIG. 1, and FIG. 4C is an operation timing diagram of signals related thereto.

5A and 5B are diagrams illustrating an implementation of the driver of FIG. 1 and operation timings of signals related thereto;

6A and 6B illustrate an implementation example of the control signal generator of FIG. 1 and an operation timing diagram of signals related thereto;

The above and other objects, features, and operational advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention described below with reference to the accompanying drawings. It should be noted that the same or similar parts to each other in the drawings are described with the same or similar reference numerals for convenience of explanation and understanding.

1 is a block diagram of a data bus driving circuit applied to the present invention. A pair of bus lines L1 and L2 formed of real lines and complementary lines, and first and second drivers for driving signals on the bus lines L1 and L2 in the form of half swing pulses; 10,11) connected to the first and second receivers 30 and 31 and the bus lines L1 and L2 that receive only the bus signal provided by the driver and generate an output of a full swing, and a half in the equalization section. Receives equalization control signal EQ and the driver by receiving first and second equalizers 20 and 21 that equalize at a level of a power supply voltage, clock signal CLK, real data DIN_T, and complementary data DIN_C. It consists of a control signal generator 40 for generating signals for controlling (10, 11). Here, the complementary line is used in pairs with the real line to transmit a signal of one bit, and the logic level of the complementary line is opposite to the real line in the signal transmission section.

Typically, when a node is configured, it is necessary to supply current from an external power source when the node is charged from low to high. The amount of current required in this case is proportional to the swing width of the voltage and the capacitance, which is the load capacity. Therefore, to reduce current consumption, either the voltage swing width or the node capacitance should be reduced. However, the problem of reducing the capacitance of a node can be solved by improving the manufacturing process or modifying the chip architecture.In the state where the capacitance of the node is determined, the current consumption must be reduced by circuit technology. An efficient bus scheme must be developed to drive, receive and process the signals. In the present invention, connected to a pair of bus lines, the first power supply voltage level to the second power supply voltage level or the second power supply only in response to only the signal levels on the bus line transitioning to a half swing in a signal transmission section. A receiver that produces an output in the form of a full swing pulse that transitions from a voltage level to a first power supply voltage level is disclosed as one of its characteristic configurations.

FIG. 2 is a signal waveform diagram of a half swing pulse type shown in the bus line of FIG. 1. Referring to the drawings, each section of the bus signal consists of an equalization section EQ and a signal transmission section SIG. As shown in the sections T1, T2, and T3, in the equalizing section, both the seal line and the complementary line have the same potential as the half power supply voltage (VDD / 2), and the signal as shown in the sections T1 and T2. In the transmission section, one of the seal line and the complementary line is driven to the power supply voltage VDD potential, and the other is driven to the ground voltage GND potential. When the seal line is driven at the power supply voltage and the complementary line at the level of the ground voltage, the seal line is in a logic "high" state as in the period T1. In the logic " low " state, as shown in the section T2, the seal line is driven to the ground voltage and the complementary line to the level of the power supply voltage. That is, as described above, the bus signal is a signal that is driven from the half power supply voltage to the power supply voltage or the ground voltage and repeats the equalization from the power supply voltage or the ground voltage to the half power supply voltage, and its swing width is in the form of a half power supply voltage pulse. As can be seen in the section T3, in the standby mode, the bus signal maintains an equalization state. Thus, the advantage of this bus waveform is that the swing width of the bus is halved, so the current driving the bus is halved compared to the full swing. In addition, since the real signal and the complementary signal are divided into the power supply voltage and the ground voltage in the state equalized by the half power supply voltage, the signal transmission speed is improved. Therefore, according to the above scheme, in the embodiment of the present invention, it is possible to solve the trade-off problem of current reduction and speed improvement.

3A, 3B, and 3C show detailed circuit diagrams showing implementations of the equalizer in FIG. 1. In FIG. 3A, the equalizer for half supply voltage equalization has a drain connected to the seal line L1, a source connected to the complementary line L2, and a N-type MOS transistor receiving a control signal EQ for performing equalization through a gate terminal. (NM1). In the equalization section, the control signal EQ is activated to a high level, and the seal line and the complementary line are short-circuited. On the other hand, in the signal transmission section, the control signal is deactivated to a low level so that the seal line and the complementary line are opened. That is, in this case, the N-type MOS transistor NM1, which is a switching element, is turned off. In FIG. 3B, an equalizer has a source MOS transistor PM1 that receives a source connected to the seal line L1, a drain connected to the complementary line L2, and receives an inversion control signal EQ # for equalization. do. In the equalizing section, the inversion control signal EQ # is activated at a low level so that the seal line and the complementary line are short-circuited. On the other hand, in the signal transmission section, the inversion control signal is inactivated to a high level so that the shaped MOS transistor PM1 is turned off, so the seal line and the complementary line are opened.

3A and 3B, it has been described that each transistor is shorted and equalized to a half power supply voltage. However, substantially the capacitance of the two bus lines may be slightly different, and if the equalization section lasts for a long time, the potential of the bus lines may drop to a level below the half power supply voltage due to current leakage. Therefore, the equalizer which has a countermeasure against this is FIG. 3C. In Fig. 3C, the equalizer is composed of three N-type MOS transistors N1, N2 and N3, each gate of which is connected to the node N3 to which the control signal EQ is applied. The drain of the transistor N1 is connected to a half power supply voltage, and the source is connected to a seal line L1 connected to the node N1. The drain of the transistor N2 is connected to the half power supply voltage, and the source is connected to the complementary line L2 connected to the node N2. A drain and a source of the transistor N3 are connected between the sources of the transistors N1 and N2. In the equalization section, the seal line L1 and the complementary line L2, which maintain their respective half power supply voltages according to the turn-on of the transistors N1 and N2, have a more accurate level by the turn-on operation of the transistor N3. Maintain power supply voltage surely. In FIG. 3C, three terminals, that is, the half power voltage terminal and the nodes N1 and N2, are mode- shorted in the equalization section, and the three terminals are opened to each other in the signal transmission section.

4A and 4B are detailed circuit diagrams showing implementation examples of the receiver of FIG. 1, and FIG. 4C is an operation timing diagram of signals related thereto. Referring to FIG. 4A, a receiver includes an N-type transistor N1 having a drain connected to a seal line L1 and a gate connected to a complementary line, a gate connected to the complementary line, and a source receiving a power supply voltage. The source of the transistor N1 is composed of a connected morph transistor P1. As shown in FIG. 4C, it can be seen that the level of the output node X of the receiver is full swing between the power supply voltage and the ground voltage. The receivers 30 and 31 receive a bus signal which is a half swing pulse without a separate control signal and change the full signal to a full swing pulse. Therefore, since there is no additional control signal, there is no power consumption for driving the control signal, thereby saving power.

Similarly, referring to FIG. 4B, the receivers 30 and 31 are connected to the N-type MOS transistor N1 having a drain connected to the complementary line L2 and a gate connected to the seal line L1, and to the seal line L1. A gate is connected, a source receives a power supply voltage, and a drained Morse transistor P1 is connected to a source of the transistor N1 at a drain. According to the above configuration, as shown in FIG. 4C, it can be seen that the level of the output node Y of the receiver is full swing between the power supply voltage VDD and the ground voltage GND in the section T1. The circuit of FIG. 4B also takes only a half swing pulse bus signal as an input and converts it to full swing without requiring a separate control signal, thereby reducing power consumption.

4A and 4B, the electric potentials of the seal line and the complementary line maintain the half power supply voltage VDD / 2 in the equalization period EQ in the sections T1 and T2. Therefore, the N-type MOS transistor N1 of FIGS. 4A and 4B is turned off, only the type MOS transistor P1 is turned on, and each output node X and Y is precharged to the power supply voltage VDD. If the bus signal connected to the source of NMOS is low and the bus signal connected to the gates of NMOS and PMOS is high during the signal transmission section SIG, PMOS is off and NMOS (N1) is turned on so that the output nodes (X, Y) are driven to the ground potential (GND). If the bus signal connected to the source of NMOS (N1) is high and the bus signal connected to the gates of NMOS and PMO (P1) is low in the signal transmission section (SIG), PMOS is on. The NMOS is turned off to maintain the output node precharged with the power supply voltage. That is, according to the receiver circuits of FIGS. 4A and 4B, the pulse signal of the half swing is converted into the full swing without a separate control signal.

5A and 5B show an implementation timing of the driver of FIG. 1 and an operation timing diagram of signals related thereto. The seal line pull-up control signal TUP # and the seal line pull-down control signal TDN are applied to the gates of the PMOS transistors and the NMOS transistors MP1 and MN1, respectively. The complementary line pull-up control signal CUP # and the complementary line pull-down control signal CDN are applied to the gates of the PMOS transistors and the NMOS transistors MP2 and MN2, respectively. Sources of the type MOS transistors MP1 and MP2 are connected to a power supply voltage, and sources of the N-type transistors MN1 and MN2 are connected to a ground voltage. The common drain node of the type MOS transistor and the en-type MOS transistor MP1 and MN1 is connected to the seal line BUS_T, and the common drain node of the type MOS transistor and the en-type MOS transistor MP2 and MN2 is the complementary line BUS_C. Is connected to. Referring to FIG. 5B, in the equalizing period EQ, the seal line pull-up control signal TUP # and the seal line pull-down control signal TDN are applied to the high and low states, respectively, and the complementary line pull-up control signal CUP # and The complementary line pull-down control signal CDN is applied to the high and low states, respectively, so that the transistors MP1, MN1, MP2, and MN2 as driver bus driving switches are turned off. In the standby mode, the states of the transistors MP1, MN1, MP2, and MN2 are the same as in the equalization section. The states of the transistors MP1, MN1, MP2, and MP2 of the driver that do not transmit a signal during the signal transmission period are also the same as above. The states of the transistors MP1, MN1, MP2, and MN2 of the driver transmitting the signal during the signal transmission period depend on the state of the data to be transmitted, that is, high or low level. In other words, when data high is transmitted, the transistors MP1 and MN2 are in an on state and the transistors MN1 and MP2 are in an off state. When the data row is transferred, the transistors MP1 and MN2 are in an off state, and the transistors MN1 and MP2 are in an on state. Therefore, the state of the bus drive control switch is TUP # = GND, TDN = GND, CUP # = VDD, CDN = VDD when transmitting data high, and TUP # = VDD, TDN = VDD, CUP when transmitting data low. # = GND, CDN = GND.

6A and 6B show an implementation example of the control signal generator of FIG. 1 and an operation timing diagram of signals related thereto. Referring to FIG. 6A, an inverter IN1 that inverts the clock signal CLK to generate an equalization control signal EQ, and a NAND gating of the clock signal CLK and real data to generate a seal line pull-up control signal. Inverter IN3 generating a complementary line pull-down control signal by inverting a NAND gate NAN1 and the output of the NAND gate NAN1, and generating a complementary line pull-up control signal by NAND gating complementary data with the clock signal CLK. NAND gate NAN2 and an inverter IN2 for inverting the output of the NAND gate NAN2 to generate a seal line pull-down control signal. According to the above arrangement, only one global control signal is used, which makes the circuit very simple. It can also be seen that the control of the equalizer can be made simply by inverting the clock. If the equalizer is composed of a type MOS transistor as shown in FIG. 3B, the equalizer control signal may be used as EQ #, which is a direct equalization control signal, without inverting a clock. In addition, the control signal of the driver is simply configured using the local data DIN_T, DIN_C, and CLK.

As described above, the data bus driving circuit disclosed in the embodiments of the present invention can reduce current consumption by reducing the swing width of the bus signal by half, and the signal transmission speed since the bus signal transitions from the half supply voltage to the supply voltage or the ground voltage. While improved, as shown in the embodiment, the receiver does not need a separate control signal, and there is an advantage that the control of the driver and the equalizer is very simple.

Therefore, it is expected that the contribution of implementing a bus in the semiconductor memory chip at low power and high speed will be great.

The present invention has been described based on the embodiments based on the illustrated drawings, but is not limited thereto, and various changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is obvious that other embodiments may be modified, as well as equivalent embodiments. For example, the number of transistors constituting the components of the bus system, the driving type and the connection configuration can be changed in various ways as the matter changes.

According to the present invention as described above, while improving the speed and power consumption, the components of the bus system is simple, so that the implementation is easy and the additional control signal is minimized.

Claims (10)

A pair of bus lines comprising a seal line and a complementary line; The bus line is connected to the bus line, and the bus line is connected to the bus line from the level of the half power voltage in response to the seal line and complement line pull up / pull control signals obtained by logically combining the clock with the applied real data and the complementary data. Or a driver for driving at the signal level of the second power supply voltage; An equalizer connected between the pair of bus lines, the equalizer maintaining the potential of the seal line and the complementary line at the half power voltage in an equalization section in response to an equalization control signal applied according to the clock cycle; And A first power supply voltage level to a second power supply voltage level or a second power supply voltage level, in response to only the signal levels on the busline that are connected to the pair of buslines and transition to a half swing in a signal transmission section; And a receiver for generating an output in the form of a full swing pulse that transitions to the first power supply voltage level at the first power supply voltage. The data bus driving circuit of claim 1, wherein the second power supply voltage is a level of a ground voltage when the first power supply voltage is a level of a driving power supply voltage. The NMOS transistor of claim 1, wherein the receiver comprises a N-type transistor having a drain connected to the seal line and a gate connected to a complementary line, a source connected to the complementary line, a source receiving a power supply voltage, and a source of the transistor at a drain. The data bus driving circuit of claim 1, wherein the data bus driving circuit comprises a connected MOS transistor. The NMOS transistor of claim 1, wherein the receiver comprises a N-type transistor having a drain connected to the complementary line and a gate connected to a seal line, a source connected to the seal line, a source receiving a power supply voltage, and a source of the transistor at a drain. The data bus driving circuit of claim 1, wherein the data bus driving circuit comprises a connected MOS transistor. The data bus driving circuit according to claim 1, wherein the signal transmission section is determined to transmit logic high when the seal line is driven at the power supply voltage level and the complementary line is driven at the ground voltage level. The data bus driving circuit according to claim 1, wherein the signal transmission section is determined to transmit a logic low when the seal line is driven at the ground voltage level and the complementary line is driven at the power supply voltage level. 2. The equalizer of claim 1, wherein the equalizer is composed of three N-type MOS transistors N1, N2, N3 connected to gates of the node N3 to which the control signal EQ is applied. The drain is connected to the half power supply voltage, the source is connected to the seal line L1 connected to the node N1, the drain of the transistor N2 is connected to the half power supply voltage, and the source is connected to the node N2. The drain and the source of the transistor N3 are connected between the sources of the transistors N1 and N2. In the equalization section, three terminals, that is, the half power voltage terminal and the nodes ( N1, N2) is mode shorted, and the three terminals are open to each other in the signal transmission section. 2. The driver of claim 1, wherein the driver comprises a PMOS transistor and an NMOS transistor MP1 and MN1 for receiving a seal line pull-up control signal TUP # and a seal line pull-down control signal TDN, respectively, as a gate. It is composed of the PMOS transistors and the NMOS transistors MP2 and MN2 respectively receiving the pull-up control signal CUP # and the complementary line pull-down control signal CDN as gates, and the source of the PMOS transistors MP1 and MP2 is The source of the N-type transistors MN1 and MN2 is connected to a ground voltage, and the common drain node of the N-type transistor and the N-type transistors MP1 and MN1 are connected to the seal line BUS_T. The common drain node of the PMOS transistor and the NMOS transistor MP2 and MN2 is connected to the complementary line BUS_C. Data bus drive circuit. A control signal generator which logically combines applied real data and complementary data with a clock to generate real line and complementary line pull-up / pull-down control signals and an equalization control signal; A pair of bus lines comprising a seal line and a complementary line; A signal level of a first power supply voltage or a second power supply voltage is connected between the control signal generator and the bus line, and the bus line is connected from the level of a half power supply voltage to a level of a half power supply voltage in response to the seal line and complementary line pull-up / pull down control signals. At least one driver for driving; At least one equalizer connected between the pair of bus lines and configured to maintain the same potential of the seal line and the complementary line at a half power supply voltage in an equalization section in response to the equalization control signal generated in synchronization with the clock; And A first power supply voltage level to a second power supply voltage level or a second power supply voltage level, in response to only the signal levels on the busline that are connected to the pair of buslines and transition to a half swing in a signal transmission section; And at least one receiver for generating an output in the form of a full swing pulse that transitions to a first power supply voltage level in the system. 2. The seal line of claim 1, wherein the control signal generator is configured to invert the clock signal CLK to generate an equalization control signal EQ, and to nand gate the clock data CLK to real data. NAND gate NAN1 generating a pull-up control signal, inverter IN3 generating a complementary line pull-down control signal by inverting the output of the NAND gate NAN1, and NAND gating complementary data with the clock signal CLK. And a NAND gate (NAN2) for generating a line pull-up control signal, and an inverter (IN2) for inverting the output of the NAND gate (NAN2) to generate a seal line pull-down control signal.