KR20010076456A - A delay controlable clock buffer - Google Patents

Abstract

PURPOSE: A clock buffer capable of delay adjustment is provided to realize the delay adjustment of clock by having delay compensating parts which compensate for the delay of clock in buffer row. CONSTITUTION: The clock buffer capable of delay adjustment has the buffer row(200), the delay compensating parts(300), the control pin(400). The delay compensating parts(300) compensate the delay of the clock in the buffer rows(200). The control pin(400) is for supplying reference voltage to the delay compensating parts(300). The delay compensating parts(300) has nMOS transistor for resistance and nMOS transistor for capacitance to compensates the delay of input clock depending on the delay due to RC time constant formed by capacitance and resistance.

Description

A delay controlable clock buffer

The present invention generally solves the problem that the chip does not operate due to skew or delay difference between the clocks after layout out during chip design. In particular, the clock control of the system can be performed externally. It relates to the structure of the clock buffer.

The conventional clock buffer structure is composed of one or several clock buffers sized in consideration of the load between the internal PLL (or external clock) 10 and the internal flip-flop 20 as shown in FIG. have. 2 is a view for explaining the operation of the clock buffer of the above structure. Hereinafter, the operation and effect of the conventional clock buffer of FIG. 2 will be described.

The PLL 10 using the external reference clock shown in FIG. 2 generates a clock for operation inside the chip. In consideration of the number of flip-flops, the internal clock uses a clock buffer with a large driving capability to operate the internal logic and the flip-flop in conjunction.

In the conventional clock buffer having such a structure, the PLL 10 generates an accurate clock in consideration of skew, delay, and the like. However, since the driving capability is small, the clock of the PLL 10 passes through clock buffers having a large driving capability and is used as an internal clock. However, as shown in the timing diagram of FIG. 2, after passing through the buffers 20 having the large driving capability, skew may increase as the timing diagram goes from 1) to 5).

In order for the clock buffer of the above configuration to operate correctly, it is necessary to verify timing of the correct clock using various back-annotation tools. In reality, however, the difference between the tool and the silicon is difficult to match precisely, and there is a problem that the skew problem caused by the delay cannot be solved.

Accordingly, an object of the present invention is to provide a clock buffer capable of adjusting a clock delay by including a delay compensation unit for compensating for a delay of a clock in a buffer string. .

1 is a block diagram showing the configuration of a clock buffer according to the prior art.

Figure 2 is a block diagram for explaining the operation of the conventional clock buffer

Figure 3 shows the configuration of a clock buffer capable of delay adjustment according to the present invention

Block diagram

4 is a diagram showing the structure of a clock buffer capable of delay adjustment according to the present invention;

Figure 5 shows another embodiment

** & * Description of the symbols for the main parts of the drawings ***

100: PLL 200: Clock Buffer

300: nMOS Tr. 400: control pin

In order to achieve the above object, a configuration of the present invention includes a buffer string to which a clock signal is input, a delay compensator for compensating a clock delay in the buffer string, and a control pin for applying a reference voltage to the delay compensator. Characterized in that configured to include.

Hereinafter, with reference to the accompanying drawings, the operation and effect of an embodiment of the present invention will be described in detail.

As shown in FIG. 3, one PLL 100 and one or more clock buffers 200 that can adjust one or more delays are configured.

4 shows the internal structure of a clock buffer that can adjust the delay, and the nMOS Tr. 300 and the capacitances of the capacitances compensate for the delay between the clocks used as small buffers and capacitances. It consists of a control pin 400 that determines the capacitance.

After the chip is designed as shown in Figure 3, if the clock does not operate due to the delay or skew difference between the clocks, the control pin of the clock buffer that can adjust the delay provided externally The voltage set at 400 is applied. When the voltage is applied, the delay of the clock buffer 200 to be adjusted can be known.

This can be obtained by the following principle. That is, it is used depending on the voltage applied to the gate of the gate capacitance of the nMOS Tr. 300 inside. That is, by adjusting the voltage of the control pin 400 by using the principle that the turn on resistance of the nMOS Tr. 300 is changed according to the gate voltage, the nMOS Tr is outputted to the output of one small buffer. The resistance and capacitance according to the characteristic of .300 are configured to compensate for the delay of the input clock according to the delay due to the RC time constant so as to adjust the skew.

FIG. 5 is a diagram illustrating another embodiment of a delay adjustment method using an RC time constant of nMOS Tr. 300 of FIG.

In the configuration of FIG. 5, a variable resistor and a variable capacitor are substituted for the nMOS Tr.

Since the present invention described above compensates for the difference between the CAD tool and the chip, the skew difference caused by the delay between clocks generated in the conventional chip can be easily solved without adding a complicated circuit configuration. . In addition, debugging of the chip can be easily implemented, resulting in cost and time savings.

Claims (3)

The delay control of the clock is configured to include a buffer string to which a clock signal is input, a delay compensator for compensating a clock delay in the buffer string, and a control pin for applying a reference voltage to the delay compensator. Possible clock buffers. The clock buffer structure of claim 1, wherein the delay compensation unit uses an RC time constant by a capacitor and a resistor. The buffer structure of claim 1, wherein the delay compensation unit is a resistance nMOS Tr. And a capacitance nMOS Tr.