KR20010076008A - A Method of Forming Semiconductor Devices - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to solve the problems that a plate electrode is reduced due to rear processes, a portion connecting a buried contact with a SAC(Self Aligned Contact) pad in the path of a capacitor and a drain area of a cell, and a transistor of the cell malfunctions. CONSTITUTION: The method includes the first through the fifth steps. The first step is to sequentially form a storage electrode(3) and a dielectric film on a semiconductor substrate having an interlayer including a BPSG(Boro Phosphorous Silicate Glass) film(1). The second step is to form a plate electrode layer by stacking a polysilicon on the semiconductor substrate. The third step is to form a plate electrode by patterning the plate electrode layer, and form a plurality of holes(9) on a position not folded on a plane with the storage electrode. The fourth step is to stack a USG(Undoped Silicate Glass) on the plate electrode having holes, and fill up the holes. The fifth step is to stack the BPSG film on the USG film and reflow.

Description

A method of forming semiconductor devices

The present invention relates to a method for forming a semiconductor device, and more particularly, to a method for forming a memory semiconductor device having a COB structure.

BACKGROUND OF THE INVENTION A semiconductor device is a very complicated and precise device formed by stacking a film of various materials that function as a conductor, a non-conductor, and a semiconductor on a semiconductor substrate, processing the same to form a plurality of electronic and electrical elements, and combining them by wiring. A typical example of these semiconductor devices is DRAM. Cells that make up the storage unit in DRAM are usually composed of one metal oxide silicon (MOS) transistor and one capacitor. In this case, the source / drain regions of the transistor are connected to the bit line and the capacitor, respectively, and the gate electrode is connected to the word line.

In accordance with the trend toward higher integration of devices in semiconductor devices, the distance between cells in a single chip is narrowing, and of course, the distance between devices and devices, wires and wires is narrowing, and the size of devices and wires is decreasing. In the case of capacitors, the formation area must be reduced due to high device integration, but a proper capacity of the device must be secured so that a trade off relation occurs in the manufacture of semiconductor devices. In order to overcome this problem, a method of three-dimensionally forming a capacitor is used. For example, a capacitor on bit line (COB) structure may be used to form a capacitor on a relatively large bit line, and the storage electrode forming the capacitor may be hollowed out in a cylindrical shape, or several planar wings may be formed around the bit line. I'm using.

As the memory semiconductor device of the COB structure continues to be highly integrated, the pitch between the bit lines, which serve to transport data, is reduced, and the pitch of formation of the capacitor, which serves to store data, becomes very narrow, and the lower electrode of the capacitor The spacing between the buried contact and the Saal Aligned Contact pad (SAC) pad connecting the storage electrode forming the first electrode and the drain electrode of the active region is also reduced.

Fig. 1 shows a cross section of a boundary between a cell block and a periphery in an example of a conventional COB structure DRAM device. A shallow trench isolation (STI) insulating film is formed on the substrate, and a gate pattern is formed on the substrate. The gate pattern is formed on the gate insulating film formed before the gate pattern formation, and the gate pattern is usually surrounded by the capping mask insulating film and the spacer insulating film. Above it is an interlayer insulating film, usually with SAC pads between the gate patterns. SAC pads have been gradually used because the gaps between the gate patterns become narrow, and it is difficult to form a contact for connecting the active region between the gate patterns and the upper bit line 6 or the capacitor storage electrode 3.

The oxide films constituting the interlayer insulating film are not formed at one time, but are stacked two or more times in connection with the formation of the bit line 6 and the contacts. For example, the interlayer insulating film is first formed on the gate pattern with a lower portion first, and then etched to form a SAC pad, and then, an intermediate portion is stacked, a bit line contact hole is etched, and a bit line 6 is formed, and then again an upper portion. A BPSG film 1 and a PE (Plasma Enhanced) oxide film 2 are stacked and patterned for the buried contacts 5.

A silicon nitride film is usually stacked over the interlayer insulating film made of an oxide film for the convenience of forming an upper capacitor. Some of the SAC pads are connected to storage node contacts, i.e., buried contacts 5, and some are connected to contacts with bit lines 6. As shown in FIG. An oxide-nitride-oxide (ONO) film and tantalum pentoxide (Ta ₂ ) are formed on the silicon nitride layer before forming a three-dimensional polysilicon storage electrode 3 and forming a plate electrode 4 on the storage electrode 3. O ₅₎ is a laminating film or the like surrounding the storage electrode 3. The plate electrode 4 is again formed thereon, and then a silicon oxide film 7 usually made of USG (Undoped Silicate Glass) and a silicon oxide film 8 made of Boro-Phosphorous Silecate Glass (BPSG) are laminated.

In the DRAM semiconductor device, the plate electrode 4 formed over the storage electrode 3 is integrally formed in a block without being separated for each cell. And mainly consists of polysilicon. However, the upper BPSG film 1 forming at least a part of the interlayer insulating film reflows the silicon oxide film 8 when the silicon oxide film 8 made of BPSG is used again after the upper plate electrode 4 is formed. In the process of softening again, it has fluidity. In addition, the polysilicon constituting the plate electrode 4 also shows a phenomenon in which some recrystallization is made by receiving heat.

When the plate electrode 4 is contracted, the periphery of the cell block moves little toward the center, and the storage electrode 3 engaged with the plate electrode 4 and the buried contact 5 connected with the storage electrode 3 are sequentially in turn. Try to move towards the center of In addition, although the interlayer insulating layer through which the buried contact 5 penetrates should suppress movement of the buried contact 5, the buried contact 5 is softened because the upper BPSG film 1 constituting the buried contact 5 is softened and has fluidity. ) Does not prevent movement. As a result, the buried contact 5 may be spaced apart from the SAC pad connected to the lower side while the upper portion moves to the center, and the electrical connection may be weakened, resulting in a malfunction of the function.

FIG. 2 is a cross sectional view showing the inclination of the buried contact 5 due to heat shrinkage of the plate electrode 4 in the conventional COB type memory semiconductor device as shown in FIG. When the plate electrode 4 contracts, the dielectric film and the storage electrode 3 engaged with each other also move together. In addition, the buried contact 5, which is connected to the storage electrode 3, is also moved along with the storage electrode 3 as the plate electrode 4 contracts. As a result, the gap between the storage electrode 3 and the buried contact 5 and the buried contact 5 and the SAC pad interface, which are vulnerable parts, is formed and partially separated.

In particular, at the periphery of each block, the thermal contraction of the plate electrode 4 accumulates, and the displacement of the plate electrode 4 increases, and in the cells located therein, the buried contact 5 is inclined. There was a problem that the transistors were not connected correctly and the cell function became uncertain or inefficient.

According to the present invention, as described above, in a DRAM having a conventional COB type structure, the plate electrode contracts under the influence of a subsequent process, and the contact between the drain region of the cell and the contact of the buried contact with the SAC pad in the path of the capacitor is spaced apart. It is an object of the present invention to provide a method for forming a new DRAM semiconductor device that can solve a problem in which an abnormality occurs in a transistor function.

1 is a process sectional view of a cell block and a peripheral boundary in an example of a conventional COB structure DRAM device;

FIG. 2 is a cross-sectional view illustrating a buried contact inclination due to thermal contraction of a plate electrode in the COB type memory semiconductor device of FIG. 1; FIG.

3 and 4 are process cross-sectional views showing characteristic steps in one embodiment of the present invention;

5 is a partial plan view showing in plan view the holes of the plate electrode layer formed in accordance with another embodiment of the present invention.

※ Explanation of code for main part of drawing

1: upper BPSG film 2: PE (Plasma Enhanced) oxide film

3: storage electrode 4: plate electrode

5: buried contact 6: bitline

7, 8: silicon oxide film 9: hole

The present invention for achieving the above object relates to the construction of a DRAM semiconductor device that can prevent the contraction of the plate electrode that causes the separation between the SAC pad and the buried contact, the plate in the state in which the storage electrode and the dielectric film formed Stacking a polysilicon layer to form an electrode, forming a plurality of holes similar to a contact hole in the middle so as not to overlap with the storage electrode through a patterning operation, and filling these holes in a subsequent insulating film stack to form a kind of fixing file And forming a plate by the structure. As a result, even when the plate electrode receives heat and recrystallizes, the plate electrode functions to prevent displacement of each part by contraction.

In the present invention, the holes are generally formed together in the patterning step of the plate electrode, and are usually filled in subsequent USG layer formation. The USG piles formed as described above are integrated with the upper USG layer, so that the polysilicon layer plate that shrinks within the limit of the USG layer is not displaced in the reflow process of softening and flattening a film having a low softening point such as a BPSG film that is subsequently stacked. The electrode can be supported to prevent shrinkage, and even in the case where a displacement occurs together, the accumulation of displacement can be dispersed to prevent the peripheral displacement from expanding.

In addition, the present invention is more effective in this case because the contraction of the plate electrode occurs easily when the interlayer insulating film under the storage electrode layer has a low softening point and easy softening, such as BPSG, as in the conventional example.

However, other materials other than USG may be filled, and the formation of holes may be performed before the subsequent BPSG reflow operation, even if the formation of the plate electrode is performed separately, and the shape is not limited.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

3 and 4 are process cross-sectional views showing characteristic steps in one embodiment of the invention.

In FIG. 3, a MOS transistor structure is formed in a COB-type DRAM, a SAC pad, an interlayer insulating film, and a bit line are formed, and then an upper interlayer insulating film, an etch stop layer, a storage electrode, and a dielectric film are formed, and a plate electrode is formed. A pattern of plate electrodes 4 having a plurality of holes 9 in the middle was formed while the polysilicon to be formed was laminated and then integrated through a patterning operation. The hole is formed so as not to contact the storage electrode 3 or other structures between the periphery of the plate electrode 4 and the storage electrode 3.

In FIG. 4, the USG film silicon oxide film 7 is stacked on the plate electrode 4 in the state of FIG. 3, and the BPSG film silicon oxide film 8 is stacked again. The holes 9 already formed in this process are filled with the USG film-like silicon oxide film 7, and the upper plate-shaped USG film-like silicon oxide film 7 in the reflow step of about 830 ° C after lamination of the BPSG film-like silicon oxide film 8 And the pile of USG film quality filling the hole 9 suppresses the contraction of the plate electrode 4.

Fig. 5 is a partial plan view showing the holes 9 of the plate electrode 4 layer formed according to another embodiment of the present invention in a plan view. In the periphery, which is the maximum displacement region of the integrally formed plate electrode 4, covering the cell block, holes 9 are formed side by side at a high density, and also in the middle of the storage electrode 3, which appears elliptical, in the hole 9 Are formed to disperse the force against the contracting force of the plate electrode 4.

According to the present invention, during the BPSG reflow process, which is used as an interlayer insulating film after forming a plate electrode in a DRAM having a COB structure, the buried contact connected through the storage electrode is inclined while the polysilicon layer plate electrode is contracted, and there is a gap between the SAC pad and the gap. This can prevent the abnormality in the cell transistor function.

Claims (3)

In the method of forming a capacitor of a COB (Capacitor On Bit line) structure memory device, Sequentially forming a storage electrode and a dielectric film on a semiconductor substrate on which an interlayer insulating film including a BPSG (Boro Phosphorous Silicate Glass) film is formed, Stacking polysilicon on the semiconductor substrate including the storage electrode and the dielectric layer to form a plate electrode layer; Patterning the plate electrode layer to form a plate electrode and forming a plurality of holes at positions not overlapping with the storage electrode in a plane; Filling the hole while stacking a USG (Undoped Silicate Glass) film on the plate electrode on which the hole is formed; Stacking and reflowing a BPSG film on the USG film; and forming a capacitor of the semiconductor device. In the method of forming a capacitor of a COB (Capacitor On Bit line) structure memory device, Sequentially forming a storage electrode and a dielectric film on the semiconductor substrate on which the interlayer insulating film is formed, Stacking polysilicon on the semiconductor substrate including the storage electrode and the dielectric layer to form a plate electrode layer; Patterning the plate electrode layer to form a plate electrode and forming a plurality of holes at positions not overlapping with the storage electrode in a plane; Filling the hole while stacking a silicon oxide film on the plate electrode on which the hole is formed; and And depositing a low softening point silicon oxide film having a low relative softening temperature on the silicon oxide film and performing heat treatment at a temperature higher than the softening point of the low softening point silicon oxide film. The method of claim 2, The silicon oxide film is a USG film, the low softening point silicon oxide film is a BPSG film, and the temperature of the heat treatment step is a temperature lower than the softening point of the USG film.