KR20010075945A - Sense amplifier - Google Patents

Abstract

PURPOSE: A sense amplifier is provided, improve a sensing operation speed by detecting voltage difference between the first bit line and the second bit line after discharing the first bit line and the second bit line. CONSTITUTION: A sense amplifier used for an SRAM includes a sense amplifier(10) for sense-amplifying voltage difference between the first and second bit lines in response to a sense signal, and the first pre-charge circuit(MP14) for pre-charging the first bit line with the first voltage. The sense amplifier further has the second pre-charge circuit(MP15) for pre-charging the second bit line with the first voltage, the first discharge circuit(20) for discharging the pre-charged first bit line in response to a control signal activated before the sense amplifier is activated, and the second discharge circuit(30) for discharging the pre-charged second bit line in response to the control signal.

Description

Sense Amplifiers {SENSE AMPLIFIER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to high speed sense amplifiers used in static random access memory (SRAM) devices.

In static random access memory (SRAM), each of the memory cells is connected to one of a plurality of word lines WL arranged in a horizontal direction and bit lines BL and BLB arranged in a vertical direction. One of the word lines is set to a high level by the decoder and the other word lines are set to a low level so that the memory cell is selected. According to the binary information stored in the memory cell selected by the decoder, one of the bit lines BL and BLB of the selected memory cell outputs the same signal as the power supply voltage, and the other outputs a signal lower than the power supply voltage. Data '1' or '0' stored in the selected memory cell is determined by a very small voltage difference between a pair of bit lines connected to the memory cell. This voltage difference is usually from several tens of mV to 100 mV. For example, if the data stored in the memory cell is '1', the potential of the bit line BL is higher than the bit line BLB. If the data stored in the memory cell is '0', the potential of the bit line BL is the bit line. Lower than (BLB). The sense amplifier amplifies this small voltage difference and outputs it.

1 is a circuit diagram showing a conventional sense amplifier circuit, Figure 2 is a timing diagram of the sense amplifier circuit shown in FIG.

The sense amplifier circuit shown in FIG. 1 includes a sense amplifier in the form of a current mirror. When the pair of PMOS transistors PM4 and MP5 are turned on by the low level precharge signal PRECHARGE, the pair of bit lines BL and BLB are precharged to the power supply voltage level. After the precharge signal PRECHARGE signal is deactivated to a high level, a word line connected to a memory cell selected by a decoder (not shown) is set to a high level. When the sense signal SENSE is activated to a high level, a small potential difference between the pair of bit lines BL and BLB is provided to the NMOS transistors MN1 and MN2 and output as an output signal DOUT. If the potential of the bit line BL is high and the potential of the other bit line BLB is low, the NMOS transistor MN1 is turned on and the NMOS transistor MN2 is turned off. Therefore, the low level signal DOUT is output. Therefore, the data stored in the selected memory cell is determined as '1'. As such, the sense amplifier circuit senses and outputs a small potential difference between the pair of bit lines BL and BLB.

With the recent increase in memory capacity, a larger number of memory cells have been integrated into one chip. Increasing the memory cell results in an increase in the junction capacitance of the memory cells, and increases the length of the bit lines BL and BLB connected to the memory cells. This acts to increase the loading of the bit lines BL and BLB. This increase in load increases the discharge time of the bit lines BL and BLB precharged to the supply voltage. Therefore, after the sense amplifier enable signal SAE is activated, it takes a long time until the time point A at which the sense amplifier can sense the voltage difference between the bit lines BL and BLB. This is not a problem for memory devices of small capacity (e.g., 1K bytes or less), but results in a slow detection speed of the sense amplifier in large memory devices of 1K bytes or more.

Accordingly, it is an object of the present invention to provide a high speed sense amplifier of a highly integrated mass memory device.

1 is a circuit diagram showing a conventional sense amplifier circuit;

2 is a timing diagram of the sense amplifier circuit shown in FIG. 1;

3 is a circuit diagram of a current amplifying circuit according to a preferred embodiment of the present invention; And,

4 is a timing diagram of the current amplifier circuit shown in FIG. 3.

* Description of the symbols for the main parts of the drawings *

10: sense amplifier

20: first discharge circuit

30: third discharge circuit

MP14: first precharge transistor

MP15: second precharge transistor

According to an aspect of the present invention for achieving the object of the present invention as described above, the sense amplifier circuit for SRAM: a sense amplifier for sensing and amplifying the voltage difference between the first bit line and the second bit line in response to the sense signal First precharge means for precharging the first bit line to a first voltage, second precharge means for precharging the second bit line to the first voltage, and activated before the sensing signal is activated First discharge means for discharging the first bit line precharged in response to a control signal and second discharge means for discharging the second bit line precharged in response to the control signal.

In a preferred embodiment, the first discharge means comprises: a first NMOS transistor having a drain connected to a power voltage, a source and a gate connected to the control signal, a drain connected to the first bit line, a source, and the control signal; A second NMOS transistor having a connected gate, a drain connected with a source of the second NMOS transistor, a source connected with a ground voltage and a third NMOS transistor having a gate connected with a source of the first NMOS transistor, a source of the first NMOS transistor And a fourth NMOS transistor having a drain connected to the gate and a source connected to the ground voltage.

According to another aspect of the present invention for achieving the object of the present invention, a method for detecting the data of the selected memory cell by detecting the voltage difference between the first bit line and the second bit line connected to the memory cell of the semiconductor memory device First, the first and second bit lines are precharged with a first voltage. Next, the precharged first and second bit lines are discharged. The voltage difference between the first bit line and the second bit line is sensed and amplified.

(Action)

By such a device, a sense amplifier that performs a fast sensing operation is implemented.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 4.

3 is a circuit diagram of a current amplifier circuit according to a preferred embodiment of the present invention, Figure 4 is a timing diagram of the current amplifier circuit shown in FIG.

The sense amplifier circuit shown in FIG. 3 includes a sense amplifier 10 in the form of a current mirror, first and second precharge transistors MP14 and MP15, and first and second discharge circuits 20. 30).

The sense amplifier 10, which detects a voltage difference between the first bit line BL and the second bit line BLB and outputs a sense signal DOUT, may include PMOS transistors MP11, MP12, and MP13 and NMOS transistors. (MN11, MN12, MN13). The drain of the PMOS transistor MP11 is connected to a power supply voltage. A drain of the PMOS transistor MP12 is connected to the power supply voltage, and a gate thereof is connected to its source and a gate of the PMOS transistor MP11. A source-drain current path of the PMOS transistor MP13 is formed between the drains of the PMOS transistors MP11 and MP12, and a gate is connected to the sense amplifier enable signal SAE. A drain of the NMOS transistor MN11 is connected to the source of the PMOS transistor MP11 and a gate is connected to the first bit line BL. A drain of the NMOS transistor MN12 is connected to a source of the PMOS transistor MP12 and a gate is connected to the second bit line BLB. A drain of the NMOS transistor MN13 is connected to the sources of the NMOS transistors MN11 and MN12, a source is connected to a ground voltage, and a gate is connected to the sense amplifier enable signal SAE.

A drain of the first precharge transistor MP14 is connected with a power supply voltage, a source is connected with the first bit line BL, and a gate is connected with a precharge signal PRECHARGE. A drain of the second precharge transistor MP15 is connected to the power supply voltage, a source is connected to the second bit line BLB, and a gate is connected to the precharge signal PRECHARGE.

The first discharge circuit 20 is composed of four NMOS transistors MN21, MN22, MN23, and MN24. A drain of the NMOS transistor MN21 is connected to a power supply voltage and a gate is connected to a discharge control signal DISCHARGE. A drain of the NMOS transistor MN22 is connected to the first bit line BL, and a gate is connected to the discharge control signal DISCHARGE. A drain of the NMOS transistor MN23 is connected with a source of the NMOS transistor MN22, a source is grounded, and a gate is connected with a source of the NMOS transistor MN21. A drain and a gate of the NMOS transistor MN24 are connected to a source of the NMOS transistor MN21 and a source is connected to a ground voltage.

The second discharge circuit 30 has the same circuit configuration as the first discharge circuit 20. That is, the second discharge circuit 30 includes an NMOS transistor MN32 having a drain connected to a power supply voltage, a gate connected to the discharge control signal DISCHARGE, a drain connected to the second bit line BLB, and NMOS transistor MN31 having a gate connected to discharge control signal DISCHARGE, a drain connected to the source of NMOS transistor MN31, a gate connected to the source of NMOS transistor MN32, and a NMOS transistor having a source connected to ground voltage And an NMOS transistor MN34 having a drain and a gate connected to the source of the NMOS transistor MN21 and a source connected to a ground voltage.

Subsequently, the operation of the sense amplifier circuit according to the preferred embodiment of the present invention will be described with reference to FIGS. 3 and 4.

When the first and second precharge transistors PM14 and MP15 are turned on by the precharge signal PRECHARGE signal activated at a low level, the first and second bit lines BL and BLB are connected to a power supply voltage. Precharged to level. After the precharge signal PRECHARGE signal is deactivated to a high level, a word line WL connected to a memory cell selected by a decoder (not shown) is set to a high level. When the word line WL is set at the high level and the discharge control signal DISCHARGE is activated at the high level, all NMOS transistors MN21 and MN22 in the first and second discharge circuits 20 and 30 are activated. , MN23, MN24, MN31, MN32, MN33, MN34) are turned on. Therefore, the voltage levels of the first and second bit lines BL and BLB are rapidly lowered. At this time, the voltage level of any one of the first and second bit lines BL and BLB is higher than the other one according to data stored in a memory cell connected to the first and second bit lines BL and BLB. Lower.

Subsequently, when the sense amplifier enable signal SAE is activated to a high level, the NMOS transistor MN13 in the sense amplifier 10 is turned on to sense the voltage difference between the first and second bit lines BL and BLB. Is amplified. For example, if the potential of the bit line BL is high and the potential of the other bit line BLB is low, the NMOS transistor MN11 is turned on and the NMOS transistor MN12 is turned off. Therefore, the output signal DOUT goes low level. Therefore, the data stored in the selected memory cell is determined as '1'.

In the sense amplifier circuit of the present invention as described above, the discharge control signal DISCHARGE is activated before the sense amplifier enable signal SAE is activated to discharge the first and second bit lines BL and BLB. . Accordingly, as a large number of memory cells are integrated in the semiconductor memory device of the original chip, the first and the same time as the sense amplifier enable signal SAE is activated even when the load of the bit lines BL and BLB is increased. The voltage difference between the second bit lines may be sensed. Thus, the detection speed of the first and second bit line voltage differences of the sense amplifier circuit is improved.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

According to the present invention as described above, the detection speed of the sense amplifier used in the semiconductor memory device is improved.

Claims (3)

In the sense amplifier circuit for SRAM: A sense amplifier for sensing and amplifying a voltage difference between the first bit line and the second bit line in response to the sense amplifier enable signal; First precharge means for precharging the first bit line to a first voltage; Second precharge means for precharging the second bit line to the first voltage; First discharge means for discharging the precharged first bit line in response to a control signal that is activated before the sense amplifier enable signal is activated; And And second discharge means for discharging said second bit line precharged in response to said control signal. The method of claim 1, The first discharge means, A first NMOS transistor having a drain connected to a power supply voltage, a source, and a gate connected to the control signal; A second NMOS transistor having a drain connected to the first bit line, a source, and a gate connected to the control signal; A third NMOS transistor having a drain connected to the source of the second NMOS transistor, a source connected to a ground voltage, and a gate connected to the source of the first NMOS transistor; And And a fourth NMOS transistor having a drain and a gate connected to a source of the first NMOS transistor and a source connected to a ground voltage. A method of sensing data of a selected memory cell by sensing a voltage difference between a first bit line and a second bit line connected to a memory cell of a semiconductor memory device: Precharging the first and second bit lines to a first voltage; Discharging the precharged first and second bit lines; And And sensing and amplifying a voltage difference between the first bit line and the second bit line.