KR20010073502A - A alloy of bonding wire for high strength - Google Patents
A alloy of bonding wire for high strength Download PDFInfo
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- KR20010073502A KR20010073502A KR1020000001934A KR20000001934A KR20010073502A KR 20010073502 A KR20010073502 A KR 20010073502A KR 1020000001934 A KR1020000001934 A KR 1020000001934A KR 20000001934 A KR20000001934 A KR 20000001934A KR 20010073502 A KR20010073502 A KR 20010073502A
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- bonding wire
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- 239000000956 alloy Substances 0.000 title claims abstract description 16
- 229910045601 alloy Inorganic materials 0.000 title claims abstract description 16
- 239000010931 gold Substances 0.000 abstract description 52
- 239000004065 semiconductor Substances 0.000 abstract description 36
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 25
- 229910052737 gold Inorganic materials 0.000 abstract description 25
- 238000007665 sagging Methods 0.000 abstract description 13
- 229910052790 beryllium Inorganic materials 0.000 abstract description 9
- 238000010408 sweeping Methods 0.000 abstract description 9
- 229910052727 yttrium Inorganic materials 0.000 abstract description 8
- 239000013078 crystal Substances 0.000 abstract description 7
- 230000010354 integration Effects 0.000 abstract description 7
- 230000000452 restraining effect Effects 0.000 abstract 1
- 239000011575 calcium Substances 0.000 description 18
- 238000002156 mixing Methods 0.000 description 16
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 9
- 229910052791 calcium Inorganic materials 0.000 description 9
- 229910052788 barium Inorganic materials 0.000 description 8
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 8
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 239000012535 impurity Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 7
- 229910052772 Samarium Inorganic materials 0.000 description 6
- KZUNJOHGWZRPMI-UHFFFAOYSA-N samarium atom Chemical compound [Sm] KZUNJOHGWZRPMI-UHFFFAOYSA-N 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 229910052738 indium Inorganic materials 0.000 description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000654 additive Substances 0.000 description 3
- 230000000996 additive effect Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005275 alloying Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005242 forging Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000615 nonconductor Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000007670 refining Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000746 purification Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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Abstract
Description
본 발명은 집적회로(IC) 패키지의 반도체 칩(Semiconductor Chip)과 리드 프레임(Lead Frame)을 상호 연결하는데 사용되는 금(Au) 본딩 와이어(Bonding Wire)의 합금에 관한 것으로, 특히, 집적도(Integrated)가 높은 반도체 칩의 패드와 리드 프레임사이에 긴 루프를 형성하면서 전기적으로 연결하는 고강도 본딩와이어 합금에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to alloys of Au bonding wires used to interconnect semiconductor chips and lead frames in integrated circuit (IC) packages, and in particular, integrated. It relates to a high strength bonding wire alloy that is electrically connected while forming a long loop between a pad and a lead frame of a high semiconductor chip.
반도체는 도체도 아니고 부도체도 아닌 중간의 성질을 갖는 소자로써, 불순물이 없는 순수한 게르마늄(Ge) 또는 실리콘(Si)의 결정체로 이루어진 얇은 판(Wafer)에 1가를 갖는 도전성 원소를 불순물로 사용하고, 특수한 공정 및 규칙에 의하여 침투시킴으로써, 전자(Electron)의 흐름을 인위적으로 제어할 수 있는 하나의 회로(Circuit)이다.A semiconductor is a device having intermediate properties, which is neither a conductor nor a non-conductor. The semiconductor uses a conductive element having a monovalent value as a impurities in a thin wafer made of pure germanium (Ge) or silicon (Si) crystals without impurities. It is a circuit that can artificially control the flow of electrons by infiltrating by special processes and rules.
상기와 같은 반도체 회로를 하나의 작은 칩(Chip) 속에, 기능별로 무수히 많은 수를 집적(Integrate) 시킨 것이 집적회로(IC: Integrated Circuit)이며, 집적되는 회로의 숫자에 의하여 SSI(Small Scale IC), MMI(Medium Scale IC), LSI(Large Scale IC), VLSI(Very Large Scale IC), ULSI(Ultra Large Scale IC) 등으로 분류하고 있으나, 현재 반도체 제조 기술에서는, 집적도가 기하 급수적으로 증가하므로 집적되는 회로의 숫자로 분류하지 않고 신호처리 속도 또는 기능 별로 구분하는 경향이며, 또한, 집적도의 차이에 의하여 패키지의 종류도 매우 다양하게된다.An integrated circuit (IC) is an integrated circuit (IC) in which a large number of semiconductor circuits are integrated into a single chip, and each function is integrated, and the number of integrated circuits is SSI (Small Scale IC). , Medium Scale IC (MMI), Large Scale IC (LSI), Very Large Scale IC (VLSI), Ultra Large Scale IC (ULSI), etc. There is a tendency to classify by signal processing speed or function without classifying the number of circuits, and the type of package is very diverse due to the difference in the degree of integration.
상기와 같이, 반도체 칩의 크기는 일정하고, 집적된 회로의 숫자는 기하급수적으로 증가하므로, 집적도가 높은 반도체 칩의 신호 입출력을 위한 단자 또는 칩패드(Chip Pad)는, 크기가 작아 지면서, 간격도 매우 작고 협소하므로 리드프레임과 연결하는 본딩와이어의 굵기도 가늘어져야 한다.As described above, since the size of the semiconductor chip is constant and the number of integrated circuits increases exponentially, terminals or chip pads for signal input / output of a semiconductor chip having a high degree of integration are smaller in size and spaced apart. In addition, the thickness of the bonding wire connecting the lead frame should be thin because it is very small and narrow.
또한, 집적도가 높은 반도체 칩의 칩패드와 대응되는 리드 프레임은 상기 칩패드의 숫자만큼 리드 프레임(Lead Frame)을 배열하여야 하므로, 상기 리드 프레임이 배열되는 면적에 의하여, 배열되는 길이가 길어지고 따라서, 상기 반도체 칩과 리드 프레임과의 거리가 상대적으로 길어지게 되며, 이러한 현상은 집적도가 커지면 커질수록 리드프레임을 사용하는 패키지에서는 더 심하게 나타나게 된다.In addition, the lead frame corresponding to the chip pad of the semiconductor chip having a high degree of integration has to arrange a lead frame by the number of the chip pads. Therefore, the length of the lead frame is increased according to the area in which the lead frame is arranged. The distance between the semiconductor chip and the lead frame becomes relatively long, and this phenomenon becomes more severe in a package using the lead frame as the degree of integration increases.
따라서, 상기와 같이 집적도가 높아 조밀해지는 칩패드와 리드프레임을 전기적으로 연결하는 본딩 와이어는 그 굵기 또는 직경(Diameter)이 더 작아야 되면서도 높은 전송속도의 처리 신호를 전송할 수 있도록 비저항 또는 저항률(Resistivity)이 작아야 되며, 긴 거리를 배선하는 루프(Loop)의 형상에 처짐(Sagging) 및 쏠림(Sweeping)이 적음으로써, 루프 사이에 전기적으로 접촉하는 쇼트(Short)가 발생하지 않아야 한다.Therefore, as described above, the bonding wire electrically connecting the chip pad and the lead frame, which has a high density, has a specific resistance or resistivity to transmit a processing signal having a high transmission speed while having a smaller thickness or diameter. This should be small, and sagging and sweeping in the shape of the loop for wiring the long distances should be small, so that a short in electrical contact between the loops should not occur.
이하, 첨부된 도면을 이용하여 종래 기술에 의한 반도체 패키지용 본딩와이어를 설명한다.Hereinafter, the bonding wire for a semiconductor package according to the prior art will be described with reference to the accompanying drawings.
도1은 일반적인 반도체 패키지의 본딩 와이어 연결 상태를 도시한 모사도 이고, 도2는 종래 기술에 의한 고집적 반도체 칩패드와 리드 프레임 사이에 배선된 본딩 와이어의 상태를 확대 도시한 모사도 이다.FIG. 1 is a schematic view showing a bonding wire connection state of a general semiconductor package, and FIG. 2 is an enlarged view illustrating a state of bonding wires wired between a highly integrated semiconductor chip pad and a lead frame according to the related art.
상기 첨부된 도1을 참조하면, 일반적인 반도체 패키지는, 실리콘(Si) 또는 게르마늄(Ge) 등의 부도체를 얇은 기판(Substrate)으로 하여 많은 수의 전자회로가 별도의 공정에 의하여 집적(Integrated)된 집적회로(IC)로 이루어지는 반도체 칩(10)과, 상기 반도체 칩(10)위에 형성되며 각종 신호의 입출력을 위하여 단자 역할을 하는 칩패드(20)와, 상기 반도체 칩(10)과 전기적으로 연결되어 각종 신호를 외부회로에 직접(Directly) 입출력하는 다수의 리드프레임(40)과, 상기 칩패드(20)와 리드프레임(40) 사이를 전기적으로 접촉하는 것으로, 불순물이 극히 적고 높은 고순도의 금(Au)을 인발 가공하여 제조되는 본딩 와이어(30)로 구성된다.Referring to FIG. 1, a general semiconductor package includes a plurality of electronic circuits integrated by a separate process using a non-conductor such as silicon (Si) or germanium (Ge) as a thin substrate. A semiconductor chip 10 formed of an integrated circuit (IC), a chip pad 20 formed on the semiconductor chip 10 and serving as a terminal for input / output of various signals, and electrically connected to the semiconductor chip 10. And a plurality of lead frames 40 which directly input and output various signals to an external circuit, and the electrical contact between the chip pad 20 and the lead frames 40, and have extremely low impurities and high purity gold. It consists of the bonding wire 30 manufactured by drawing (Au).
상기 본딩 와이어(30)는, 상기 첨부된 도2와 같이, 상기 본딩 와이어의 일측 끝 부분을 방전에 의하여 용융 시킴으로써 소정의 크기로 형성되는 볼(Ball)(32)과, 상기 볼(32)과 본딩 와이어(30)의 연결부분인 네크(Neck)(34)로 이루어진다.As shown in FIG. 2, the bonding wire 30 may include a ball 32 and a ball 32 formed to a predetermined size by melting one end portion of the bonding wire by discharge. It is composed of a neck (34) that is a connection portion of the bonding wire (30).
이하, 상기와 같이 첨부된 도면을 참조하여 종래 기술에 의한 반도체 패키지용 본딩 와이어(30)를 상세히 설명하면, 실리콘(Si) 또는 게르마늄(Ge) 등으로 이루어진 기판(Substrate) 위에 도전성 불순물 원소를 별도의 공정 및 특정한 규칙에 의하여 침투시켜, 전기적 신호의 흐름을 제어하는 회로(Circuit)가 대규모로 집적(Integrated)되고, 동시에 상기 회로에서 처리되는 신호의 입출력을 위하여 단자 또는 칩패드(20)가 조밀한 간격으로 일체 형성되는 반도체 칩(Semiconductor Chip)(10)과, 상기 반도체 칩(10)에서 생성된 신호를 외부의 회로(Circuit)로 직접(Directly) 출력하고 동시에 외부의 회로로부터 신호를 직접(Directly) 인가 받는 리드프레임(40)과의 사이를 금(Au)으로 이루어진 상기 본딩 와이어(30)로 배선(Wiring)한다.Hereinafter, the semiconductor package bonding wire 30 according to the prior art will be described in detail with reference to the accompanying drawings as described above. A conductive impurity element is separately formed on a substrate made of silicon (Si), germanium (Ge), or the like. The circuit for controlling the flow of the electrical signal by infiltrating by the process and specific rules of the circuit is integrated on a large scale, and at the same time, the terminal or the chip pad 20 is dense for the input / output of the signal processed in the circuit. The semiconductor chip 10 integrally formed at an interval and the signal generated by the semiconductor chip 10 are directly output to an external circuit, and at the same time, the signal is directly output from the external circuit. Directly is wired with the bonding wire 30 made of gold (Au) between the lead frame 40 to be applied.
상기 본딩 와이어(30)는 불순물이 없는 고순도인 99.999 로 정제되므로써 전기 저항이 작은 금(Au)에 베릴리움(Be)과 칼슘(Ca) 그리고 파라듐(Pd) 또는 바륨(Ba)을 ppm 무게 단위로 혼합한 것으로써, 원형 단조 및 인발 가공 그리고, 열처리하여 배선하기 적합한 기계적 특성을 갖도록 한 것이다.Since the bonding wire 30 is purified to 99.999, which is high purity without impurities, beryllium (Be), calcium (Ca), palladium (Pd), or barium (Ba) in gold (Au) having a low electrical resistance is measured in ppm. By mixing, it has a mechanical characteristic suitable for circular forging, drawing, heat processing, and wiring.
상기 반도체 칩(10)의 패드(20)에 접합되는 본딩 와이어(30)는, 일측 끝단 부분을, 상기 도면에 도시되지 않은 방전 가공부를 통과시킴으로써, 용융된 상태의 볼(Ball)(32)이 형성되도록 하고, 상기 용융 상태의 볼(32)을 상기 칩패드(20)위에 접착시킴으로써, 상기 용융된 볼(32)이 상기 칩패드(20)와 용융 접합된다.In the bonding wire 30 bonded to the pad 20 of the semiconductor chip 10, a ball 32 in a molten state is formed by passing one end portion through an electric discharge machining part not shown in the drawing. And the molten ball 32 is melt-bonded with the chip pad 20 by bonding the molten ball 32 onto the chip pad 20.
상기와 같은 본딩 와이어(30)는 일측 끝단에 용융 형성된 볼(32)에 의하여 칩패드(20)와 용융 접합되고, 상기 해당되는 리드 프레임(40)의 위치까지 적정한 높이 및 길이로 루프(Loop)를 형성한 후, 반대측 끝단은 압력이 인가되어 상기 해당되는 리드프레임(40)에 압착 접합된다.The bonding wire 30 as described above is melt-bonded with the chip pad 20 by a ball 32 fused at one end thereof, and looped at an appropriate height and length to a position of the corresponding lead frame 40. After forming, the opposite end is press-bonded to the corresponding lead frame 40 by applying pressure.
상기와 같은 종래 기술의 본딩 와이어(30)를 사용하여 칩패드(20) 및 리드프레임(40)에 접합되어 루프(Loop)를 형성하는 본딩 와이어(30)의 접합 상태를 일 실시예로서, 상기 첨부된 도2에 모사 하였고, 상기 도1은 해당 칩패드(20)와 리드 프레임(40)이 본딩 와이어(30)로 루프가 형성되어 배선 완료된 상태의 모사도 이며, 상기 본딩 와이어(30)가 배선 완료된 상태의 상부를 기계적 충격 등으로 보호하기 위하여 수지물 또는 세라믹 등으로 밀폐시킴으로서 패키지(Package)가 완성된다.The bonding state of the bonding wire 30 bonded to the chip pad 20 and the lead frame 40 by using the bonding wire 30 of the prior art as described above to form a loop as an embodiment, 2 is a schematic diagram of a state in which the chip pad 20 and the lead frame 40 are looped with the bonding wires 30 and the wiring is completed, and the bonding wires 30 are connected to each other. The package is completed by sealing the upper part of the completed wiring state with a resin material or ceramics in order to protect it from mechanical impact or the like.
상기 반도체 칩(10)은 집적도가 높아지면서 많은 숫자의 회로가 실장 되고, 상기 회로에 입출력되는 신호를 위한 칩패드(20)도 동시에 증가하게 되지만, 한정된 면적에 많은 수의 칩패드(20)를 배치하기 위해서는, 상기 칩패드(20)의 크기를 작게 하여 조밀한 간격으로 배치하여야 한다.Although the semiconductor chip 10 has a higher integration degree, a large number of circuits are mounted, and the chip pads 20 for signals input and output to the circuits increase simultaneously, but a large number of chip pads 20 are limited in a limited area. In order to arrange, the chip pads 20 should be made small in size and arranged at close intervals.
또한, 상기 리드 프레임(40)은 외부회로와 직접 접촉하기 위한 단자로써, 그크기(Size)를 줄이는데 한계가 있으므로, 칩패드와 대응되는 리드 프레임의 숫자 만큼 넓은 면적이 필요하게 된다.In addition, since the lead frame 40 is a terminal for directly contacting an external circuit, there is a limit in reducing the size, and thus, an area as large as the number of lead frames corresponding to the chip pads is required.
상기 첨부된 도1을 참조하여 다시 설명하면, 일정한 크기를 갖는 반도체 칩(10)은 일측 변 'A'의 길이를 그대로 유지하고서도, 칩패드(20)의 크기를 작게 하므로써 많은 수의 칩패드(20)를 배치 할 수 있으나, 리드 프레임(40)은 외부회로와 접촉되는 최소한의 크기를 확보해야 하므로, 많은 숫자의 리드 프레임을 배치하기 위하여는 패키지(50)의 일측변 'C'의 길이가 길어지게 되고, 동시에 칩패드(20)와 리드 프레임(40)사이의 거리 'B'가 길어지게 된다.Referring to the attached FIG. 1 again, the semiconductor chip 10 having a constant size has a large number of chip pads by reducing the size of the chip pad 20 while maintaining the length of one side 'A'. 20) can be arranged, but since the lead frame 40 must secure a minimum size in contact with an external circuit, in order to arrange a large number of lead frames, the length of one side 'C' of the package 50 is increased. At the same time, the distance 'B' between the chip pad 20 and the lead frame 40 is increased.
상기와 같이 칩패드(20)와 리드 프레임(40) 사이가 길어진 패키지(50)에서 종래의 기술에 의한 본딩 와이어(30)로 상기 칩패드(20)와 리드 프레임(40)을 연결하는 경우, 강도가 부족하여 상기 첨부된 도2와 같이, 루프(Loop)가 처지거나(Sagging) 또는 쏠리는(Sweeping) 현상(36)이 발생하게 되고 인접한 루프와 접촉되는 쇼트(Short) 현상이 발생하는 문제가 있었다.When the chip pad 20 and the lead frame 40 are connected to each other by the bonding wire 30 according to the related art in the package 50 in which the chip pad 20 and the lead frame 40 are elongated as described above, Insufficient strength results in a loop 36 sagging or sweeping 36 and a short circuit contacting an adjacent loop as shown in FIG. 2. there was.
본 발명은, 상온 및 고온에서 파단 강도가 우수하며, 처짐(Sagging) 및 쏠림(Sweeping) 현상이 개선되어 형성된 루프의 모양이 변하지 않고, 비저항 성분이 변하지 않아, 본딩 와이어의 직경을 작게 할 수 있음과 동시에 길이를 길게 하며, 볼의 형상이 양호한 고집적 반도체 패키지용 고강도 본딩 와이어 합금을 제공하는 것이 그 목적이다.The present invention is excellent in breaking strength at room temperature and high temperature, sagging and sweeping is improved, the shape of the formed loop does not change, the resistivity component does not change, it is possible to reduce the diameter of the bonding wire In addition, the object of the present invention is to provide a high strength bonding wire alloy for a highly integrated semiconductor package having a long length and good ball shape.
도1 은 일반적인 반도체 패키지의 본딩 와이어 연결 상태를 도시한 모사도 이고,1 is a schematic diagram showing a bonding wire connection state of a general semiconductor package;
도2 는 종래 기술에 의한 고집적 반도체 칩패드와 리드 프레임 사이에 배선된 본딩 와이어의 상태를 확대 도시한 모사도 이고,2 is an enlarged schematic diagram showing a state of a bonding wire wired between a highly integrated semiconductor chip pad and a lead frame according to the prior art;
도3은 본 발명 기술에 의한 본딩 와이어를 사용한 루프 형상 도시도 이고,3 is a loop shape diagram using a bonding wire according to the present invention,
도4 는 볼에 수축공이 발생한 형상 도시도 이다.4 is a diagram illustrating a shape in which shrinkage holes are generated in a ball.
** 도면의 주요 부분에 대한 부호 설명 **** Explanation of symbols on the main parts of the drawing **
10 : 반도체 칩 20 : 패드10 semiconductor chip 20 pad
30,36 : 본딩 와이어 31 : 수축공30,36: bonding wire 31: shrinkage hole
32 : 볼 34 : 네크32: ball 34: neck
40 : 리드 프레임 50 : 패키지40: lead frame 50: package
상기와 같은 목적을 달성하기 위하여 안출한 본 발명은, 베릴륨(Be) 의 무게비 함유량이 1 내지 20 ppm이고, 칼슘(Ca) 의 무게비 함유량은 1 내지 50 ppm이며, 바륨(Ba) 의 무게비 함유량은 1 내지 30 ppm 으로서 상기 원소중 한가지 이상이 첨가되고, 이트륨(Y) 의 무게비 함유량은 1 내지 30 ppm이며, 사마륨(Sm) 의 무게비 함유량은 1 내지 40 ppm이고, 인듐(In) 의 무게비 함유량은 1 내지 20 ppm이며, 인(P)의 무게비 함유량은 1 내지 10 ppm 으로서 상기 원소중 한가지 이상이 첨가되고, 잔여량은 고순도의 금(Au) 으로 구성되는 고강도 본딩 와이어용 합금을 특징으로 한다.In the present invention devised to achieve the above object, the weight ratio content of beryllium (Be) is 1 to 20 ppm, the weight ratio content of calcium (Ca) is 1 to 50 ppm, and the weight ratio content of barium (Ba) is 1 to 30 ppm of one or more of the above elements are added, the weight ratio content of yttrium (Y) is 1 to 30 ppm, the weight ratio content of samarium (Sm) is 1 to 40 ppm, and the weight ratio content of indium (In) is It is 1 to 20 ppm, the weight ratio content of phosphorus (P) is 1 to 10 ppm, and at least one of the above elements is added, and the remaining amount is characterized by an alloy for high strength bonding wire composed of high purity gold (Au).
이하, 본 발명에 의하여 큰 집적도의 반도체 패키지용 고강도 본딩 와이어 합금을 상기 첨부된 도면을 참조하여 설명한다.Hereinafter, the high-strength bonding wire alloy for a semiconductor package of a large degree of integration according to the present invention will be described with reference to the accompanying drawings.
도3은 본 발명 기술에 의한 본딩 와이어를 사용한 루프 형상 도시도 이고, 도4 는 볼에 수축공(Dimple)이 발생한 형상 도시도 이다.3 is a diagram illustrating a loop shape using a bonding wire according to the present invention, and FIG. 4 is a diagram illustrating a shape in which shrinkage holes are formed in a ball.
상기와 같은 구성의 본 발명에 의한 반도체 패키지용 고강도 본딩 와이어의 합금은, 베릴리움(Be: Beryllium), 칼슘(Ca: Calcium), 바륨(Ba: Barium) 중에 한가지 이상을 첨가원소로 함유하며, 첨가되는 총 함량은 1 내지 50 중량 ppm으로 한정되어 함유하고,The alloy of the high-strength bonding wire for a semiconductor package according to the present invention having the above-described configuration contains one or more of beryllium (Be: Beryllium), calcium (Ca: Calcium), and barium (Ba: Barium) as an additional element, and Total content is limited to 1 to 50 ppm by weight,
또한, 이트륨(Y: Yttrium), 사마륨(Sr: Samarium), 인듐(In: Indium), 인(P: Phosphorus) 중에 한가지 이상을 첨가원소로 함유하며, 첨가되는 총 함량은 1 내지 50 중량 ppm 으로 한정되어 함유하며,In addition, one or more of yttrium (Y: yttrium), samarium (sr: samarium), indium (in :), and phosphorus (p: phosphorus) may be added as an additive element, and the total content may be 1 to 50 ppm by weight. Contains a limited amount,
상기 첨가원소의 전체 함유량은 2 내지 100 중량 ppm 으로 제한되고,The total content of the additive element is limited to 2 to 100 ppm by weight,
잔여량은 99.999 이상의 고순도의 금(Au)으로 이루어져 구성된다.The remainder consists of high purity gold (Au) of more than 99.999.
이하, 상기와 같은 구성의 본 발명에 의한 반도체 패키지용 고강도 본딩 와이어 합금을 상기 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a high strength bonding wire alloy for a semiconductor package according to the present invention having the above configuration will be described in detail with reference to the accompanying drawings.
본 발명에서 사용되는 반도체 패키지용 본딩 와이어(Bonding Wire)는, 주재료로서, 불순물이 적은 고순도의 금(Au)을 사용한다.The bonding wire for a semiconductor package used by this invention uses high purity gold (Au) with few impurities as a main material.
상기 금(Au)을 주재료로써 사용하는 이유는, 현존하는 순수한 금속성 원소 중에서 가장 전기적 저항이 작은 특징이 있기 때문이다.The reason why the gold (Au) is used as the main material is that it has the smallest electrical resistance among the pure metal elements present.
상기 금(Au)은 불순물을 제거하고 순도를 높이기 위하여, 전기 화학적 정제방법 및 국부 용해 정제방법의 2 단계 정제를 거침으로써, 99.999 이상의 고 순도 금(Au)을 얻을 수 있고, 금(Au)은 전기적 저항이 가장 적어, 전자회로의 신호 전달용으로는 가장 좋은 도체이고, 또한, 연성이 우수하여 길게 늘리거나 넓게 펼칠 수 있는 우수한 특징이 있는 반면에 주변온도의 변화에 민감하여 고온에서 쉽게 늘어나고, 기계적인 강도가 약하므로, 본딩 와이어(30)로 제작하여 반도체 패키지(Package)에 배선하였을 경우, 배선이 형성된 루프(Loop)가 쳐지는 처짐 현상, 루프가 쓰러지는 쏠림 현상 등을 방지하기 위하여, 금(Au)의 우수한 전기 전도성 상태를 유지하는 범위에서의 다른 원소를 ppm 단위의 중량비로 혼합 또는 도판트(Dopant)하여 사용한다.In order to remove impurities and increase purity, the gold (Au) is subjected to two-stage purification of the electrochemical refining method and the locally dissolved refining method to obtain high purity gold (Au) of 99.999 or more, and gold (Au) It has the lowest electrical resistance, which is the best conductor for signal transmission of electronic circuits, and it has excellent ductility, so it has an excellent feature of being able to extend or spread widely, while being sensitive to changes in ambient temperature, it easily increases at high temperatures, Since the mechanical strength is weak, when the wires are manufactured by the bonding wires 30 and wired to the semiconductor package, in order to prevent sagging or falling of the loops, the loops in which the wirings are formed are collapsed. Other elements in the range that maintain the excellent electrical conductivity of (Au) are mixed or doped in a weight ratio in ppm.
상기와 같이 합금 재료로 사용되는 원소의 혼합 비율 및 해당원소의 특징을 설명하면 다음과 같다.Referring to the mixing ratio and the characteristics of the element used as the alloying material as described above are as follows.
베릴륨(Be: Beryllium)은 상온 및 고온에서 본딩 와이어(30)의 인장 강도를향상시키고, 본딩 와이어(30)의 일측 끝단이 방전에 의하여 용융 형성되는 볼(Ball)(32)의 결정 입자를 미세화 시켜 루프(Loop)가 형성된 후의 처짐(Sagging) 또는 쏠림(Sweeping)과 같은 루프형상의 굴곡 또는 변형을 억제하는 작용을 한다.Beryllium (Be: Beryllium) improves the tensile strength of the bonding wire 30 at room temperature and high temperature, and refines the crystal grains of the ball 32 in which one end of the bonding wire 30 is melt-formed by discharge. This is to suppress the bending or deformation of the loop shape such as sagging or sweeping after the loop is formed.
상기 베릴륨(Be)은 금(Au)과 혼합되는 중량 또는 무게 혼합 비율이 1 ppm 이하인 경우에는 첨가 효과가 없으며, 중량 혼합 비율이 10 ppm 을 넘으면, 오버 도핑(Over Doping)에 의하여 네크(Neck)(34) 부분에 취성 파단(Brittle Failure)이 발생하게 되므로, 1 내지 10 ppm 범위의 중량비로 한정하여 첨가 또는 혼합한다.The beryllium (Be) has no added effect when the weight or the weight mixing ratio of 1 ppm or less is mixed with gold (Au), and if the weight mixing ratio is more than 10 ppm, the neck by over doping (Over Doping) Brittle failure occurs in the (34) part, so it is added or mixed only in the weight ratio in the range of 1 to 10 ppm.
칼슘(Ca: Calcium)은 본딩 와이어(30)의 열적 저항을 높여 주며, 재결정 온도를 상승시키고, 상온 및 고온에서의 기계적 인장강도를 향상시킬 뿐 아니라, 긴 루프(Long Loop)에서의 처짐(Sagging)이 억제되고 패키징(Packaging) 하는 경우의 눌려서 발생하는 쏠림(Sweeping) 현상이 적어 루프 사이에 전기적으로 접촉하는 쇼트(Short) 현상을 방지하며, 볼 네크(34) 부분의 결정 성장을 억제하고 항복강도를 상승시켜 인성을 커지게 하므로써, 볼 네크(34) 부분의 취성 파단(Brittle Failure)이 감소하고, 특히, 본딩 와이어(30)의 직경이 작아도 볼 네크(34)의 취성 파단(Brittle Failure)이 발생하지 않도록 한다.Calcium (Ca) increases the thermal resistance of the bonding wire 30, increases the recrystallization temperature, improves the mechanical tensile strength at room temperature and high temperature, as well as sagging in long loops. ) Is suppressed and there is little pressing phenomenon during packaging, which prevents shorting of electrical contact between loops, suppresses the crystal growth of the ball neck 34 and yields By increasing the strength to increase toughness, brittle failure of the portion of the ball neck 34 is reduced, and in particular, brittle failure of the ball neck 34 even when the diameter of the bonding wire 30 is small. This should not happen.
또한, 상기 칼슘(Ca)은 금(Au)의 탄성을 높여 주어 배선된 본딩 와이어(30)의 루프(Loop)가 주변 환경에 의하여 변형되어도 원래의 형상으로 복원되도록 하는 작용을 하고, 특히, 상기 알루미늄(Al)을 주재료로 하는 칩패드(20)와 본딩 와이어(30)사이에 원자 이동에 의하여 고온에서 심하게 발생하는 커켄달 보이드(Kirkendall Void) 현상을 억제한다.In addition, the calcium (Ca) acts to increase the elasticity of the gold (Au) to restore the original shape even if the loop of the bonded wire 30 is deformed by the surrounding environment, in particular, the The Kirkendall Void phenomenon which is severely generated at high temperature by the movement of atoms between the chip pad 20 mainly made of aluminum (Al) and the bonding wire 30 is suppressed.
상기 칼슘(Ca)은 금(Au)과 혼합되는 중량 또는 무게 혼합 비율이 1 ppm 이하에서는 첨가 효과가 거의 없으며, 중량 혼합 비율이 50 ppm 을 넘으면, 오버 도핑(Over Doping)이 되어, 상기 첨부된 도4에서와 같이 방전에 의하여 형성된 프리 에어 볼(Ball)(32)의 밑 부분이 찌그러지는 수축공(Dimple) 현상이 나타나 진구 형성이 어렵게 되고, 볼(32)의 표면에 산화피막이 형성되므로써, 상기 칩패드(20)와의 용융접합이 취약하게 되므로, 1 내지 50 ppm 범위의 중량비로 한정하여 혼합 또는 첨가한다.The calcium (Ca) is hardly added when the weight or the weight mixing ratio of 1 ppm or less mixed with gold (Au), and when the weight mixing ratio is more than 50 ppm, the over doping (Over Doping), the attached As shown in Fig. 4, the contraction hole (Dimple) phenomenon in which the lower part of the free air ball 32 formed by the discharge is distorted appears, making it difficult to form a true sphere, and since an oxide film is formed on the surface of the ball 32, Since the melt bonding with the chip pad 20 becomes fragile, the mixing or addition is limited to the weight ratio in the range of 1 to 50 ppm.
바륨(Ba: Barium)은 고온에서 상기 본딩 와이어(30)의 인장 강도를 향상시키고, 본딩 와이어(30)의 인발 후에 열처리하는 과정에서 결정의 조대화 방지 및 전체적으로 미세 결정립이 형성되도록 하며, 조직 내부의 격자를 변형시켜 전위의 이동을 방해하므로, 긴 루프(Long Loop)의 처짐(Sagging) 및 쏠림(Sweeping)을 방지하는 기능을 한다.Barium (Ba: Barium) improves the tensile strength of the bonding wire 30 at a high temperature, prevents coarsening of crystals and forms fine grains as a whole during heat treatment after drawing the bonding wire 30, and internally inside a tissue. It prevents sagging and sweeping of long loops by deforming the lattice of and hinders the movement of dislocations.
상기 바륨(Ba)은 금(Au)과 혼합되는 무게 혼합 비율이 1 ppm 이하에서는 첨가 효과가 거의 없으며, 중량 혼합 비율이 50 ppm 을 넘으면, 오버 도핑(Over Doping) 되어, 본딩 와이어(30)가 너무 경화되므로써 루프의 형상이 불 균일하게 되고, 또한, 볼(32)을 칩패드(20)에 접착하는 과정에서 반도체 칩(10)이 파손되는 칩크랙(Chip Crack)을 유발하므로, 1 내지 50 ppm 범위의 중량비로 한정하여 혼합 또는 첨가한다.The barium (Ba) has almost no addition effect when the weight mixing ratio mixed with gold (Au) is 1 ppm or less, and when the weight mixing ratio exceeds 50 ppm, the doping is over doped, so that the bonding wire 30 is Due to the hardening, the shape of the loop becomes uneven, and also causes chip cracks in which the semiconductor chip 10 is broken in the process of adhering the balls 32 to the chip pads 20. Mix or add to the weight ratio in the ppm range.
상기에서 설명한 바와 같이, 상기 베릴륨(Be), 칼슘(Ca) 및 바륨(Ba) 중에서 한가지 이상의 원소를 첨가하며, 첨가되는 원소의 총합이 1 내지 50 ppm 으로 한정하는 것이 중요하다.As described above, at least one element of the beryllium (Be), calcium (Ca) and barium (Ba) is added, and it is important to limit the total of the added elements to 1 to 50 ppm.
이트륨(Y: Yttrium)은 금(Au)의 내열성 또는 연화온도를 향상시키고, 동시에 볼(32) 형성시에 결정립의 조대화를 억제시키며 본딩 와이어(30)의 인장강도를 향상시킴으로써, 루프(Loop)의 처짐(Sagging)을 억제하는 작용을 하는 것으로써, 단독 첨가시보다 상기 칼슘(Ca)과 복합 첨가시에 그 효과가 더 크며, 금(Au)과 혼합되는 중량 또는 무게 혼합 비율이 1 ppm 이하인 경우에는 첨가 효과가 거의 없고, 중량 혼합 비율이 50 ppm 을 넘으면, 오버 도핑(Over Doping)에 의하여 특성의 향상이 없으며, 오히려 볼(32) 형성시에 상기 첨부된 도4에서와 같이 수축공(Dimple)(31)이 발생하고, 볼(32)의 경도가 증가하여 상기 반도체 칩(10)이 파손되는 칩크랙(Chip Crack)을 유발 할 수 있으므로, 1 내지 50 ppm 범위의 중량비로 한정하여 혼합 또는 첨가한다.Yttrium (Y: Yttrium) improves the heat resistance or softening temperature of gold (Au), at the same time suppresses coarsening of crystal grains when forming the balls 32, and improves the tensile strength of the bonding wire 30, thereby providing a loop. It has the effect of suppressing sagging of), and its effect is greater when combined with calcium (Ca) than when added alone, and the weight or weight mixing ratio mixed with gold (Au) is 1 ppm. In the case of the following, there is almost no addition effect, and if the weight mixing ratio exceeds 50 ppm, there is no improvement in characteristics due to over doping, but rather, as shown in FIG. (Dimple) 31 may occur, and the hardness of the ball 32 may be increased to cause chip cracks in which the semiconductor chip 10 is broken, and thus, limited to a weight ratio of 1 to 50 ppm. Mix or add.
사마륨(Sm: Samarium)은 금(Au)의 인장강도를 향상시키고, 연화온도를 높여 열적 안정성을 증가시키며, 볼(32) 형성시에 열에 의한 결정립 조대화를 방지하는 기능으로써, 칼슘(Ca) 및 이트륨(Y)과 함께 첨가되었을 경우에 효과가 크고, 금(Au)과 혼합되는 중량 또는 무게 혼합 비율은 3 내지 50 ppm 범위의 중량비로 한정하여 혼합 또는 첨가한다.Samarium (Sm: Samarium) is a function of improving the tensile strength of gold (Au), increasing the softening temperature to increase thermal stability, and prevents grain coarsening by heat when forming the balls (32). And when added together with yttrium (Y), the effect is great, and the weight or weight mixing ratio to be mixed with gold (Au) is limited to the weight ratio in the range of 3 to 50 ppm and mixed or added.
인듐(In: Indium)은 금(Au)의 결정립을 미세화 시키고, 인장 강도를 향상시키며 루프(Loop)를 길고 높게 형성하여도 형태가 변형되지 않도록 하는 기능으로써, 금(Au)과 혼합되는 중량 또는 무게 비율이 1 ppm 이하인 경우에는 효과가 거의 없으며, 중량 혼합 비율이 50 ppm 을 넘으면, 오버 도핑(Over Doping)에 의하여 인성이 지나치게 증가하므로, 1 내지 50 ppm 범위의 중량비로 한정하여 혼합한다.Indium (In: Indium) is a function that makes the crystal grains of gold (Au) finer, improves tensile strength, and prevents deformation even when long and high loops are formed. When the weight ratio is 1 ppm or less, there is almost no effect. When the weight mixing ratio exceeds 50 ppm, the toughness is excessively increased due to over doping, and the mixing is limited to the weight ratio in the range of 1 to 50 ppm.
인(P: Phosphorus)은 금(Au)에 균일하게 분산 고용되고 금(Au) 격자에 응력장을 발생시켜 상온에서의 강도를 향상시키는 것으로써, 혼합되는 중량 또는 무게 비율을 1 내지 50 ppm 범위로 한정하여 첨가한다.Phosphorus (P) is uniformly dispersed and dissolved in gold (Au) and generates a stress field in the gold (Au) lattice to improve strength at room temperature, thereby mixing the weight or weight ratio in the range of 1 to 50 ppm. It adds limitedly.
상기에서 설명한바와 동일하게 이트륨(Y), 사마륨(Sm), 인듐(In), 인(P) 중에서 한가지 이상을 첨가 원소로 함유하고, 상기 첨가 원소의 총 중량비는 50 ppm을 초과하지 않도록 제한한다.As described above, at least one of yttrium (Y), samarium (Sm), indium (In), and phosphorus (P) is contained as an additional element, and the total weight ratio of the additional element is limited not to exceed 50 ppm. .
다시 설명하면, 첨가되는 모든 원소의 총 함유량은 2 내지 100 ppm을 초과하지 않고, 잔여량은 고순도의 금(Au)으로 이루어진다.In other words, the total content of all the added elements does not exceed 2 to 100 ppm, and the remaining amount is made of high purity gold (Au).
이하 상기와 같은 첨가원소를, 일 실시예로서, 중량 혼합 비율을 변경하면서, 혼합한 금(Au) 합금의 본딩 와이어(30)에 의하여 실험한 결과를 구체적으로 설명한다.Hereinafter, the result of experimenting with the bonding wire 30 of the mixed gold (Au) alloy while changing the weight mixing ratio as an example of the above-mentioned addition element is demonstrated concretely.
실시예;Example;
순도 99.999 이상으로 정제된 금(Au)에 상기의 합금 재료인 첨가원소를 하기 표1 과 같이 중량비 ppm 으로 혼합하여 용해한 후에 원형단조 및 직경(Diameter) 30 ㎛의 와이어(Wire)로 인발 가공하고 기계적 특성을 향상 시키기 위하여 열처리하여 제조하였다.After adding and dissolving the additive element, which is the alloying material, to the gold (Au) having a purity of 99.999 or more, in a weight ratio of ppm as shown in Table 1 below, it is drawn and processed into a circular forging and a wire having a diameter of 30 μm. It was prepared by heat treatment to improve the properties.
상기와 같은 조성비로 제조된 본딩 와이어(Bonding Wire)를 이용하여 실험하므로써, 하기 표2에 표시한 것과 같은 결과 값을 확인하였다. 하기 표2에서 본딩와이어의 기계적 성질인 파단강도(gf: Gram Force)는 상온 및 고온에서 실험하여 측정하였으며, 본딩 와이어로 이루어진 루프의 길이 별로 안정성을 실험하였으며, 루프의 쏠림(Sweeping) 정도, 볼 형상 및 비저항(Resistivity)을 실험하여 측정하였고, 'O'는 양호한 상태, '△'는 보통상태, 'X'는 불량한 상태를 표시한 것이다.By using a bonding wire (Bonding Wire) prepared in the composition ratio as described above, the result value as shown in Table 2 was confirmed. In Table 2, the mechanical properties of the bonding wires (gf: Gram Force) were measured by testing at room temperature and high temperature. The shape and resistivity were measured and measured, 'O' is a good state, '△' is a normal state, and 'X' is a bad state.
상기의 표2에 나타난 바와 같이, 본 발명에 의한 합금의 본딩 와이어는 상온에서의 파단 강도(Brittle Failure)가 최소 16.7 gf이고, 최대 18.5 gf 로써 종래 기술의 최대 15.7 gf 및 최소 14.3 gf 과 대비하여 매우 좋은 결과 값임을 확인할 수 있고, 고온에서의 파단 강도 역시, 최소 15.3 gf이고, 최대 18.2 gf 로써 종래기술의 최대 13.8 gf 및 최소 12 gf 보다 매우 우수한 파단 강도를 나타내고 있음과 동시에 본 발명의 비저항 값도 2.28 내지 2.31 μΩ㎝ 으로써 매우 안정적이고 변동이 없으나, 종래 기술에서는 상대적으로 비저항이 2.92 μΩ㎝ 로써, 급격히 증가하여 신호의 전송에 부적합함을 알 수 있다.As shown in Table 2, the bonding wire of the alloy according to the present invention has a breaking strength at room temperature of at least 16.7 gf and a maximum of 18.5 gf, compared to the maximum of 15.7 gf and at least 14.3 gf of the prior art. It can be seen that it is a very good result, and the breaking strength at high temperature is also at least 15.3 gf, at a maximum of 18.2 gf, which shows much higher breaking strength than that of the prior art of 13.8 gf and 12 gf. 2.28 to 2.31 μΩcm is very stable and unchanged. However, in the related art, the relative resistance is 2.92 μΩcm, which increases rapidly and is not suitable for signal transmission.
또한, 상기와 같이 제조된 본 발명의 기술에 의한 본딩 와이어(30)를 이용하여 3.8 mm, 4.8 mm 및 6.1 mm의 길이로 길게 배선하여 루프(Loop)를 형성한 경우, 처짐(Sagging)이 발생하지 않고 양호하게 그 형상을 유지하고 있었으며, 형성된 루프(Loop)의 쏠림(Sweeping)은 최대 2.5 이고 최소 1.3 로써 인접 루프와의 전기적으로 접촉하는 쇼트(Short) 발생률이 저하되었고, 볼(32)의 형상도 양호하였음을 확인할 수 있다.In addition, when a loop is formed by long wires having a length of 3.8 mm, 4.8 mm, and 6.1 mm using the bonding wire 30 according to the present invention manufactured as described above, sagging occurs. The shape of the loop was reduced to a maximum of 2.5 and a minimum of 1.3, and the occurrence rate of short in electrical contact with an adjacent loop was reduced, and the ball 32 It can be confirmed that the shape was also good.
그러나, 종래 기술에 의한 본딩 와이어(30)를 6 mm 이상의 길이로 루프를 형성하였을 경우, 처짐(Sagging) 상태가 불량하여 사용할 수 없고, 쏠림(Sweeping)은 3.2 내지 4.1 로써 높은 집적도의 패키지에서는 루프 사이에 쇼트(Short)가 발생할 확률이 매우 높게 나타난다.However, when the bonding wire 30 according to the prior art has a loop formed to a length of 6 mm or more, the sagging state is poor and cannot be used, and the sweeping is 3.2 to 4.1. There is a very high chance of a short in between.
상기와 같이 본 발명의 기술에 의한 고강도 본딩 와이어용 합금은, 파단 강도가 크고, 볼의 형상이 양호하며, 처짐(Sagging) 및 쏠림(Sweeping) 성능이 향상된 상태에서도 비저항 또는 저항률(Resistivity) 값이 변함없이 우수하므로, 고집적도의 반도체 패키지에서 본딩 와이어(30)의 직경(Diameter)을 작게 하면서도 고속의 전송속도로 신호를 전송할 수 있으며, 긴 루프(Long Loop)에서도 루프의 형상이 변하지 않고 있음을 보여 준다.As described above, the alloy for high strength bonding wire according to the present invention has a high breaking strength, a good shape of a ball, and a specific resistance or resistivity value even in a state where sagging and sweeping performances are improved. As it is excellent invariably, it is possible to transmit a signal at a high transmission speed while reducing the diameter of the bonding wire 30 in a high-density semiconductor package, and the shape of the loop does not change even in a long loop. Show it.
따라서, 상기와 같은 본 발명의 기술은 집적도(Integrated)가 급격히 상승하는 반도체 칩(10)에 사용하기 적합한 것으로써, 본딩 와이어(30)의 굵기를 가늘게 할 수 있고, 루프의 길이를 길게 할 수 있다.Therefore, the technique of the present invention as described above is suitable for use in the semiconductor chip 10 in which the integrated density rises sharply, so that the thickness of the bonding wire 30 can be thinned and the length of the loop can be increased. have.
상기와 같이 본 발명의 기술에 의한 합금으로 제조된 고강도 본딩 와이어는, 긴 루프(Long Loop)에서도 처짐과 쏠림이 없고, 상온 및 고온에서도 파단 강도가 우수한 동시에, 볼의 형상이 양호하고 비저항 값의 변동이 없으므로, 높은 집적도의 집적회로 패키지에서 루프 배선용으로 사용할 수 있는 공업적 및 산업적 이용효과가 있다.As described above, the high-strength bonding wire made of an alloy according to the present invention has no sag and slack even in a long loop, has excellent breaking strength even at room temperature and high temperature, and has a good shape of a ball and a resistivity value. Since there is no variation, there are industrial and industrial applications that can be used for loop wiring in high integrated circuit packages.
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