KR20010073273A - a schottky barrier diode and a method manufacturing the same - Google Patents
a schottky barrier diode and a method manufacturing the same Download PDFInfo
- Publication number
- KR20010073273A KR20010073273A KR1020000001523A KR20000001523A KR20010073273A KR 20010073273 A KR20010073273 A KR 20010073273A KR 1020000001523 A KR1020000001523 A KR 1020000001523A KR 20000001523 A KR20000001523 A KR 20000001523A KR 20010073273 A KR20010073273 A KR 20010073273A
- Authority
- KR
- South Korea
- Prior art keywords
- trench
- epitaxial layer
- guard ring
- opening
- schottky barrier
- Prior art date
Links
- 230000004888 barrier function Effects 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000004140 cleaning Methods 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 229910021642 ultra pure water Inorganic materials 0.000 claims description 6
- 239000012498 ultrapure water Substances 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims 2
- 230000007423 decrease Effects 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000002542 deteriorative effect Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical compound C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02052—Wet cleaning only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
Abstract
Description
본 발명은 쇼트키 배리어 다이오드(schottky barrier diode) 및 그 제조 방법에 관한 것이다.The present invention relates to a schottky barrier diode and a method of manufacturing the same.
일반적으로 쇼트키 배리어 다이오드는 낮은 저항을 가지는 금속 도전체와 n형 또는 p형의 반도체의 접합으로 이루어진 다이오드이다.Generally, a Schottky barrier diode is a diode composed of a junction of a metal conductor having a low resistance and an n-type or p-type semiconductor.
이러한 쇼트키 배리어 다이오드는 p형 및 n형의 반도체 접합으로 이루어진 쌍극성 다이오드(bipolar diode)와 비교해 볼 때 공핍층을 가지지 않아 순방향 전압 강하(forward voltage drop)가 작으며, 다수 캐리어만을 가지고 있으므로 단극성 소자(unipolar device)라고 한다. 또한, 공핍층 및 축적된 전하가 없으므로 도통(on), 차단(off) 및 전환(switching)이 쌍극성 다이오드보다 빨라, 빠른 역회복(reverse recovery) 특성이 요구되는 전환 방식(switching mode)의 전력 공급 장치에서 출력 정류기(output rectifier)와 모터(motor)와 같은 고주파 전력 전환 장치에 광범위하게 사용된다.These Schottky barrier diodes do not have a depletion layer as compared to bipolar diodes composed of p-type and n-type semiconductor junctions, and thus have a small forward voltage drop and only a large number of carriers. It is called a unipolar device. In addition, there is no depletion layer and no accumulated charge, so that on, off, and switching are faster than bipolar diodes, requiring power in a switching mode that requires fast reverse recovery. Widely used in high frequency power conversion devices such as output rectifiers and motors in the supply device.
이러한 쇼트키 배리어 다이오드에서의 순방향 바이어스시의 전압 강하(forward-biased voltage drop, Vf)와 역방향 바이어스시의 누설 전류(reverse-biased leakage current, Ir)는 전위 장벽 높이(schottky barrier height, Φb), 즉 n형 또는 p형 반도체의 일함수(Φs)와 금속 도전체의 일함수(Φm)의 차이에 의해 결정된다. 또한, 순방향 바이어스시의 전압 강하(Vf)는 n형 또는 p형 불순물의 농도 및 반도체층의 두께에 의해서도 결정되는데, 반도체층을 높은 농도의 불순물로 도핑하는 경우에 순방향 바이어스시의 전압 강하(Vf)는 감소시킬 수 있으나, 역방향 바이어스시 항복 전압 또한 감소하는 문제점이 있다.The forward-biased voltage drop (Vf) and the reverse-biased leakage current (Ir) at the reverse bias in the Schottky barrier diode are the schottky barrier height (Φb), That is, it is determined by the difference between the work function Φs of the n-type or p-type semiconductor and the work function Φm of the metal conductor. The voltage drop Vf during forward bias is also determined by the concentration of n-type or p-type impurities and the thickness of the semiconductor layer, and the voltage drop Vf during forward bias when the semiconductor layer is doped with a high concentration of impurities. ) Can be reduced, but the breakdown voltage also decreases during reverse biasing.
이러한 문제점을 개선하기 위해 쇼트키 다이오드에 p형 및 n형 접합 격자 구조가 추가되어 있는 구조로서 JBS 정류기(junction controled barrier schottky rectifier)가 미국 특허 출원 번호 4,641,174에서 제안되었으며, 동일한 목적으로 TMBS 정류기(trench MOS barrier schottky rectifier)가 미국 특허 출원 번호 5,365,102에서 제안되었다.In order to solve this problem, a junction controled barrier schottky rectifier (JBS rectifier) has been proposed in US Patent Application No. 4,641,174 as a structure in which p-type and n-type junction lattice structures are added to a Schottky diode, and a TMBS rectifier is used for the same purpose. MOS barrier schottky rectifier) is proposed in US Patent Application No. 5,365,102.
그러나 JBS 정류기의 경우에는 p형 및 n형 접합 격자 구조를 가지고 있어 쇼트키 다이오드의 특성을 향상시키기 위해서는 소자의 면적이 커지는 문제점이 있으며, TMBS 역시 소자의 면적이 커지는 동시에 MOS 구조를 가지고 있어 제조 공정이 복잡하다는 문제점이 있다.However, JBS rectifiers have p-type and n-type junction lattice structures, so the area of the device is increased to improve the characteristics of the Schottky diode. There is a problem with this complexity.
본 발명의 과제는 순방향 바이어스시의 전압 강하를 줄이고 역방향 바이어스시의 항복 전압 특성을 악화시키지 않으면서도 면적이 작은 쇼트키 배리어 다이오드를 제공하는 것이다.An object of the present invention is to provide a Schottky barrier diode having a small area without reducing the voltage drop during forward bias and without deteriorating the breakdown voltage characteristic during reverse bias.
또한 본 발명의 다른 과제는 쇼트키 배리어 다이오드의 제조 방법을 단순화하는 것이다.Another object of the present invention is to simplify the method of manufacturing a Schottky barrier diode.
도 1은 본 발명의 실시예에 따른 쇼트키 배리어 다이오드(schottky barrier diode)의 구조를 도시한 단면도이고,1 is a cross-sectional view showing the structure of a schottky barrier diode according to an embodiment of the present invention,
도 2a 내지 도 2d는 본 발명의 실시예에 따른 쇼트키 배리어 다이오드의 제조 방법을 그 공정 순서에 따라 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a schottky barrier diode according to an embodiment of the present invention in the order of their processes.
위와 같은 과제를 해결하기 위하여 본 발명에서는 에피택셜층에 트렌치를 형성한다.In order to solve the above problems, the present invention forms a trench in the epitaxial layer.
구체적으로, 본 발명에 따른 쇼트키 배리어 다이오드에는, 제1 도전형의 반도체 기판 상부에 트렌치를 가지는 제1 도전형의 에피택셜층이 성장되어 있다. 트렌치 둘레에는 제2 도전형의 가드 링이 형성되어 있으며, 기판 상부에는 트렌치 및 가드 링의 일부를 드러내는 개구부를 가지는 절연막이 형성되어 있다. 또한, 기판 상부에는 개구부를 통하여 가드 링과 에피택셜층에 연결되어 있는 제1 전극이 형성되어 있으며, 기판의 하부에는 제2 전극이 형성되어 있다.Specifically, in the Schottky barrier diode according to the present invention, an epitaxial layer of a first conductivity type having a trench over the first conductivity type semiconductor substrate is grown. A guard ring of the second conductivity type is formed around the trench, and an insulating film having an opening that exposes a portion of the trench and the guard ring is formed on the substrate. In addition, a first electrode connected to the guard ring and the epitaxial layer is formed at an upper portion of the substrate, and a second electrode is formed at the lower portion of the substrate.
여기서, 트렌치의 깊이는 가드 링의 접합 깊이보다 얕고, 가드 링은 트렌치와 거리를 두고 있고, 개구부 경계는 가드 링 위에 위치하는 것이 바람직하다.Here, the depth of the trench is shallower than the junction depth of the guard ring, the guard ring is spaced from the trench, and the opening boundary is preferably located above the guard ring.
제1 전극과 에피택셜층 사이에는 형성되어 있는 배리어 금속층을 더 포함할수 있다.The semiconductor device may further include a barrier metal layer formed between the first electrode and the epitaxial layer.
이러한 본 발명에 따른 쇼트키 배리어 다이오드의 제조 방법은, 우선 제1 도전형의 반도체 기판 상부에 제1 도전형의 에피택셜층을 형성하고, 에피택셜층 상부에 절연막을 적층하고 패터닝하여 제1 개구부를 형성한다. 이어, 제1 개구부를 통하여 제2 도전형의 불순물을 이온 주입하고 확산하여 가드 링을 형성하고, 절연막을 패터닝하여 제2 개구부를 형성한다. 이어, 에피택셜층에서 제2 개구부를 통하여 노출된 부분의 일부를 식각하여 트렌치를 형성하고 에피택셜층의 상부에 제1 전극을 형성하고 기판의 하부에 제2 전극을 형성한다.According to the method of manufacturing a Schottky barrier diode according to the present invention, first, an epitaxial layer of a first conductivity type is formed on a semiconductor substrate of a first conductivity type, and an insulating film is laminated and patterned on the epitaxial layer to form a first opening. To form. Subsequently, a second ring of impurities is ion-implanted and diffused through the first opening to form a guard ring, and the insulating film is patterned to form a second opening. Subsequently, a portion of the epitaxial layer exposed through the second opening is etched to form a trench, a first electrode is formed on the epitaxial layer, and a second electrode is formed on the bottom of the substrate.
여기서, 트렌치의 깊이는 가드 링의 깊이보다 얕게 형성하는 것이 바람직하다.Here, the depth of the trench is preferably formed to be shallower than the depth of the guard ring.
또한, 트렌치 형성 단계에서의 식각은 건식 식각 방법을 이용하는 것이 바람직하다.In addition, the etching in the trench forming step is preferably using a dry etching method.
트렌치 형성 후 에피택셜층의 손상된 표면을 소프트 식각으로 제거하는 단계를 더 포함할 수 있으며, 트렌치 형성 후 열산화 공정을 실시하여 에피택셜층의 표면에 산화막을 형성한 후 제거하는 단계를 더 포함할 수 있다.The method may further include removing the damaged surface of the epitaxial layer by soft etching after the trench formation, and performing a thermal oxidation process after the trench formation to form an oxide film on the surface of the epitaxial layer and then removing the damaged layer. Can be.
또한, 트렌치 형성 후 에피택셜층의 표면을 세정액을 이용하여 세정하는 단계를 더 포함할 수 있으며, 세정액은 NH4OH, H2O2및 초순수를 포함할 수 있으며, 1%의 HF와 초순수를 포함할 수도 있다.The method may further include cleaning the surface of the epitaxial layer using a cleaning solution after the trench is formed, and the cleaning solution may include NH 4 OH, H 2 O 2, and ultrapure water, and may contain 1% HF and ultrapure water. It may also include.
여기서, 절연막은 열산화 방법으로 형성하는 것이 바람직하며, 제2 개구부는가드 링의 일부를 드러내도록 형성하는 것이 바람직하다.Here, the insulating film is preferably formed by a thermal oxidation method, and the second opening is preferably formed to expose a part of the guard ring.
트렌치와 상기 제1 전극 사이에 배리어 금속층을 형성하는 단계를 더 포함할 수 있다.The method may further include forming a barrier metal layer between the trench and the first electrode.
그러면, 본 발명의 실시예에 따른 쇼트키 배리어 다이오드 및 그 제조 방법에 대하여 첨부한 도면을 참고로 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세하게 설명한다.Next, a Schottky barrier diode and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.
쇼트키 배리어 다이오드에서 순방향 바이어스시 전압 강하는 규소 기판의 저항 또는 에피택셜층의 저항 또는 금속과 규소의 접촉 저항 등으로 인하여 발생한다. 특히, 에피택셜층의 저항은 순방향 바이어스시의 전압 강하를 결정하는 데 중요한 요소이다. 이때, 순방향 바이어스시의 전압 강하를 낮추기 위해서는 에피택셜층의 저항을 작게 하는 것이 바람직한데, 이를 위해서는 에피택셜층의 두께를 얇게 하고 농도를 높이는 것이 유리하나, 이렇게 하면 항복 전압이 낮아지게 된다. 따라서, 항복 전압 특성을 악화시키지 않으면서 순방향 바이어스의 전압 강하는 줄일 수 있도록 에피택셜층을 설계해야 한다.In the Schottky barrier diode, the voltage drop during forward bias occurs due to the resistance of the silicon substrate or the resistance of the epitaxial layer or the contact resistance of metal and silicon. In particular, the resistance of the epitaxial layer is an important factor in determining the voltage drop during forward bias. In this case, it is preferable to reduce the resistance of the epitaxial layer in order to lower the voltage drop during the forward bias. For this purpose, it is advantageous to reduce the thickness of the epitaxial layer and to increase the concentration, but the breakdown voltage is lowered. Therefore, the epitaxial layer should be designed to reduce the voltage drop of the forward bias without degrading the breakdown voltage characteristic.
도 1은 본 발명의 실시예에 따른 쇼트키 배리어 다이오드의 구조를 도시한 단면도이다.1 is a cross-sectional view showing the structure of a Schottky barrier diode according to an embodiment of the present invention.
도 1에서 보는 바와 같이, 고농도 n형 불순물이 함유되어 있는 기판(10)의 위에 n형의 에피택셜층(20)이 형성되어 있으며, 에피택셜층(20)에는 트렌치(21) 및 이를 둘러싸고 있는 고농도 p형의 가드 링(30)이 형성되어 있다. 에피택셜층(20) 상부에는 개구부를 가지는 절연막(40)이 형성되어 있으며, 개구부는 가드 링(30)일부와 가드 링(30)으로 둘러싸인 영역을 드러낸다. 이때, 개구부의 경계는 가드 링(30)의 상부에 위치하여 트렌치(21)의 경계와 일정 거리(d)를 두고 형성한다. 기판(10) 상부에는 절연막(40)의 개구부를 통하여 드러난 에피택셜층(20) 및 가드 링(30)과 접촉하고 있는 배리어 금속층(50)과 알루미늄과 같이 저저항을 가지는 금속으로 이루어진 애노드 전극(60)이 차례로 형성되어 있다. 여기서, 가드 링(30)은 에피택셜층(20)의 가장자리에서 전기장이 집중되는 것을 완화시키는 기능을 한다.As shown in FIG. 1, an n-type epitaxial layer 20 is formed on a substrate 10 containing a high concentration of n-type impurities, and the trench 21 and surrounding the epitaxial layer 20 are formed. A high concentration p-type guard ring 30 is formed. An insulating film 40 having an opening is formed on the epitaxial layer 20, and the opening exposes a portion of the guard ring 30 and an area surrounded by the guard ring 30. In this case, the boundary of the opening is formed at the upper portion of the guard ring 30 to be formed at a distance d from the boundary of the trench 21. An anode electrode made of a metal having low resistance, such as aluminum, and the barrier metal layer 50 contacting the epitaxial layer 20 and the guard ring 30 exposed through the opening of the insulating film 40. 60 are sequentially formed. Here, the guard ring 30 serves to mitigate the concentration of the electric field at the edge of the epitaxial layer 20.
한편, 기판(10)의 하부에는 캐소드 전극(70)이 형성되어 있다.Meanwhile, a cathode electrode 70 is formed below the substrate 10.
여기에서 트렌치(21)의 깊이는 역방향 바이어스시, 즉 전원의 양극(+) 및 음극(-) 단자가 캐소드 및 애노드 전극(70)에 연결되었을 경우의 항복 전압 특성에 영향을 주지 않도록 결정해야 한다. 이를 위해서는 도 1에서 보는 바와 같이, 역방향 바이어스시 트렌치(21) 하부에 형성되는 공핍층의 경계(90)가 가드 링(30) 하부에 형성되는 공핍층의 경계보다 기판(10)으로부터 멀어야 한다. 따라서, 트렌치(21)의 깊이는 가드 링(30)의 접합 깊이보다 얕은 것이 바람직하다.Here, the depth of the trench 21 should be determined so as not to affect the breakdown voltage characteristics during reverse biasing, i.e., when the positive (+) and negative (-) terminals of the power supply are connected to the cathode and anode electrodes 70. . To this end, as shown in FIG. 1, the boundary 90 of the depletion layer formed under the trench 21 at the reverse bias should be farther from the substrate 10 than the boundary of the depletion layer formed under the guard ring 30. . Therefore, the depth of the trench 21 is preferably shallower than the junction depth of the guard ring 30.
이러한 본 발명의 구조에서는 에피택셜층(20)에 트렌치(21)가 형성되어 있어 기판(10) 표면으로부터 에피택셜층(20) 표면까지의 거리가 감소하므로 순방향 바이어스시 에피택셜층(20)의 내부 저항(80)이 감소한다.In the structure of the present invention, the trench 21 is formed in the epitaxial layer 20, so that the distance from the surface of the substrate 10 to the surface of the epitaxial layer 20 is reduced, so that the epitaxial layer 20 is formed during forward biasing. The internal resistance 80 is reduced.
그러므로, 본 발명에서는 역방향 바이어스시의 항복 전압 특성을 악화시키지 않는 동시에 순방향 바이어스시의 전압 강하를 최소화할 수 있다.Therefore, in the present invention, it is possible to minimize the voltage drop during the forward bias while not deteriorating the breakdown voltage characteristic during the reverse bias.
이러한 본 발명의 실시예에 따른 쇼트키 배리어 다이오드의 제조 방법에 대하여 설명하면 다음과 같다.Hereinafter, a method of manufacturing a schottky barrier diode according to an exemplary embodiment of the present invention will be described.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 쇼트키 배리어 다이오드의 제조 방법을 그 공정 순서에 따라 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a schottky barrier diode according to an embodiment of the present invention in the order of their processes.
도 2a에서 보는 바와 같이, n형의 불순물이 고농도로 도핑되어 있는 기판(10)의 상부에 에피택셜층(20)을 성장시켜 형성한다. 이어, 열산화를 통하여 에피택셜층(20)의 상부에 산화막(40)을 형성하고, 선택적으로 이온을 주입하기 위해 산화막(40)을 패터닝하여 절연막(40)에 제1 개구부(41)를 형성한다.As shown in FIG. 2A, the epitaxial layer 20 is grown on the substrate 10 to which n-type impurities are heavily doped. Subsequently, an oxide film 40 is formed on the epitaxial layer 20 through thermal oxidation, and the oxide film 40 is patterned to selectively implant ions to form a first opening 41 in the insulating film 40. do.
다음, 도 2b에서 보는 바와 같이, 산화막(40)을 주입 마스크로 하여 붕소(boron) 등과 같은 p형의 불순물을 고농도로 이온주입하고 고온의 확산 공정을 통하여 가드 링(30)을 형성한다. 이때, 제1 개구부(41)에는 제1 개구부(41)를 통하여 노출되어 있는 에피택셜층(20) 상부가 고온의 확산 공정으로 열산화되어 얇은 산화막이 채워진다.Next, as shown in FIG. 2B, a p-type impurity such as boron or the like is ion-implanted at high concentration using the oxide film 40 as an injection mask to form the guard ring 30 through a high temperature diffusion process. At this time, the upper portion of the epitaxial layer 20 exposed through the first opening 41 is thermally oxidized by a high temperature diffusion process to fill the first opening 41 with a thin oxide film.
이어, 도 2c에서 보는 바와 같이, 산화막(40)을 패터닝하여 제2 개구부(42)를 형성하여, 가드 링(30)의 일부 및 가드 링(30)으로 둘러싸여 있는 에피택셜층(20)을 드러낸다. 이때, 산화막(40)의 경계는 가드 링(30)의 상부에 위치하도록 한다. 여기서 제2 개구부(42)는 산화막(40)에서 제1 개구부(41)로 둘러싸인 부분과 가드 링(30) 확산 공정에서 형성된 부분의 일부를 제거하여 형성하므로, 제2 개구부(42)의 경계가 계단 모양이 된다.Subsequently, as shown in FIG. 2C, the oxide layer 40 is patterned to form the second opening 42, thereby exposing a part of the guard ring 30 and the epitaxial layer 20 surrounded by the guard ring 30. . In this case, the boundary of the oxide film 40 is positioned above the guard ring 30. The second opening 42 is formed by removing a portion of the oxide film 40 surrounded by the first opening 41 and a part of the guard ring 30 diffusion process, so that the boundary between the second opening 42 is It becomes a staircase shape.
이어, 도 2d에서 보는 바와 같이, 드러난 에피택셜층(20)의 중앙부에 습식 또는 건식 식각 방법으로 트렌치(21)를 형성한다. 건식 식각을 사용하는 경우에는트렌치(21)의 표면이 손상되기 쉬우므로, 소프트(soft) 식각 공정을 추가로 실시하여 손상된 표면을 제거하는 것이 좋으며, 열산화 공정을 통하여 제2 개구부(42)를 통하여 드러난 반도체 기판(10)의 상부에 열산화막을 형성하고 제거하는 공정을 추가로 실시한다. 이렇게 하면 트렌치(21)의 모서리 부분이 완만해져서 이 부분에서 전기장이 집중되는 것을 방지할 수 있다.Next, as shown in FIG. 2D, the trench 21 is formed in the center of the exposed epitaxial layer 20 by a wet or dry etching method. In the case of using dry etching, the surface of the trench 21 may be easily damaged. Therefore, a soft etching process may be additionally removed to remove the damaged surface, and the second opening 42 may be formed through a thermal oxidation process. A process of forming and removing a thermal oxide film on top of the semiconductor substrate 10 exposed through the above is further performed. In this way, the corner portion of the trench 21 is smoothed to prevent the electric field from being concentrated in this portion.
이후, 안정적인 쇼트키 계면을 형성하기 위한 방법으로 노출된 에피택셜층(20) 및 가드 링(30)의 규소 표면을 NH4OH, H2O2및 초순수를 포함하는 세정액 및/또는 초순수와 1%의 HF를 포함하는 세정액을 이용하여 세정한다.Thereafter, the silicon surface of the epitaxial layer 20 and the guard ring 30 exposed as a method for forming a stable Schottky interface may be washed with a cleaning liquid and / or ultrapure water containing NH 4 OH, H 2 O 2, and ultrapure water. It washes using the washing | cleaning liquid containing% HF.
이어, 도 1에서 보는 바와 같이, 티타늄 또는 몰리브덴을 포함하는 고융점 금속을 이용하여 배리어 금속층(60)과 알루미늄 등의 저저항을 가지는 금속 물질을 이용하여 애노드 전극(60)과 캐소드 전극(70)을 형성한다.Subsequently, as shown in FIG. 1, the anode electrode 60 and the cathode electrode 70 using a metal material having low resistance, such as the barrier metal layer 60 and aluminum, using a high melting point metal including titanium or molybdenum. To form.
이러한 본 발명의 실시예에 따른 제조 방법에서는 MOS 제조 공정을 추가하지 않고 트렌치(21)만을 형성함으로써 제조 공정을 단순화할 수 있다.In the manufacturing method according to the embodiment of the present invention, it is possible to simplify the manufacturing process by forming the trench 21 without adding the MOS manufacturing process.
이와 같이 본 발명에 따르면, 역방향 항복 전압 특성을 악화시키지 않고 순방향 바이어스시의 전압 강하는 낮추면서도 면적을 늘리지 않으며, 제조 공정이 단순화하다.As described above, according to the present invention, the voltage drop at the forward bias is not deteriorated without deteriorating the reverse breakdown voltage characteristic and the area is not increased while the manufacturing process is simplified.
Claims (16)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000001523A KR20010073273A (en) | 2000-01-13 | 2000-01-13 | a schottky barrier diode and a method manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000001523A KR20010073273A (en) | 2000-01-13 | 2000-01-13 | a schottky barrier diode and a method manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010073273A true KR20010073273A (en) | 2001-08-01 |
Family
ID=19638310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000001523A KR20010073273A (en) | 2000-01-13 | 2000-01-13 | a schottky barrier diode and a method manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010073273A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100482845B1 (en) * | 2002-08-22 | 2005-04-14 | 한국전기연구원 | Silicon carbide back-to-back Schottky barrier diode structure |
| KR100888290B1 (en) * | 2007-08-10 | 2009-03-11 | 주식회사 케이이씨 | Schottky barrier diode and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63311762A (en) * | 1987-06-15 | 1988-12-20 | Matsushita Electronics Corp | Schottky barrier semiconductor device |
| JPH0465876A (en) * | 1990-07-06 | 1992-03-02 | Fuji Electric Co Ltd | Schottky barrier semiconductor device |
| JPH06224410A (en) * | 1993-01-22 | 1994-08-12 | Fuji Electric Co Ltd | Manufacture of schottky barrier diode |
| JPH06252381A (en) * | 1993-03-01 | 1994-09-09 | Yokogawa Electric Corp | Manufacture of schottky barrier diode |
| JPH09307120A (en) * | 1996-05-14 | 1997-11-28 | Rohm Co Ltd | Schottky barrier semiconductor device and its manufacture |
-
2000
- 2000-01-13 KR KR1020000001523A patent/KR20010073273A/en not_active Application Discontinuation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63311762A (en) * | 1987-06-15 | 1988-12-20 | Matsushita Electronics Corp | Schottky barrier semiconductor device |
| JPH0465876A (en) * | 1990-07-06 | 1992-03-02 | Fuji Electric Co Ltd | Schottky barrier semiconductor device |
| JPH06224410A (en) * | 1993-01-22 | 1994-08-12 | Fuji Electric Co Ltd | Manufacture of schottky barrier diode |
| JPH06252381A (en) * | 1993-03-01 | 1994-09-09 | Yokogawa Electric Corp | Manufacture of schottky barrier diode |
| JPH09307120A (en) * | 1996-05-14 | 1997-11-28 | Rohm Co Ltd | Schottky barrier semiconductor device and its manufacture |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100482845B1 (en) * | 2002-08-22 | 2005-04-14 | 한국전기연구원 | Silicon carbide back-to-back Schottky barrier diode structure |
| KR100888290B1 (en) * | 2007-08-10 | 2009-03-11 | 주식회사 케이이씨 | Schottky barrier diode and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9905666B2 (en) | Trench schottky rectifier device and method for manufacturing the same | |
| US6426541B2 (en) | Schottky diode having increased forward current with improved reverse bias characteristics and method of fabrication | |
| US7078780B2 (en) | Schottky barrier diode and method of making the same | |
| US6404033B1 (en) | Schottky diode having increased active surface area with improved reverse bias characteristics and method of fabrication | |
| JP2005532698A (en) | Trench type Schottky barrier diode | |
| US20130093066A1 (en) | Semiconductor device | |
| US8691635B2 (en) | Fabrication method of semiconductor device | |
| US7064408B2 (en) | Schottky barrier diode and method of making the same | |
| JPH1197716A (en) | Mos control diode and manufacture of the same | |
| CN112201697A (en) | Schottky diode and method for preparing Schottky diode | |
| US9406788B2 (en) | Structure of a trench MOS rectifier and method of forming the same | |
| US10388801B1 (en) | Trench semiconductor device having shaped gate dielectric and gate electrode structures and method | |
| KR20010073273A (en) | a schottky barrier diode and a method manufacturing the same | |
| KR101184378B1 (en) | Schottky diode and method for manufacturing the same | |
| CN113451296B (en) | Power device with lateral insulated gate bipolar transistor and method of manufacturing the same | |
| KR19990024988A (en) | Manufacturing method of power semiconductor device using semi-insulating polysilicon film | |
| KR101667669B1 (en) | Schottky barrier diode and method for manufacturing the diode | |
| KR100598348B1 (en) | Method for fabricating schottky diode using silicon-based cmos process | |
| KR20040019477A (en) | Schottky diode and method for fabricating thereof | |
| KR100289742B1 (en) | Power semiconductor device using Semi-Insulating PO1ycrysta IIine Silicon(SIPOS) film | |
| US20070293028A1 (en) | Method of forming low forward voltage Shottky barrier diode with LOCOS structure therein | |
| KR101072992B1 (en) | Schottky diode and method for forming the same | |
| KR101502306B1 (en) | Semiconductor rectification device and method for fabricating the same | |
| CN117673117A (en) | Terminal structure, manufacturing method thereof and power device | |
| KR101128703B1 (en) | Method for forming schottky diode |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |