KR20010065304A - Method of forming a contact hole in a semiconductor device - Google Patents
Method of forming a contact hole in a semiconductor device Download PDFInfo
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- KR20010065304A KR20010065304A KR1019990065177A KR19990065177A KR20010065304A KR 20010065304 A KR20010065304 A KR 20010065304A KR 1019990065177 A KR1019990065177 A KR 1019990065177A KR 19990065177 A KR19990065177 A KR 19990065177A KR 20010065304 A KR20010065304 A KR 20010065304A
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- 238000000034 method Methods 0.000 title claims abstract description 81
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000010410 layer Substances 0.000 claims abstract description 54
- 238000005530 etching Methods 0.000 claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 9
- 229920005591 polysilicon Polymers 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000001312 dry etching Methods 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 230000005284 excitation Effects 0.000 claims description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 239000000126 substance Substances 0.000 description 6
- 238000007517 polishing process Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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Abstract
Description
본 발명은 반도체 소자의 콘택 홀 형성방법에 관한 것으로, 콘택 접촉면적을 넓혀 콘택 저항을 낮추며 공정을 단순화 시켜 제조원가를 절감하도록 하여 소자 특성을 향상시킬 수 있는 반도체 소자의 콘택 홀 형성방법에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device, and to a method for forming a contact hole in a semiconductor device capable of improving device characteristics by increasing contact contact area to lower contact resistance and simplifying a process to reduce manufacturing cost.
일반적으로, 반도체 소자의 고집적화에 따라 회로 선폭 및 간격이 축소 되고 있다. 일반적인 회로 패턴은 반도체 소자 공정에서 기존에 형성되어 있는 패턴에 새로운 패턴을 형성할 경우 발생할 수 있는 패턴간의 어긋남을 고려하여 설계 및 제작한다. 이러한 회로 패턴 설계의 마진은 소자의 고집적화로 점차 축소되므로 콘택 홀 형성시 어긋남을 방지하기 위해 자기정합 콘택 홀 형성방법을 적용하고 있다.In general, circuit line widths and spacings are reduced due to high integration of semiconductor devices. The general circuit pattern is designed and manufactured in consideration of the deviation between the patterns that may occur when a new pattern is formed on the existing pattern in the semiconductor device process. Since the margin of the circuit pattern design is gradually reduced due to the high integration of the device, a self-aligning contact hole forming method is applied to prevent misalignment when forming the contact hole.
종래 반도체 소자의 콘택 홀 형성방법을 첨부도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, a conventional method for forming a contact hole in a semiconductor device is as follows.
도 1a 내지 도 1e는 종래 반도체 소자의 콘택 홀 형성방법을 설명하기 위한 소자의 단면도이다.1A to 1E are cross-sectional views of devices for describing a method for forming contact holes in a conventional semiconductor device.
도 1a를 참조하면, 필드산화막(2)이 형성된 반도체 기판(1) 상에 게이트전극 (3), 스페이서(4) 및 실리사이드막(5)를 형성한 후 전체 상부면에 식각방지막(6)을 형성하고, 전체 상부면에 층간절연막(7)을 형성한다.Referring to FIG. 1A, after forming the gate electrode 3, the spacer 4, and the silicide layer 5 on the semiconductor substrate 1 on which the field oxide layer 2 is formed, the etch stop layer 6 is formed on the entire upper surface. The interlayer insulating film 7 is formed on the entire upper surface.
상기에서, 층간절연막(7)은 BPSG막 또는 PSG막으로 이루어지고,식각방지막(6)은 플라즈마 보조 화학 기상법 또는 저압 화학지상법에 의한 질화막으로 이루어진다.In the above, the interlayer insulating film 7 is made of a BPSG film or a PSG film, and the etch stop film 6 is made of a nitride film by a plasma assisted chemical vapor deposition method or a low pressure chemical ground method.
도 1b를 참조하면, 평탄화 공정인 화학적 기계적 연마공정을 실시하여 층간절연막(7)을 평탄화한다.Referring to FIG. 1B, the interlayer insulating film 7 is planarized by performing a chemical mechanical polishing process, which is a planarization process.
상기에서, 화학적 기계적 연마공정은 고비용공정으로 소자 제조원가의 많은 부분을 차지한다. 따라서, 화학적 기계적 연마공정을 생략하기 위해 시도가 이루어지고 있으나 게이트 전극(3)와 액티브 영역의 단차로 인해 층간절연막(7)인 BPSG막 또는 PSG막의 플로우(flow) 만으로는 충분하게 평탄화되지 않아 필수적으로 화학적 기계적 연마공정을 실시하여야 한다.In the above, the chemical mechanical polishing process is a high cost process and takes up a large part of the device manufacturing cost. Therefore, attempts have been made to omit the chemical mechanical polishing process, but the flow of the BPSG film or PSG film, which is the interlayer insulating film 7, is not sufficiently flattened due to the step difference between the gate electrode 3 and the active region. A chemical mechanical polishing process should be performed.
도 1c를 참조하면, 플라즈마 건식식각 방법으로 식각방지막(6)이 노출되도록 층간절연막(7) 일부를 제거하여 콘택 홀(8)을 형성한다.Referring to FIG. 1C, a contact hole 8 is formed by removing a portion of the interlayer insulating film 7 so that the etch stop layer 6 is exposed by a plasma dry etching method.
도 1d를 참조하면, 자기정합방법으로 콘택 홀(8)에 노출된 식각방지막(6)을 제거하여 접합영역을 노출시킨다.Referring to FIG. 1D, the etch stop layer 6 exposed to the contact hole 8 is removed by a self-aligning method to expose the junction region.
상기에서, 식각방지막(6)은 일반적으로 질화막을 이용하는데, 고유전율의 질화막 형성은 소자의 전기적 특성면에서 좋지 않는 영향을 주므로 가능한 두께가 한정되어 형성된다. 또한, 식각방지막(6)이 충분한 두께로 형성되지 못하여 식각에 의해 뚫릴 경우 스페이서(4) 및 필드산화막(2)이 손상을 받게 된다. 이와같이, 한정된 식각방지막(6)으로 식각을 정지시키기 위해서는 탄소를 많이 함유하는 C-F 계열의 폴리머를 보다 풍부하게 생성시켜 산화막과 식각방지막(6)의 식각선택비를 높여야 한다. 그러나, 폴리머가 증가하게 되면 콘택 홀에서 식각이 정지되는 현상이발생하며, 이러한 현상은 콘택 홀이 폴리실리콘 라인과의 단차에 의해 좁혀진 경우에 많이 발생한다. 또한, 콘택 홀 형성시 웨이퍼 전체에 걸쳐 균일하게 식각방지막의 손실이 없는 동시에 식각이 정지되지 않으면 콘택 홀 식각공정은 그 공정마진이 매우 작기 때문에 공정의 재현성과 안전성에 문제를 발생시킨다.In the above, the anti-etching film 6 generally uses a nitride film. Since the formation of a high dielectric constant nitride film has an adverse effect on the electrical characteristics of the device, the thickness is limited. In addition, when the etch stop layer 6 is not formed to a sufficient thickness and is pierced by etching, the spacer 4 and the field oxide layer 2 are damaged. As such, in order to stop the etching with the limited etch stop layer 6, a carbon-rich C-F-based polymer should be more abundant to increase the etch selectivity of the oxide film and the etch stop layer 6. However, when the polymer increases, the etching stops in the contact hole, and this phenomenon occurs frequently when the contact hole is narrowed by a step with the polysilicon line. In addition, when the contact hole is not uniformly lost throughout the wafer and the etching is not stopped, the contact hole etching process causes a problem in the reproducibility and safety of the process because the process margin is very small.
식각방지막(6)인 질화막은 C-H-F 계열의 가스에 O2와 Ar/He 을 첨가한 플라즈마 건식 식각에 의해 제거되는데, 이때 식각은 Si 또는 실리사이드에서 정지되어야 한다. 그러나, 식각이 기본적으로 Si와 실리사이드와 반응할 수 있는 조건으로 이루어지기 때문에 콘택 홀이 형성될 부분에 손상을 줄 수 있으며, 손상 정도가 심할 경우 소자 특성에 악영향을 미치게 된다. 비메모리 반도체 소자의 경우 동작 속도의 향상을 위해 콘택 저항이 수 Ω 으로 유지되어야 하는데, 소자의 집적도가 증가함에 따라 콘택 면적은 점차 감소하고 있어 기존의 방법으로 자기 정합 콘택을 형성할 경우 발생되는 콘택 면적의 감소는 소자의 전기적 특성을 감소시킨다.The nitride film, which is the etch stop film 6, is removed by plasma dry etching by adding O 2 and Ar / He to the CHF-based gas, wherein the etching must be stopped in Si or silicide. However, since the etching is basically made of a condition that can react with Si and silicide, it may damage the portion where the contact hole is to be formed, and if the degree of damage is severe, the device characteristics are adversely affected. In the case of non-memory semiconductor devices, the contact resistance should be maintained at several Ω to improve the operation speed. The contact area is gradually decreasing as the integration degree of the device increases, so that the contact generated when the self-aligned contact is formed by the conventional method. Reducing the area reduces the electrical properties of the device.
따라서, 본 발명은 종래 식각방지막을 이용하여 콘택 홀을 형성함에 따라 발생되는 문제점을 해소하고, 콘택 접촉면적을 넓혀 콘택 저항을 낮추며 공정을 단순화 시켜 제조원가를 절감하도록 하여 소자 특성을 향상시킬 수 있는 반도체 소자의 콘택 홀 형성방법을 제공하는데 그 목적이 있다.Accordingly, the present invention solves the problems caused by forming a contact hole by using a conventional etch barrier layer, and widens the contact contact area to lower the contact resistance and simplify the process to reduce the manufacturing cost to improve the device characteristics semiconductor It is an object of the present invention to provide a method for forming a contact hole in a device.
상기한 목적을 달성하기 위하 본 발명에 따른 반도체 소자의 콘택 홀 형성방법은 필드산화막이 형성된 반도체 기판 상에 게이트 전극, 스페이서, 실리사이드막 및 폴리실리콘 라인을 형성한 후 콘택이 형성될 영역을 제외한 나머지 영역에 금속 패드 형성용 산화막 패턴을 형성하는 단계; 상기 산화막 패턴을 포함한 전체상부면에 확산방지막 및 금속층을 순차적으로 형성하는 단계; 상기 금속층을 에치 백 공정으로 상기 산화막 패턴을 노출 시켜 금속 패드를 형성하고, 인시튜로 식각선택비를 조절하여 상기 금속패드 및 산화막 패턴의 식각 단차를 줄이는 평탄화 공정을 실시하는 단계; 전체 상부면에 층간절연막을 증착한 후 마스크 및 식각공정으로 상기 금속 패드가 노출되도록 층간절연막 일부 식각하여 콘택 홀을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, a method of forming a contact hole in a semiconductor device according to the present invention includes forming a gate electrode, a spacer, a silicide layer, and a polysilicon line on a semiconductor substrate on which a field oxide film is formed, except for a region where a contact is to be formed. Forming an oxide film pattern for forming a metal pad in a region; Sequentially forming a diffusion barrier and a metal layer on an entire upper surface including the oxide layer pattern; Exposing the oxide layer pattern to the metal layer by an etch back process to form a metal pad, and performing a planarization process of reducing an etching step between the metal pad and the oxide layer pattern by controlling an etching selectivity in situ; And depositing an interlayer insulating film on the entire upper surface to form a contact hole by partially etching the interlayer insulating film so that the metal pad is exposed by a mask and an etching process.
도 1a 내지 도 1d는 종래 반도체 소자의 콘택 홀 형성방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of a device for explaining a method of forming a contact hole in a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 콘택 홀 형성방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of devices for explaining a method for forming contact holes in a semiconductor device according to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
1 및 10 : 반도체 기판 2 및 11 : 필드산화막1 and 10: semiconductor substrate 2 and 11: field oxide film
3 및 12 : 게이트 전극 4 및 13 : 스페이서3 and 12: gate electrode 4 and 13: spacer
5 및 14 : 실리사이드막 6 : 식각방지막5 and 14: silicide film 6: etching prevention film
7 및 19 : 층간절연막 8 및 20 : 콘택 홀7 and 19: interlayer insulating film 8 and 20: contact hole
15 : 산화막 패턴 17 : 확산방지막15: oxide film pattern 17: diffusion barrier film
18 : 금속층 18a : 금속패드18: metal layer 18a: metal pad
8 및 20 : 콘택 홀8 and 20: contact hall
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명에 따른 반도체 소자의 콘택 홀 형성방법을 설명하기 위한 소자의 단면도이다.2A to 2F are cross-sectional views of devices for describing a method for forming contact holes in a semiconductor device according to the present invention.
도 2a를 참조하면, 필드산화막(11)이 형성된 반도체 기판(10) 상에 게이트 전극(12), 스페이서(13), 실리사이드막(14) 및 폴리실리콘 라인(16)을 형성한 후 콘택이 형성될 영역을 제외한 나머지 영역에 금속 패드 형성용 산화막 패턴(15)을 형성한다.Referring to FIG. 2A, a contact is formed after the gate electrode 12, the spacer 13, the silicide layer 14, and the polysilicon line 16 are formed on the semiconductor substrate 10 on which the field oxide layer 11 is formed. The oxide film pattern 15 for forming a metal pad is formed in the remaining region except for the region to be formed.
상기에서, 금속 패드 형성용 산화막 패턴(15)은 저압 화학기상증착방법 또는 플라즈마 보조 화학기상증착방법을 이용하여 2000 내지 4000Å 두께로 산화막을 증착한 후 마스크 및 식각 공정을 형성한다. 이때, 식각 공정은 C-F 계열의 가스를 이용한 플라즈마 건식 식각법을 이용하여 30 내지 200mT 압력, 300 내지 700W 전력, 0 내지 50 G 자기장, 0 내지 30sccm 량의 CF3가스, 10 내지 50sccm량의 CHF3가스, 25 내지 100sccm 량의 Ar가스 조건하에서 실시한다. 또한, 식각공정은 필드산화막(11) 및 콘택이 형성될 실리사이드막(14)과 폴리실리콘 라인(16)이 손상되지 않도록 식각조건을 최적화하고, 핫 케리어 효과를 억제하기 위한 스페이서(13)를 패턴의 어긋남에 대한 여유면적으로 이용한다. 그리고, 후속 에치백 식각공정이 폴리실리콘 라인(16)과 실리사이드막(14)에 손상을 줄수 있으므로 폴리실리콘 라인(16)도 산화막 패턴(15)으로 보호한다.In the above, the oxide film pattern 15 for forming a metal pad is formed by using a low pressure chemical vapor deposition method or a plasma assisted chemical vapor deposition method to deposit an oxide film at a thickness of 2000 to 4000 kPa, thereby forming a mask and an etching process. At this time, the etching process is 30 to 200mT pressure, 300 to 700W power, 0 to 50 G magnetic field, 0 to 30sccm CF 3 gas, 10 to 50sccm CHF 3 by using plasma dry etching method using CF-based gas Gas, and carried out under Ar gas conditions of 25 to 100sccm amount. In addition, the etching process may optimize the etching conditions so that the field oxide layer 11 and the silicide layer 14 and the polysilicon line 16 on which the contact is to be formed are not damaged and pattern the spacer 13 to suppress the hot carrier effect. Use as a margin area for misalignment. In addition, since the subsequent etch back etching process may damage the polysilicon line 16 and the silicide layer 14, the polysilicon line 16 is also protected by the oxide layer pattern 15.
도 2b를 참조하면, 전체상부면에 확산방지막(17) 및 금속층(18)을 순차적으로 형성한다.Referring to FIG. 2B, the diffusion barrier 17 and the metal layer 18 are sequentially formed on the entire upper surface.
상기에서, 확산방지막(17)은 후속 콘택 홀 형성 후 콘택 홀에 매립되는 텅스텐 플러그와 동일한 조건하에서 스퍼터링 또는 화학기상증착방법으로 Ti/TiN막을 100 내지 300Å/300 내지 500Å 두께로 형성한다. 금속층(18)은 화학기상증착방법으로 텅스텐을 3000 내지 10000Å 두께로 형성한다.In the above, the diffusion barrier 17 forms a Ti / TiN film with a thickness of 100 to 300 mW / 300 to 500 mW by sputtering or chemical vapor deposition under the same conditions as the tungsten plug embedded in the contact hole after the subsequent contact hole formation. The metal layer 18 is formed of tungsten to a thickness of 3000 to 10000 kPa by chemical vapor deposition.
도 2c를 참조하면, 플라즈마 건식식각방법으로 금속층(18)을 에치백(etch back)하여 산화막 패턴(15)을 노출 시켜 금속 패드(18a)를 형성하고, 인시튜(In-situ)로 식각선택비를 조절하여 금속패드(18a)와 산화막패턴(15)의 식각 단차를 줄이는 평탄화 공정을 실시한다. 이때, 금속패드(18a)는 접합영역에 형성되고, 2000내지 3000Å 두께로 형성된다.Referring to FIG. 2C, the metal layer 18 is etched back by the plasma dry etching method to expose the oxide layer pattern 15 to form the metal pad 18a, and the etching selection is performed in-situ. By adjusting the ratio, a planarization process of reducing the etching step between the metal pad 18a and the oxide film pattern 15 is performed. At this time, the metal pad 18a is formed in the junction region and is formed to a thickness of 2000 to 3000 Å.
상기에서, 금속층(18)인 텅스텐을 식각공정은 5 내지 50mT 압력, 200 내지 600W 전력, 50 내지 100G 자기장, 50 내지 200sccm량의 SF6및 20 내지 50sccm 량의 Cl2조건하에서 플라즈마 건식식각방법으로 실시하고, 금속층(18)과 산화막 패턴(15)의 식각단차를 줄이는 평탄화 공정은 5 내지 200mT 압력, 500 내지 900W 전력, 0 내지 50G 자기장, 20 내지 100sccm량의 SF6, 10 내지 50sccm 량의 CF4, 30 내지 100sccm량의 CHF3, 50 내지 150sccm량의 Ar 및 5 내지 20sccm량의 O2조건하에서 실시한다.In the above, the etching process of tungsten, the metal layer 18, is performed by plasma dry etching under 5 to 50 mT pressure, 200 to 600 W power, 50 to 100 G magnetic field, 50 to 200 sccm SF 6 and 20 to 50 sccm Cl 2 conditions. The planarization process for reducing the etching step between the metal layer 18 and the oxide layer pattern 15 is performed by 5 to 200 mT pressure, 500 to 900 W power, 0 to 50 G magnetic field, 20 to 100 sccm SF 6 , and 10 to 50 sccm CF 4 , 30 to 100 sccm of CHF 3 , 50 to 150 sccm of Ar and 5 to 20 sccm of O 2 .
도 2d를 참조하면, 전체 상부면에 층간절연막(19)을 증착한 후 마스크 및 식각공정으로 금속 패드(18a)가 노출되도록 층간절연막(19) 일부 식각하여 콘택 홀(20)을 형성한다.Referring to FIG. 2D, the interlayer insulating layer 19 is deposited on the entire upper surface, and then the contact hole 20 is formed by etching a portion of the interlayer insulating layer 19 to expose the metal pads 18a through a mask and etching process.
상기에서, 층간절연막(19)은 BPSG막 또는 PSG막으로 이루어진다. 콘택 홀(20)은 C-F 계열 가스를 이용한 플라즈마 건식식각공정으로 형성하며, 상세하게 30 내지 100mT 압력, 1500 내지 2000W 전력, 0 내지 60G 자기장, 10 내지 20sccm량의 C4F8, 20 내지 100sccm 량의 CHF3, 200 내지 600sccm량의 Ar 및 5 내지 15sccm량의 O2조건하에서 실시하거나, 3 내지 10mT 압력, 2000 내지 3000W 여기전력, 500 내지 1500W 바이어스 전력, 10 내지 50sccm량의 CF4, 10 내지 100sccm 량의 CHF3, 10 내지 50sccm 량의 C2F6및 0 내지 100sccm량의 Ar 조건하에서 실시한다.In the above, the interlayer insulating film 19 is made of a BPSG film or a PSG film. The contact hole 20 is formed by a plasma dry etching process using a CF-based gas, and in detail, 30 to 100 mT pressure, 1500 to 2000 W power, 0 to 60 G magnetic field, and 10 to 20 sccm amount of C 4 F 8 , 20 to 100 sccm amount CHF 3 , 200 to 600sccm amount of Ar and 5 to 15sccm amount of O 2 conditions, or 3 to 10mT pressure, 2000 to 3000W excitation power, 500 to 1500W bias power, 10 to 50sccm amount of CF 4 , 10 to 100 sccm of CHF 3 , 10 to 50 sccm of C 2 F 6 and 0 to 100 sccm of Ar under conditions.
층간절연막(19)은 이미 평탄화된 상태에서 증착되므로 화학적 기계적연마공정 없이 플로우(Flow)에 의해 충분히 평탄화된다.Since the interlayer insulating film 19 is already deposited in a flattened state, it is sufficiently flattened by flow without chemical mechanical polishing process.
접합영역에 형성된 금속패드(18a)는 2000 내지 3000Å 의 두께를 가지므로 종래 콘택 홀에 비해 종횡비(Aspect Ratio)가 작아지므로 용이한 조건에서 콘택홀을 형성할 수 있다. 또한, 일반적인 자기정합 콘택 홀 식각시 얇은 식각방지막에서 식각을 정지시킬 필요가 없으므로 C/F가 높은 플라즈마를 사용하지 않아도 된다.Since the metal pad 18a formed in the junction region has a thickness of 2000 to 3000 Å, the aspect ratio is smaller than that of the conventional contact hole, so that the contact hole can be formed under easy conditions. In addition, in the self-aligned contact hole etching process, the etch stop does not need to be stopped in the thin etch stop layer, and thus the C / F high plasma may not be used.
상술한 바와같이, 본 발명은 식각이 정지되거나 소자를 손상시킬 가능성이 있는 식각방지막을 이용한 종래 자기정합 콘택 홀 형성방법과 달리 금속층(텅스텐) 에치백 공정으로 금속 패드를 형성한 후 콘택 홀을 형성함으로써 보다 안정된 공정을 실현할 수 있어 웨이퍼 형성되는 소자의 수율을 향상시킬 수 있다.As described above, the present invention is different from the conventional self-aligning contact hole forming method using an etch stop layer which may cause etching to be stopped or damage the device, and then forms a contact hole after forming a metal pad by a metal layer (tungsten) etchback process. By this, a more stable process can be implemented and the yield of the element formed by a wafer can be improved.
또한, 본 발명은 콘택 홀 형성전에 증착하는 층간절연막을 평탄화가 이루어진 상태에서 형성하므로 플로우만으로 평탄화가 가능하게 되어 공정의 단순화 및 제조원가를 낮출 수 있다. 그리고, 콘택 영역에 형성되는 금속 패드는 콘택 영역의 전반에 걸쳐 형성되므로 콘택의 접촉면적을 넓혀 콘택 저항을 낮추므로 소자의 전기적 특성을 향상시키고, 콘택 홀의 종횡비를 낮추어 콘택홀 식각공정을 보다 쉽게 진행할 수 있게 하여 콘택 홀 식각을 위한 전용 장비보다 저렴한 일반적인 산화막 식각 장비로도 고집적화된 소자의 콘택 홀 공정을 진행할 수 있어 장비 투자비가 절감되는 효과가 있다.In addition, in the present invention, since the interlayer insulating film deposited before forming the contact hole is formed in the planarization state, the planarization is possible only by the flow, thereby simplifying the process and lowering the manufacturing cost. In addition, since the metal pads formed in the contact region are formed throughout the contact region, the contact area of the contact region is increased to lower the contact resistance, thereby improving the electrical characteristics of the device, and reducing the aspect ratio of the contact hole, thereby making the contact hole etching process easier. In this way, the contact hole process of the highly integrated device can be performed even with the general oxide etching equipment which is cheaper than the dedicated equipment for the contact hole etching, thereby reducing the equipment investment cost.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7656087B2 (en) | 2003-11-27 | 2010-02-02 | Samsung Mobile Display Co., Ltd. | Flat panel display |
| US7893438B2 (en) | 2003-10-16 | 2011-02-22 | Samsung Mobile Display Co., Ltd. | Organic light-emitting display device including a planarization pattern and method for manufacturing the same |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7893438B2 (en) | 2003-10-16 | 2011-02-22 | Samsung Mobile Display Co., Ltd. | Organic light-emitting display device including a planarization pattern and method for manufacturing the same |
| US8283219B2 (en) | 2003-10-16 | 2012-10-09 | Samsung Display Co., Ltd. | Organic light-emitting display device and method for manufacturing the same |
| US7656087B2 (en) | 2003-11-27 | 2010-02-02 | Samsung Mobile Display Co., Ltd. | Flat panel display |
| US7936125B2 (en) | 2003-11-27 | 2011-05-03 | Samsung Mobile Display Co., Ltd. | Flat panel display |
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