KR20010064321A - Electrostatic discharge protecting circuit for CDM - Google Patents

Abstract

PURPOSE: An electrostatic protection circuit for CDM(Charged Device Model) is provided to protect a circuit from concentrated charges by forming a discharge device between a circuit arranged at both ends of a power line and the power line. CONSTITUTION: A circuit S1, an S2, and an S3 receive a grounding power of a VSS pad(20) from a VSS power line(10). A circuit SQ1, an SQ2, and an SQ3 receive a grounding power of a VSSQ pad(22) from a VSS power line(20). A discharge device(40) is formed with a P1, a P2, a P3, and a P4 arranged at an outside of the S1, the S3, the SQ1, and the SQ3. The S1, the S3, the SQ1, and the SQ3 is arranged at both ends of the VSS power lines(10,12). The discharge device(40) including the P1, the P2, the P3, and the P4 is a dummy well pickup device.

Description

Electrostatic discharge protection circuit for CDM {Electrostatic discharge protecting circuit for CDM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic protection circuit of a semiconductor device, and more particularly, to an electrostatic protection circuit for a CDM, in which an electrostatic discharge (ESD) characteristic of a power line is improved to improve product reliability.

As the degree of integration of semiconductor memory devices increases and the size of devices become smaller, the reliability of integrated circuits against ESD has become an important task, such as internal circuits being destroyed by lower voltages. This is because the submicron process technology makes the electrostatic discharge even worse by employing techniques such as thin oxide film, shallow junction, small contact area and short channel.

On the other hand, a semiconductor device often causes a fatal damage to an element by high voltage static electricity in various cases such as a manufacturing process or a distribution process. The process of damaging a device by static electricity has been largely divided into a human body model and a mechanical model. Recently, a charged device model (CDM), which is damaged by electric charges accumulated in a chip, has also been considered. .

In order to increase the immunity to CDM, most power lines use a static protection device such as a diode or a bipolar transistor to form a direct path to the power line at high potential, thereby protecting the internal circuit from static electricity due to accumulated charge.

FIG. 1 is a diagram illustrating an example of a power line structure of a conventional semiconductor device, and briefly illustrates a circuit configuration connected to a ground voltage VSS in a die 1. In accordance with the trend of higher integration, semiconductor memory devices are separating power lines of circuits from circuit to circuit. Accordingly, S1, S2, and S3 represent a circuit receiving ground power of the VSS pad 20 from the VSS power line 10, and SQ1, SQ2, and SQ3 represent VSSQ pads separated from the VSS power line 20. 22 shows a circuit receiving ground power. In addition, the areas A, B, C, and D are diagrams of relative positions in the die 1.

Then, in the CDM test of the semiconductor device, when the charge is discharged to the VSS pad 20 after the semiconductor device is charged, the electric charges existing in the regions B and C are dispersed through the S1, S2, and S3 circuits. The charge is almost concentrated in the S1 and S3 circuits, respectively.

At the same time, when the charge of the semiconductor chip is discharged by the VSSQ pad 22, the charge of the region C is distributed to the SQ1, SQ2 and SQ3 circuits, but the regions A and B are concentrated to the SQ1 circuit and the region D to the SQ3 circuit.

Currently, memory such as DRAM is being pushed toward making power pads and separating power lines according to a trend of increasing integration. As a result, when the electric charges charged in the semiconductor device are discharged, a large amount of electric charges are concentrated in a specific circuit disposed at the end of the power supply line, which inevitably weakens the immunity to the CDM. That is, the circuit disposed at the end of the power line has to discharge all the electric charges around the power line, and thus has a structure more vulnerable to static electricity than the circuit at the center of the power line.

SUMMARY OF THE INVENTION An object of the present invention is to provide a discharge element between a circuit disposed at both ends of a power supply line and a power supply line in order to solve the problems of the prior art. To provide an electrostatic protection circuit for the CDM.

1 is a view showing an example of a power line structure of a conventional semiconductor device;

2 is a view showing an example of a power supply line pad having a static electricity protection circuit for a CDM according to the present invention.

* Description of the symbols for the main parts of the drawings *

1: die

10, 12: power line

20, 22: power pad

30: circuits

40: Static electricity protection element

A, B, C, D: area

S1, S2, S3, S4: Circuits

SQ1, SQ2, SQ3, SQ4: Circuits

In order to achieve the above object, the present invention, in the electrostatic protection circuit of a semiconductor device having a power supply from the power pad to supply power to each circuit, but having a separate power line, the circuit outside disposed at both ends of each power line And a discharge device capable of discharging the electrostatic charge charged in the chip.

According to the present invention, it is possible to safely protect the circuit at the end portion of the power supply line where the static electricity due to the charged charge in the chip is most concentrated through the discharge element disposed at the end portion of the power supply line.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention, the same reference numerals are used for similar parts in the present embodiment.

2 is a view showing an example of a power line pad having a static electricity protection circuit for CDM according to the present invention, referring to the present invention, in the static electricity protection circuit of a semiconductor device having power lines separated from each other by circuit, A discharge element 40 capable of discharging the electrostatic charge charged in the chip is further configured outside the circuits S1, S3, SQ1, SQ3 disposed at both ends of each of the power lines 10, 12.

Here, the discharge device 40 is a dummy well pick up device connected to the power lines 10 and 12 and the outermost chip.

More specifically, the embodiment of the present invention briefly shows a circuit configuration connected to the ground voltage VSS in the die 1, similar to the conventional circuit configuration. S1, S2, and S3 are circuits for receiving ground power of the VSS pad 20 from the VSS power line 10, and SQ1, SQ2, and SQ3 are ground power for the VSSQ pad 22 separated from the VSS power line 20. It shows a circuit that is supplied with. The regions A, B, C, and D illustrate the relative positions in the die 1.

The present invention provides a power supply through a discharge element 40 including P1, P2, P3, and P4 disposed outside circuits S1, S3, SQ1, and SQ3 disposed at both ends of the VSS power lines 10, 12 of 10 and 12. It can discharge static electricity concentrated at the end of the line.

That is, in the CDM test of the present invention, when the charge is discharged to the VSS pad 20 after the semiconductor device is charged, the electric charges present near the regions B and C are dispersed through the S1, S2 and S3 circuits, and the regions A and D The nearby charge is discharged through the discharge elements P1 and P2 at the ends of the power supply line 10 before being applied to the S1 and S3 circuits.

At the same time, when the charge of the semiconductor chip is discharged by the VSSQ pad 22, the charges in the region C are dispersed in the SQ1, SQ2, and SQ3 circuits, and the charges in the regions A and B are at the end of the power supply line 12. At P3, the charge in the region D is discharged through the discharge element P4 at the other end.

Accordingly, the present invention reduces the amount of charge concentrated in the end circuits S1, S3, SQ1, and SQ3 of the power supply line by discharging in advance through the discharge elements 40 P1, P2, P3, and P4 disposed at both ends of the power supply line. Can be.

Although the discharge element of the present invention has been described with respect to the ground (VSS) power supply line in this embodiment, the same applies to the VCC power supply line.

As described above, when the discharge device is configured at the ends of all power lines separated from each other in the semiconductor device according to the present invention, the discharge amount of the electrostatic charge in the circuit at the end of the power line is reduced to have a strong resistance to fixed electricity. It can make a semiconductor device and improve the CDM characteristics of the chip.

Claims (3)

In the static electricity protection circuit of a semiconductor device that receives power from the power pad to supply power to each circuit, but having a separate power line, And electrostatic discharge circuits for discharging the electrostatic charges charged in the outer chips respectively disposed at both ends of the power line. 2. The static electricity protection circuit for a CDM according to claim 1, wherein the discharge element is a dummy well pip-up element connected to a power supply line and an outermost chip. The electrostatic protection circuit for a CDM according to claim 1, wherein the discharge element is provided on both VCC and VSS power lines.