KR20010064087A - Quadrature Amplitude Modulation Demodulator for symbol timing recovery with low noise and high speed - Google Patents

Abstract

PURPOSE: A quadrature amplitude modulation demodulator for low-nose high-speed symbol timing recovery is provided which performs symbol timing recovery for a signal including an error causing factor output from an interpolation and SRRC filter in response to a signal output from a lock detector during the initial operation and carries out the symbol timing recovery for a signal from which an error causing factor output from a carrier recovery unit is removed after locking has been made. CONSTITUTION: A low-noise high-speed QAM demodulator includes an analog-digital converter(100) for sampling a modulated analog signal into digital data with a predetermined frequency, and an interpolation and filtering circuit(110) for interpolating the sampled digital data in response to a sampling timing and filtering the data into a desired specific shape. The demodulator further has an equalizer(130) for receiving the data output from the interpolation and filtering circuit to remove an error causing factor generated due to interference between data, and a carrier recovering circuit(140) for receiving the data output from the equalizer to remove an error causing factor caused by a phase offset and frequency offset and outputting the data as a recovered final symbol. The demodulator also has a lock detector for performing a locking operation in response to the signal output from the carrier recovering circuit, and a symbol timing recovering circuit(120) for selectively receiving the data output from the interpolation and filtering circuit and the final symbol data output from the carrier recovering circuit to carry out symbol timing recovery.

Description

Quadrature Amplitude Modulation Demodulator for symbol timing recovery with low noise and high speed

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data communication technology, and more particularly, to a quadrature amplitude modulation (QAM) demodulator for low noise and high speed symbol timing recovery.

Recently, due to the increase in the use of the Internet and the popularization of video communication and multimedia contents, the amount of transmission data is rapidly increasing, and due to this trend, data transmission cannot be smoothly supported by the bandwidth of communication using existing communication networks and telephone lines. Therefore, in order to overcome these limitations, researches on high-speed communication networks such as an Asymmetric Digital Subscriber Line (ADSL) or a cable modem have been actively conducted and are currently being installed and operated.

In addition, in order to smoothly transmit data, a multi-level data transmission method that can transmit and receive more data at the same time according to the state of a transmission channel is introduced. Such multi-level data transmission is generally a QAM (Quadrature). Amplitude Modulation) A modulation / demodulation method is used.

On the other hand, the QAM demodulator includes a symbol timing recovery unit for determining an error of symbol timing by first receiving an internally modulated symbol and restoring the error, and the symbol timing recovery unit has a high speed operation and a low noise characteristic, and thus, a next stage of the demodulator. Smooth operation at can be guaranteed.

As is well known, an algorithm for determining and recovering a symbol timing error in a symbol timing recovery unit is Stochastic gradient timing recovery, which is mainly used for binary modulation schemes such as binary phase shift key (BPSK) and quadrature phase shift key (QPSK). Method and similar Minimum Mean Square Error method (Ref .: "Digital Communication", Edward Lee, David G. Messertschmitt, 1998, KluwerAcademic Publishers), Mueller method (IEEE TRANSACTION ON COMMUNICATIONS, VOL.COM-24, NO.5, MAY 1976, P516) and Early-Late mode. Since these algorithms have their own characteristics, it is necessary to select and implement a recovery algorithm suitable for timing recovery.

First, Stochastic gradient timing recovery method, Minimum Mean Square Error method, and Mueller method are Decision-directed methods. If the value determined initially has an error, it does not converge or takes time to converge even if it converges. It has a long disadvantage. The Stochastic gradient timing recovery method and the Minimum Mean Square Error method take several samples per symbol, whereas the Mueller method takes only one sample per symbol, so that it can be implemented even if the performance of the sampler decreases. Although preferred, in recent years the performance of samplers has not been used much because it is sufficient to take multiple samples per symbol. However, even if the sampler takes several samples per symbol, the hardware resource for processing it is larger than the hardware resource required to take one sample per symbol, which may be a weak point in chip design and production. .

In addition, the Stochastic gradient timing recovery method, the Minimum Mean Square Error method, and the Mueller method all have the advantage of having small timing jitter once converged. However, when the number of constellations is more than 256, the spacing between levels is so small that even a relatively small timing jitter value may adversely affect the smooth operation of symbol timing error recovery.

On the other hand, Early-Late method has good characteristics for symmetric data transmission and binary modulation by observing change of polarity of input signal and discriminating symbol timing error. . In addition, since there is no need for interworking with an equalizer, it is possible to operate independently and has another advantage of reducing peripheral control logic. However, in the case of multi-level data transmission, since zero-crossing at a predetermined interval cannot be expected, timing jitter is very disadvantageous. Because of this, it is rarely used in QAM modulators.

Various reconstruction algorithms as described above include the immunity to white noise, the immunity to errors caused by phase offsets, and the errors caused by frequency offsets. Immunity to errors caused by immunity and inter-symbol interference (ISI) for the C-PN may provide good performance. In most QAM demodulators, the Square Root Raised Cosine (SRRC) filter and symbol timing recovery unit are located after an output stage of an analog-to-digital converter (hereinafter referred to as an ADC) that samples a modulated analog signal into digital data of a constant frequency. A symbol timing recovery operation is performed on a symbol including an error causing factor. Therefore, the symbol timing recovery unit should extract an appropriate sampling point irrespective of the immunity for various error-causing factors, and consider this from the initial reconstruction algorithm selection stage and undergo several experiments. However, the implementation of an algorithm that satisfies this part requires a lot of hardware resources, which increases production costs and causes secondary problems such as heat generation due to an increase in chip area.

The present invention has been made to solve the above problems, and an object thereof is to provide a QAM demodulator capable of performing a low noise and fast symbol timing recovery operation.

1 is a block diagram of a typical QAM modulator.

2 is a block diagram of a QAM demodulator in accordance with an embodiment of the present invention.

* Description of the main parts of the drawing

100: ADC 110: interpolation and SRRC filter unit

120: symbol timing recovery unit 130: equalizer

140: carrier restorer 160: lock detector

According to an aspect of the present invention, there is provided a low noise and high speed QAM demodulator comprising: analog-to-digital conversion means for sampling a modulated analog signal input by being modulated from a transmitting side into digital data having a constant frequency; Interpolation and filtering means for filtering an interpolation operation on sampled digital data output from said analog-to-digital conversion means and filtering pulses of the sampled digital data to a desired specific shape in response to a sampling timing; Equalizing means for receiving data output from the interpolation and filtering means and eliminating error-causing factors caused by interference between data; Carrier recovery means for receiving the data output from the equalizing means and removing the error inducing factors caused by the phase offset and the frequency offset and outputting the recovered final symbols; Lock detecting means for performing a lock operation in response to a signal output from the carrier recovery means; And selectively receiving data output from the interpolation and filtering means or recovered final symbol data output from the carrier recovery means in response to a lock signal output from the lock detecting means, and performing a symbol timing recovery operation. In operation, a symbol timing recovery operation is performed on the data output from the interpolation and filtering means, and after a lock is detected by the lock detecting means, a symbol timing recovery operation is performed on the final symbol data output from the carrier recovery means. Symbol timing recovery means for performing the operation.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

Briefly summarized, the QAM demodulator of the present invention further includes a lock detector for performing a lock operation in response to a signal output from the carrier restoring unit, and responding to a signal output from the lock detector. Symbol timing recovery having a small timing jitter value by selectively outputting a signal including an error causing factor output from an SRRC filter unit or a signal from which an error causing factor is removed through an equalizer and a carrier recovery unit to a determination unit of a symbol timing recovery unit. Enable operation.

FIG. 1 is a block diagram of a general QAM modulator. The ADC 100 is configured to sample a modulated analog signal, which is modulated and input from a transmitter, into digital data of a constant frequency, and is output from the ADC 100 in response to a sampling timing. Interpolation and SRRC filter unit 110, and interpolation from the SRRC filter unit 110 to interpolate the sampled digital data, and to filter the pulses of the sampled digital data into a desired shape. Eliminates error-causing factors caused by interference (ISI) between the symbol timing recovery unit 120 and the recovered data output from the symbol timing recovery unit 120 for receiving the sample data and performing the symbol timing recovery operation. Error caused by a phase offset and a frequency offset with respect to the equalizer 130 and the data output from the equalizer 130. After removal of the carrier consists of a recovery unit 140 for a final output to the recovered symbol.

Referring to FIG. 1, first, an analog signal modulated by the ADC 100 is input, and the ADC 100 receiving the input signal outputs the digitally converted sample signal to the interpolation and SRRC filter unit 110. Subsequently, a determination unit (not shown) provided inside the symbol timing recovery unit 120 receives an appropriate determination value in response to the interpolated and interpolated sample data from the SRRC filter unit 110. The signal, which is not shown in the figure, and filtered through the loop filter, is sent to an internally controlled oscillator (NCO) or a direct digital synthesizer (DDS). Then, the output value of the NCO or DDS is input to the interpolation and SRRC filter unit 110 to indicate an appropriate sampling point, and then a signal in a symbol unit is output through the SRRC filter. However, the reconstruction operation of the symbol timing recovery unit is performed in response to data from the interpolation and SRRC filter unit 110 including error inducing factors due to phase offset, frequency offset, and intersymbol interference (ISI). In the restoration operation of the symbol timing restoration unit 120, a malfunction may be caused.

2 is a block diagram of a QAM demodulator according to an embodiment of the present invention.

2, the QAM demodulator of the present invention outputs from the ADC 100 in response to the sampling timing and the ADC 100 for sampling the modulated analog signal, which is modulated and input from the transmitting side, into digital data of a constant frequency. Interpolation and SRRC filter unit 110 for filtering an interpolation operation on the sampled digital data and a pulse of the sampled digital data into a desired shape, and interpolation output from the interpolation and SRRC filter unit 110. The equalizer 130 for removing the error-caused factors caused by the interference (ISI) between the received sample data and the error-induced factors due to the phase offset and the frequency offset with respect to the data output from the equalizer 130. After removing the signal, the carrier recovery unit 140 outputs the recovered final symbol and the signal output from the carrier recovery unit 140. The lock detector 160 performing a lock operation and the interpolated sample data from the SRRC filter unit 110 or the carrier reconstructor 140 in response to a signal output from the lock detector 160. The symbol timing recovery unit 120 is configured to selectively receive the symbol data output from the symbol timing recovery operation, and the symbol timing recovery unit 120 responds to the signal output from the lock detector 160. A multiplexer (MUX) 122 for selecting one of the sample data from the interpolation and SRRC filter unit 110 or the recovered symbol data output from the carrier recovery unit 140 to output from the multiplexer 122 A determination unit 124 for determining an error of symbol timing by receiving a signal to be input, and filtering an error signal output from the determination unit 124 to perform the interpolation and SRRC filter unit ( Any necessary for the interpolation and the interpolation operation in the SRRC filter unit 110 in response to the loop filter 126 for outputting the update signal for correcting the sampling timing of the 110 and the update signal from the loop filter 126. NCO or DDS unit 128 for outputting a value specifying a sampling point (coefficient) of the, the carrier recovery unit 140 is a phase detector 142 for detecting the phase of the recovered last symbol, the A loop filter 144 for filtering the detected signal output from the phase detector 142, and an arbitrary sampling point required for the output of the restored last symbol in response to the signal output from the loop filter 144 The NCO or DDS unit 146 for outputting a value to be multiplied by the signal output from the equalizer 130 and the value output from the NCO or DDS unit 146 is restored A multiplier 148 outputs the final result as a symbol.

The operation of the QAM modulator configured as described above will be described in detail with reference to FIG.

First, an analog signal modulated by the ADC 100 is input, and the ADC 100 receiving the input signal outputs the digitally converted sample signal to the interpolation and SRRC filter unit 110. At this time, since the value initially output from the lock detector 160 is not locked, the multiplexer 122 of the symbol timing recovery unit 120 selects the output value of the interpolation and SRRC filter unit 110 to the determination unit 124. Output Next, the determination unit 124 provided in the symbol timing recovery unit 120 outputs an appropriate determination value to the loop filter 126 according to the interpolation output from the multiplexer 122 and the output value of the SRRC filter unit 110. The output of the loop filter 126 is input to the NCO or the DDS unit 128. The output value of the NCO or DDS unit 128 is input to the interpolation and SRRC filter unit 110 to indicate an appropriate sampling point so that a signal in a symbol unit is output through the SRRC filter unit 110. However, the symbol signal output at this time includes error inducing factors due to phase offset, frequency offset, and inter-symbol interference (ISI), and the symbol signal enters the input of the discriminating unit 124, thereby causing symbol timing due to timing jitter. The lock of the recovery unit 120 is not maintained and the optimal sampling point is shaken by repeating the lock-unlock state.

On the other hand, the symbol signal output from the interpolation and SRRC filter unit 110 passes through the equalizer 130, thereby eliminating error-caused factors caused by inter-symbol interference (ISI), and through the carrier recovery unit 140, phase offset and Error-causing factors due to frequency offset are eliminated. As a result, after performing the equalization operation through the equalizer 130 and the carrier recovery operation through the carrier recovery unit 140, an appropriate final symbol signal may be obtained. However, as described above, if the optimal sampling point is shaken in the symbol timing recovery unit 120 to accurately extract the symbol, an incorrect symbol is input to the equalizer 130 and the carrier recovery unit 140 to perform an accurate demodulation function. You won't be able to.

The optimal sampling point in the symbol timing recovery unit 120 is shaken because the output of the loop filter 126 does not diverge but swings irregularly based on a certain value with jitter. When the determination unit 124 of the recovery unit 120 receives the final symbol signal of the carrier recovery unit 140 through the multiplexer 122 as a feedback, the determination unit 124 of the recovery unit 120 is input to the determination unit 124 of the symbol timing recovery unit 120. Since the signal is a signal in which various error sources are eliminated, an accurate sampling point can be output. At this time, the multiplexer 122 monitors the output of the NCO or the DDS unit 146 of the carrier recovery unit 140 in response to the signal output from the lock detector 160 for detecting whether the lock is detected or not. The final symbol signal of is selected. Here, the lock detector 160 observes the output of the NCO or the DDS unit 146 to observe how much a certain threshold value is maintained, and detects that a lock has been detected when the value is maintained for a predetermined time and then detected. Is output to the multiplexer 122.

The lock detector 160 may be configured by a simple counter circuit, and a detailed description of the internal configuration is omitted here.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, a lock detector for performing a lock operation in response to a signal output from a carrier restoring unit includes a lock detector for performing an initial operation in response to a signal output from the lock detector. The symbol timing recovery operation is performed on a signal including an error inducing factor output from the interpolation and SRRC filter unit, and after the lock is performed, the symbol timing recovery operation is performed on a signal from which the error inducing factor output from the carrier recovery unit is removed. As a result, a symbol timing recovery operation may be performed at a lower noise and a higher speed than in the related art.

Claims (5)

In low noise and high speed QAM demodulator, Analog-to-digital converting means for sampling the modulated analog signal input by being modulated from the transmitting side into digital data of a constant frequency; Interpolation and filtering means for filtering an interpolation operation on sampled digital data output from said analog-to-digital conversion means and filtering pulses of the sampled digital data to a desired specific shape in response to a sampling timing; Equalizing means for receiving data output from the interpolation and filtering means and eliminating error-causing factors caused by interference between data; Carrier recovery means for receiving the data output from the equalizing means and removing the error inducing factors caused by the phase offset and the frequency offset and outputting the recovered final symbols; Lock detecting means for performing a lock operation in response to a signal output from the carrier recovery means; And In response to the lock signal output from the lock detecting means, a symbol timing recovery operation may be performed by selectively receiving data output from the interpolation and filtering means or recovered final symbol data output from the carrier recovery means. Perform symbol timing recovery operation on the data output from the interpolation and filtering means, and perform symbol symbol recovery operation on the final symbol data output from the carrier recovery means after the lock is detected by the lock detecting means. Symbol timing recovery means for performing Low noise and high speed QAM demodulator comprising a. The method of claim 1, wherein the symbol timing recovery means, Selection means for selectively outputting data from the interpolation and filtering means or recovered last symbol data output from the carrier recovery means in response to the lock signal output from the lock detecting means; Discriminating means for discriminating an error in symbol timing with respect to data from said interpolation and filtering means output from said selecting means or recovered last symbol data output from said carrier recovery means; And First loop filtering means for outputting an update signal for correcting a sampling timing of the interpolation and filtering means by filtering an error signal output from the determining means Low noise and high speed QAM demodulator comprising a. The method of claim 2, wherein the symbol timing recovery means, Means for outputting a value for designating an arbitrary sampling point necessary for an interpolation operation in the interpolation and filtering means in response to an update signal from the loop filtering means A low noise and high speed QAM demodulator further comprising. The method of claim 2, wherein the carrier recovery means, Phase detecting means for detecting a phase of the recovered last symbol data; Second loop filtering means for filtering the detected signal output from said phase detecting means; First means for outputting a value for designating an arbitrary sampling point necessary for outputting the restored final symbol data in response to a signal output from the second loop filtering means; And Multiplication means for multiplying the signal output from the equalizing means with the value output from the first means to finally output the reconstructed final symbol data Low noise and high speed QAM demodulator comprising a. The method of claim 4, wherein the lock detecting means, And outputting said lock signal to said selection means when the output of said first means maintains a predetermined threshold value for a predetermined time or more and outputs said lock signal to said selection means.