KR20010064034A - Method for fabricating a MOS transistor having a raised source/drain - Google Patents
Method for fabricating a MOS transistor having a raised source/drain Download PDFInfo
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- KR20010064034A KR20010064034A KR1019990062149A KR19990062149A KR20010064034A KR 20010064034 A KR20010064034 A KR 20010064034A KR 1019990062149 A KR1019990062149 A KR 1019990062149A KR 19990062149 A KR19990062149 A KR 19990062149A KR 20010064034 A KR20010064034 A KR 20010064034A
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- 238000000034 method Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 150000004767 nitrides Chemical class 0.000 claims abstract description 8
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 3
- 239000011800 void material Substances 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 4
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 235000011007 phosphoric acid Nutrition 0.000 abstract 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract 1
- 230000008016 vaporization Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
- H01L29/41783—Raised source or drain electrodes self aligned with the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 트랜지스터의 제조방법에 관한 것으로, 특히 돌출형 소오스/드레인(raised source/drain)을 갖는 모스(MOS) 트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a transistor, and more particularly to a method of manufacturing a MOS transistor having a raised source / drain (raised source / drain).
서브 미크론(sub-micron) 이하의 숏 채널(short channel) 트랜지스터에서는 숏 채널 효과를 개선하기 위하여 얕은 접합(shallow junction)이 필수적이다. 얕은접합을 형성하기 위한 하나의 방법으로, 소오스/드레인 영역에 선택적으로 에피택셜층을 형성하여 돌출 소오스/드레인을 형성하는 방법이 있다. 그러나, 이 방법에 의하면, 게이트전극과 돌출 소오스/드레인 사이의 기생 캐패시턴스가 증가하여 트랜지스터의 알씨 지연시간(RC delay time)이 길어져 소자의 동작속도가 저하되는 문제점이 있다.In short channel transistors below sub-micron, shallow junctions are essential to improve short channel effects. One method for forming a shallow junction is to form an epitaxial layer selectively in the source / drain region to form a protruding source / drain. However, according to this method, there is a problem in that the parasitic capacitance between the gate electrode and the protruding source / drain increases, so that the RC delay time of the transistor becomes long and the operation speed of the device decreases.
따라서, 본 발명이 이루고자 하는 기술적 과제는, 게이트와 소오스/드레인 사이의기생 캐패시턴스를 최소화하며 얕은 접합을 형성할 수 있는 돌출 소오스/드레인을 갖는 모스 트랜지스터의 제조방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a method of manufacturing a MOS transistor having a protruding source / drain capable of forming a shallow junction while minimizing the parasitic capacitance between the gate and the source / drain.
도 1 내지 도 5는 본 발명의 실시예에 의한 돌출 소오스/드레인을 갖는 모스 트랜지스터의 제조과정을 나타낸 단면도들이다.1 to 5 are cross-sectional views illustrating a manufacturing process of a MOS transistor having a protruding source / drain according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
2.....반도체기판 4.....소자분리막2 ... semiconductor substrate 4 ..... element separation membrane
6.....게이트절연막 8.....게이트전극6 ..... gate insulating film 8 ..... gate electrode
10.....산화막 12.....스페이서10 ..... oxide 12 ..... spacer
14a, 14b.....에피택셜층 16.....절연막14a, 14b..epitaxial layer 16..insulating film
18.....소오스/드레인18 ..... source / drain
상기 과제를 이루기 위하여 본 발명에 의한 돌출 소오스/드레인을 갖는 모스 트랜지스터의 제조방법은, 반도체기판의 활성영역에 게이트절연막을 개재하여 게이트전극을 형성하는 단계와, 상기 게이트전극의 측면에 스페이서를 형성하는 단계와, 상기 반도체기판의 표면상에 선택적으로 실리콘층을 형성하는 단계와, 상기 스페이서를 제거하는 단계와, 결과물상에 절연막을 증착한 후 이방성식각하여, 상기 게이트전극과 상기 실리콘층 사이에 보이드가 형성되도록 하는 단계, 및 상기 반도체기판에 불순물을 이온주입하여 소오스/드레인을 형성하는 단계를 구비하는 것을 특징으로 한다.According to the present invention, there is provided a method of manufacturing a MOS transistor having a protruding source / drain according to the present invention, including forming a gate electrode through a gate insulating film in an active region of a semiconductor substrate, and forming a spacer on a side of the gate electrode. And selectively forming a silicon layer on a surface of the semiconductor substrate, removing the spacer, depositing an insulating film on the resultant, and then anisotropically etching the gap between the gate electrode and the silicon layer. And forming a source / drain by ion implanting impurities into the semiconductor substrate.
본 발명에 있어서, 상기 스페이서는, 실리콘층 및 열산화막에 대하여 선택적으로 제거될 수 있는 물질로 형성한다. 그리고, 상기 절연막은 단차 피복성이 불량한 물질로서, 플라즈마 화학기상증착(CVD) 법을 이용한 산화막 또는 질화막으로 형성하는 것이 바람직하다.In the present invention, the spacer is formed of a material that can be selectively removed with respect to the silicon layer and the thermal oxide film. The insulating film is a material having poor step coverage, and is preferably formed of an oxide film or a nitride film using a plasma chemical vapor deposition (CVD) method.
본 발명에 따르면, 게이트전극과 돌출 소오스/드레인 사이에 보이드가 형성되도록 함으로써, 게이트전극과 소오스/드레인 사이의 기생 캐패시턴스의 형성되는 것을 억제할 수 있다.According to the present invention, by forming a void between the gate electrode and the protruding source / drain, the formation of parasitic capacitance between the gate electrode and the source / drain can be suppressed.
이하, 첨부된 도면을 참조하여 본 발명을 더욱 상세히 설명하기로 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
도 1 내지 도 5는 본 발명의 실시예에 의한 돌출 소오스/드레인을 갖는 모스 트랜지스터의 제조과정을 나타낸 단면도들이다.1 to 5 are cross-sectional views illustrating a manufacturing process of a MOS transistor having a protruding source / drain according to an embodiment of the present invention.
도 1을 참조하면, 반도체기판(2)의 표면에 통상의 소자분리 공정을 이용하여, 반도체기판을 활성영역과 비활성영역으로 구분하기 위한 소자분리막(4)을 형성한다. 다음, 반도체기판(2)의 전면에 절연막을 형성하고, 그 위에 도우프된 폴리실리콘을 증착한 다음, 폴리실리콘막과 절연막을 차례로 패터닝하여 게이트절연막(6) 및 게이트전극(8)을 형성한다. 다음에, 상기 게이트전극의 측면을 산화시켜 산화막(10)을 형성한다. 이 결과물 상에, 예컨대 질화막을 200 ∼ 700Å 정도의 두께로 형성한 다음 에치백하여 산화막이 형성된 상기 게이트전극의 측벽에 스페이서(12)를 형성한다.Referring to FIG. 1, a device isolation film 4 is formed on the surface of the semiconductor substrate 2 to separate the semiconductor substrate into an active region and an inactive region by using a conventional device isolation process. Next, an insulating film is formed on the entire surface of the semiconductor substrate 2, and the doped polysilicon is deposited thereon, and then the polysilicon film and the insulating film are patterned in order to form a gate insulating film 6 and a gate electrode 8. . Next, the side surface of the gate electrode is oxidized to form an oxide film 10. On this resultant, for example, a nitride film is formed to a thickness of about 200 to 700 GPa and then etched back to form a spacer 12 on the sidewall of the gate electrode on which the oxide film is formed.
상기 스페이서(12)는 실리콘(Si) 및 열산화막에 대하여 화학용액을 이용하여 선택적으로 제거될 수 있는 막, 예를 들어 질화막 또는 CVD 산화막으로 형성하는 것이 바람직하다.The spacer 12 is preferably formed of a film that can be selectively removed using a chemical solution with respect to silicon (Si) and a thermal oxide film, for example, a nitride film or a CVD oxide film.
도 2를 참조하면, 결과물 상에 선택적 에피택셜 성장(Selective EpitaxialGrowth; SEG)법을 이용하여 게이트전극(8)의 상부 표면 및 반도체기판(2)의 표면에 에피택셜층(14a, 14b)을 형성한다. 상기 반도체기판의 표면에 형성된 에피택셜층(14b)은 돌출 소오스/드레인이 형성될 영역으로, 500 ∼ 700Å의두께로 형성한다. 게이트전극(8)과 돌출 소오스/드레인 사이에 형성된 스페이서(12)로 인해 기생 캐패시턴스가 형성되는데, 이를 최소화하기 위하여 다음의 공정을 진행한다.Referring to FIG. 2, epitaxial layers 14a and 14b are formed on the top surface of the gate electrode 8 and the surface of the semiconductor substrate 2 by using selective epitaxial growth (SEG). do. The epitaxial layer 14b formed on the surface of the semiconductor substrate is a region in which protruding sources / drains are to be formed, and is formed to have a thickness of 500 to 700 GPa. The parasitic capacitance is formed by the spacer 12 formed between the gate electrode 8 and the protruding source / drain. In order to minimize this, the following process is performed.
한편, 상기 게이트전극의 상부 표면에는 에피택셜층이 형성되지 않도록 하려면, 도우프된 폴리실리콘막을 증착한 상태에서 그 위에 절연막을 형성한 후에 게이트 패터닝을 하고, SEG 공정을 진행하면 된다.On the other hand, in order to prevent the epitaxial layer from being formed on the upper surface of the gate electrode, the insulating film is formed on the doped polysilicon film, and then gate patterning is performed, and the SEG process is performed.
도 3을 참조하면, 인산용액(H3PO4)을 이용하여 게이트전극의 측벽에 형성된 질화막 스페이서(도 2의 12)를 습식식각하여 제거한다. 그러면, 도시된 바와 같이 게이트전극과 에피택셜층(14b) 사이에 공간이 생기게 된다.Referring to FIG. 3, the nitride spacer (12 of FIG. 2) formed on the sidewall of the gate electrode is wet-etched using phosphoric acid solution H 3 PO 4 . As a result, a space is formed between the gate electrode and the epitaxial layer 14b.
이 때, 게이트전극과 에피택셜층 사이의 공간(참조부호 a)의 어스펙트 비(aspect ratio)가 2 이상이 되면 후속 공정에서 단차 피복성이 불량한 절연막을 증착할 때 보이드가 용이하게 형성될 수 있으므로, 스페이서(도 2의 12)의 두께 및 에피택셜층(14b)의 두께를 조절하는 것이 바람직하다.At this time, if the aspect ratio of the space between the gate electrode and the epitaxial layer (reference a) is 2 or more, voids may be easily formed when the insulating film having poor step coverage is deposited in a subsequent step. Therefore, it is preferable to adjust the thickness of the spacer (12 in Fig. 2) and the thickness of the epitaxial layer 14b.
도 4를 참조하면, 스페이서가 제거된 결과물 상에, 단차 피복성(step coverage)가 불량한 증착법, 예를 들어 플라즈마 화학기상증착(CVD) 산화막 또는 질화막을 200 ∼ 500Å 정도의 두께로 증착하여 절연막(16)을 형성한다. 다음에, 증착된 절연막(16)을 식각하여 스페이서 형태가 되도록 하면, 도시된 바와 같이,스페이서가 형성되어있던 부분, 즉 게이트전극과 돌출 소오스/드레인이 형성될 에피택셜층(14b) 사이에 보이드가 형성된다. 따라서, 게이트전극(8)과 돌출 소오스/드레인 사이의 기생 캐패시턴스를 최소화할 수 있다.Referring to FIG. 4, a deposition method having poor step coverage, for example, a plasma chemical vapor deposition (CVD) oxide film or a nitride film, is deposited to a thickness of about 200 to 500 GPa on a resultant product in which a spacer is removed. 16). Next, when the deposited insulating film 16 is etched to form a spacer, as shown, voids are formed between the portion where the spacer is formed, that is, between the gate electrode and the epitaxial layer 14b on which the protruding source / drain is to be formed. Is formed. Therefore, parasitic capacitance between the gate electrode 8 and the protruding source / drain can be minimized.
도 5를 참조하면, 상기 반도체기판(2)에 불순물이온을 주입한 다음에 이를 활성화하여 소오스/드레인(18)을 형성한다. 언급한 바와 같이, 게이트전극(8)과 소오스/드레인 사이에 종래의 유전체막이 되는 질화막 스페이서가 제거되고 보이드가 존재하기 때문에, 기생 캐패시턴스가 형성되지 않게 된다.Referring to FIG. 5, impurity ions are implanted into the semiconductor substrate 2 and then activated to form a source / drain 18. As mentioned, the parasitic capacitance is not formed because the nitride film spacer which becomes the conventional dielectric film and voids exist between the gate electrode 8 and the source / drain.
이상 본 발명을 상세히 설명하였으나 본 발명은 상기한 실시예에 한정되지 않고 본 발명의 기술적 사상내에서 많은 변형 및 개량이 가능하다.Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiments, and many modifications and improvements are possible within the spirit of the present invention.
상술한 본 발명에 의한 돌출 소오스/드레인을 갖는 모스 트랜지스터의 제조방법에 의하면, 게이트전극과 돌출 소오스/드레인 사이에 보이드가 형성되도록 함으로써, 게이트전극과 소오스/드레인 사이의 기생 캐패시턴스의 형성되는 것을 억제할 수 있다. 따라서, 소자의 동작속도가 저하되는 문제를 방지할 수 있다.According to the manufacturing method of the MOS transistor having the protruding source / drain according to the present invention described above, by forming a void between the gate electrode and the protruding source / drain, the formation of parasitic capacitance between the gate electrode and the source / drain is suppressed. can do. Therefore, the problem that the operation speed of an element falls can be prevented.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990062149A KR20010064034A (en) | 1999-12-24 | 1999-12-24 | Method for fabricating a MOS transistor having a raised source/drain |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990062149A KR20010064034A (en) | 1999-12-24 | 1999-12-24 | Method for fabricating a MOS transistor having a raised source/drain |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010064034A true KR20010064034A (en) | 2001-07-09 |
Family
ID=19629704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990062149A KR20010064034A (en) | 1999-12-24 | 1999-12-24 | Method for fabricating a MOS transistor having a raised source/drain |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010064034A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100623328B1 (en) * | 2002-07-05 | 2006-09-11 | 매그나칩 반도체 유한회사 | Method for fabrication cmos transistor of semiconductor device |
| CN112928154A (en) * | 2021-01-26 | 2021-06-08 | 微龛(广州)半导体有限公司 | Three-dimensional monolithic integrated device structure and preparation method thereof |
-
1999
- 1999-12-24 KR KR1019990062149A patent/KR20010064034A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100623328B1 (en) * | 2002-07-05 | 2006-09-11 | 매그나칩 반도체 유한회사 | Method for fabrication cmos transistor of semiconductor device |
| CN112928154A (en) * | 2021-01-26 | 2021-06-08 | 微龛(广州)半导体有限公司 | Three-dimensional monolithic integrated device structure and preparation method thereof |
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