KR20010063077A - Level shifter - Google Patents

Abstract

PURPOSE: A level shifter is provided which prevents signal delay and carries out a voltage level shifting operation and clocking pipeline operation simultaneously to reduce clock access time. CONSTITUTION: A level shifter includes the first inverter(IN1) for inverting a control signal, the first NAND gate(NA1) for NANDing the signal of the first inverter and a clock signal and then inverting the NANDed signal, and the second NAND gate(NA2) for transmitting a data path signal to the second NMOS transistor(NM2). The level shifter further has the first NMOS transistor(NM1) for receiving the output signal of the first NAND gate, the second NMOS transistor(NM2) for determining a data path according to the signal of the second NAND gate, and the third NMOS transistor(NM3) for receiving the signal of the first NAND gate. The level shifter also has the first and second PMOS transistors(PM1,PM2) whose drains are connected to the drains of the first and second NMOS transistors, the fourth NMOS transistor(NM4) for receiving the signal of the drain of the second PMOS transistor, the second inverter(IN2) for inverting the signal of the drain of the second PMOS transistor, and the third inverter(IN3) for transmitting a signal to the gate of the fourth NMOS transistor.

Description

Level Shifter {LEVEL SHIFTER}

The present invention relates to a level shifter, and more particularly, to a level shifter for improving clock access time by combining a clock signal transfer operation and a voltage level shifter operation.

Referring to the accompanying drawings, a conventional level shifter will be described.

1 is a circuit diagram illustrating a conventional level shifter.

In the conventional level shifter, as shown in FIG. 1, the NOA gate NR inverts and then inverts the LE and the QCLK signals, and the first inverter IN1 inverts and outputs the signal of the NOA gate NR. And a first and second clock inverters CIN1 and CIN2 for clock latches, and a second inverter IN2 latched with the second clock inverter CIN2 and inverting a signal of the first clock inverter CIN1. The first and second PMOS transistors PM1 and PM2 having the pipeline latch unit, the gates thereof connected to the drains, and the drains and the first gates of the first PMOS transistors PM1 connected to the internal power supply. The first NMOS transistor NM1 connected between the output signal terminal of the second inverter IN2 and the second inverter IN2 signal are inputted to the gate, and are connected between the drain and the ground voltage terminal of the second PMOS transistor PM2. Connected second NMOS transistor PM2 and the second PMOS transistor It is comprised including the 3rd inverter IN3 for inverting the signal of the drain of PM2.

The first clock inverter CIN1 receives the enable signal from the noar gate NR, and the second clock inverter CIN2 receives the enable signal from the first inverter IN1.

Referring to the operation of the conventional level shifter configured as described above are as follows.

First, the operation of the conventional level shifter when LE is "1" will be described.

Since LE is "1", the NOR gate NR outputs a low signal regardless of the signal of QCLK. At this time, the first clock inverter CIN1 is turned on and the second clock inverter CIN2 is turned off.

Accordingly, the output of the second NAND gate NA2 is bypassed to the first node N1 as it is through the first clock inverter CIN1 and the second inverter IN2.

In this case, when the output of the bypassed second NAND gate NA2 is low, the first node N1 has a low level. Accordingly, the second node N2 has a low level. do.

The second PMOS transistor PM2 receiving the low signal of the second node N2 is turned on so that the third node N3 becomes high and low to the output terminal through the third inverter IN3. ) Signal is output.

Next, when the output of the bypassed second NAND gate NA2 is high, a high signal is applied to the first node N1, and the second NMOS transistor NM2 is turned on.

Accordingly, the third node N3 falls to a low signal and the first PMOS transistor PM1 is turned on.

The second node N2 rises to an external voltage level, and the second PMOS transistor PM2 is turned off by the raised level signal.

Hereinafter, the operation when LE is "0" will be described.

When LE is "0", the output of the noble gate NR is changed by the signal of QCLK.

If QCLK is High, the operation is the same as when LE is "1".

Next, when QCLK is low, the first clock inverter CIN1 is turned off, and the second clock inverter CIN2 is turned on so that the input value when the QCLK is high is the second clock inverter CIN2. And through the second inverter IN2.

The subsequent level shifting operation is the same as when LE is "1".

The conventional level shifter as described above has the following problems.

Since the operation of level shifting to an external voltage is performed after the clocking operation, it is difficult to perform the high speed operation because the clock access time is reduced.

The present invention has been made to solve the above problems, and in particular, a level shifter suitable for reducing the clock access time by preventing the signal delay due to the level shifter and also performing the operation of the clocking pipeline together with the voltage level shifting operation. The purpose is to provide.

1 is a circuit diagram showing a conventional level shifter

2 is a circuit diagram illustrating a level shifter according to an embodiment of the present invention.

In order to achieve the above object, the level shifter of the present invention logically multiplies the signal of the first inverter (IN1) and the clock signal (QCLKB) of the first inverter (IN1) by inverting the control signal (LE). The inverted first NAND gate NA1, the second NAND gate NA2 for transferring the data path signal to the second NMOS transistor NM2, and the output signal of the first NAND gate NA1. Of the first NMOS transistor NM1, the second NMOS transistor NM2 that determines a data path according to the signal of the second NAND gate, and the first NAND gate NA1. A third NMOS transistor NM3 connected between a source terminal of the 2 NMOS transistor NM2 and a ground voltage terminal, and a gate end of each of the NMOS transistors NM2 are connected to the drain terminal to form a cross-coupling. The first and second NMOS transistors NM1 and NM The first and second PMOS transistors PM1 and PM2 and the drain terminals of the second PMOS transistor PM2 and the second PMOS transistor PM2 are respectively connected to the drain terminal of the second PMOS transistor PM1. A fourth NMOS transistor NM4 connected between the drain terminal and the ground voltage terminal, a second inverter IN2 for inverting the signal of the drain terminal of the second PMOS transistor PM2, and the second And a third inverter IN3 latched with the inverter IN2 and transmitting a signal to the gate of the fourth NMOS transistor.

Referring to the accompanying drawings, a level shifter according to an embodiment of the present invention will be described.

2 is a circuit diagram illustrating a level shifter according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the level shifter according to the embodiment of the present invention inverts the first inverter IN1 that inverts the signal of LE (Latency), and inversely multiplies the signal of the first inverter IN1 by the QCLKB signal. A first NAND gate NA1, a second NAND gate NA2 for performing a logical operation to transfer a data path to a second NMOS transistor NM2, and an output signal of the first NAND gate NA1. The first NMOS transistor NM1 operates by receiving a signal, the second NMOS transistor NM2 operates by receiving a signal of a data path through the first NMOS transistor, and the signal of the first NAND gate NA1. A third NMOS transistor NM3 that is input and is connected between the second NMOS transistor NM2 and the ground voltage terminal, and a gate of each other is connected to a drain to form a cross-coupling. To the drain of the MOS transistors NM1 and NM2. Each of the first and second PMOS transistors PM1 and PM2 configured to be connected to each other, the drain signal of the second PMOS transistor PM2 is input, and the drain and ground voltage terminals of the first PMOS transistor PM1 are received. A fourth NMOS transistor NM4 connected therebetween, a second inverter IN2 for inverting a signal at the drain terminal of the second PMOS transistor PM2, and a third inverter IN3 latched. It is.

In this case, the fourth NMOS transistor NM4 is configured to hold the drain of the first PMOS transistor PM1 low when the input of the second inverter IN2 is floating.

Referring to the operation of the shift register of the present invention configured as described above is as follows.

First, the operation when LE (Latency) is "1" will be described.

Since LE is "1", the first inverter IN1 outputs a low signal, and the first NAND gate NA1 outputs high to output the first and third NMOS regardless of the QCLKB signal. Transistors NM1 and NM3 are always turned on.

In this case, when a low signal is output from the second NAND gate NA2, a low signal is applied to the first node N1, and a second drain terminal of the first NMOS transistor NM1 turned on. The node N2 receives a low signal.

Accordingly, the second PMOS transistor PM2 is turned on and the high signal is applied to the third node N3. Accordingly, the second inverter IN2 outputs a low signal.

Next, when a high signal is outputted through the second NMOS transistor NA2, a high signal is applied to the first node N1, and accordingly, the second NMOS transistor NM2 is turned on so that the third NMOS transistor N2 is turned on. The node N3 changes from a high signal to a low signal.

As a result, the first PMOS transistor PM1 is turned on, the second node N2 is raised to a voltage level applied from the outside, and is subsequently high to the gate of the second PMOS transistor PM2 by a latch. ) Is transferred to turn off the second PMOS transistor PM2.

Next, the operation when LE is "0" will be described.

When LE is "0", the output of the first NAND gate NA1 and the turn-on / turn-off of the first NMOS transistor NM1 are determined by the signal of QCLKB.

First, when QCLKB is low, the first NAND gate NA1 outputs a high signal. Accordingly, the first and third NMOS transistors NM1 and NM3 are turned on. In this case, the second NMOS is turned on. The level shifting operation is determined according to the gate value of the transistor NM2, and the subsequent operation is performed in the same manner as when the second NAND gate NA2 described above generates a high or low output.

When QCLKB is high, the first NAND gate NA1 outputs a low signal, and the first and third NMOS transistors NM1 and NM3 are turned off.

In this case, when the output of the second inverter IN2 and the third inverter IN3 latched high, the fourth NMOS transistor NM4 is turned on so that the second node N2 is turned low. Low) and the second PMOS transistor PM2 is turned on.

Thereafter, the external voltage level is applied to the third node N3 through the second PMOS transistor PM2 and the low voltage is output through the second inverter IN2.

The level shifter of the present invention as described above has the following effects.

Compared with the conventional method, the number of logic stages is reduced and the clock shifting operation is performed, and the level shifting operation is implemented, thereby increasing the clock access time.

Claims (1)

A first inverter IN1 for inverting the control signal LE; A first NAND gate NA1 that inversely multiplies the signal of the first inverter IN1 by the clock signal QCLKB, and then inverts the result; A second NAND gate NA2 for transferring a data path signal to the second NMOS transistor NM2; A first NMOS transistor NM1 operated by receiving an output signal of the first NAND gate NA1; A second NMOS transistor NM2 which determines a data path according to the signal of the second NAND gate; A third NMOS transistor NM3 connected to a source terminal of the second NMOS transistor NM2 and a ground voltage terminal after receiving the signal of the first NAND gate NA1; The first and second PMOS transistors may be connected to the drain terminals of each other to form a cross couple, and each drain terminal is connected to the drain terminals of the first and second NMOS transistors NM1 and NM2, respectively. PM1, PM2), A fourth NMOS transistor NM4 which receives the signal of the drain terminal of the second PMOS transistor PM2 and is connected between the drain terminal of the first PMOS transistor PM1 and the ground voltage terminal; A second inverter IN2 for inverting a signal at the drain terminal of the second PMOS transistor PM2, And a third inverter (IN3) latched with the second inverter (IN2) and transmitting a signal to a gate of the fourth NMOS transistor.