KR20010063034A - wordline driver of MML - Google Patents

Abstract

PURPOSE: A word line drive circuit of a merged memory logic is provided to improve an operating characteristic of a word line drive circuit by reducing a load of a sub word line driver. CONSTITUTION: A block enable portion(48) receives block selection signals from a low predecoder(43) and generates block enables signals(pxen0-pxen3) to select one from sub word line driver blocks included in a memory cell array(47). A plurality block selection circuits provide selectively low decoding signals generated by block selection signals to sub word line driver blocks according to the block enables signals(pxen0-pxen3) generated from the block enable portion(48).

Description

Wordline driver circuit for composite memory device {wordline driver of MML}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a word line driver circuit of a mixed memory device (MML), and more particularly, to a word line driver circuit of a compound memory device having improved load characteristics by reducing a load connected to a sub word line driver. It's about the furnace.

In general, as the memory devices are highly integrated, the number of word lines increases and the time delay due to the wiring of the word lines also increases. In order to reduce the time delay, a hierarchical word line method is used. In this word line method, one word line is divided into appropriate lengths to be defined as a sub word line, and the sub decoder is used by using a row decoder and a sub word line driver. The word line is activated.

FIG. 1 is a block diagram of a conventional composite memory device having a sub word line driver and having a 16M x 32 type memory composed of two banks.

As shown in FIG. 1, a 16 M × 32 type composite memory device includes a peripheral circuit 11 mounted on a printed circuit board 10, and upper and lower banks are disposed above and below the peripheral circuit 11. The memory of the bank is mounted, and the upper and lower banks each consist of two half banks. Each half bank is composed of four memory blocks of 1M, and holes H1 to H4 and H1 'to H4' are formed between the half banks. Here, each half bank includes a high power supply voltage (vpp), a power supply voltage detection signal (pwrup), a back bias voltage (vbb), a plate voltage (vcp) of a data storage capacitor, and a bit line precharge signal (vblp). ) Is supplied. Then, the peripheral circuit 11 is supplied with an internal voltage (vint).

FIG. 2 illustrates a structure of a data bus line for the upper bank of FIG. 1, and illustrates a structure of a data bus line for data input / output of an 8M × 32 type memory. In this case, the data bus line includes a local data bus and a global data bus (glb0 to glb15), and is provided with a 64-bit column address line (yi0 to yi63).

3 illustrates a half bank structure having the sub word line driver of FIG.

Referring to FIG. 3, low-decoding signal lines px0 to px3 that have an absolute influence on the overall operating time of a memory device are distributed throughout a half bank, that is, a 4M × 16 block, and as a result, 128 sub wordline drivers Are each connected to. Here, the low decoding signal (px0), (px2) lines are connected to the subword line drivers 12 in the same order as the first, third, and fifth from the right among the subword line driver blocks 12, On the other hand, the low decoding signal (px1), (px3) lines are connected to the subword line driver blocks 12 in the same order as the second, fourth, and sixth from the right among the subword line driver blocks 12. .

As a result, as shown in the lower part of FIG. 3, among the subword line driver blocks 12 arranged in the first column on the right side, the first one from the top has a low decoding signal px0 line and a word line discharge signal. The (xdec0) line is connected, and among the subword line driver blocks 12 arranged in the first column on the right side, the third one is a low decoding signal (px2) line and a word line discharge signal (xdec2) line. Is connected. Therefore, in the worst case, the low decoding signal px0 line is connected to 20 subword line driver blocks 12, causing a delay in the time for enabling the word line. In addition, such a problem becomes more serious with a high speed operation or a large size MML.

FIG. 4 is a circuit diagram of a sub word line driver block of FIG. 1, and is an enlarged view of one sub word line driver block shown in FIG. 3 and a memory cell array region formed at left and right sides thereof.

The memory cell array 20 includes 128 sub word line drivers 120 for driving the word lines WL0 to WL127, and the memory cell array 21 drives the word lines WL0 'to WL127'. 128 sub word line drivers 120 'are provided. The word lines WL0 to WL127 and WL0 'to WL127' are driven by the corresponding sub word lines subxb0 to subxb127 under the control of the sub word line drivers 120 and 120 '. That is, the sub word line driver 120 has a low decoding signal px_j and a word line discharge signal xdecb_j, and the sub word line driver 120 'has a row decoding signal px_j and a word line discharge signal ( xdecb_j) is input.

The sub word line driver 120 is composed of PMOS transistors P1 and P2, and NMOS transistors N1 and N2. Here, the row decoding signal px_j is applied to the sources of the PMOS transistors P1 and P2, the gate is connected to the sub word line subxb0, and the drains thereof are connected to each other. The row decoding signal xdecb_j is applied to the gate of the NMOS transistor N1, and the gate of the NMOS transistor N2 is connected to the sub word line subxb0. In addition, ground voltages Vss are applied to the sources of the NMOS transistors N1 and N2, and drains thereof are connected to each other. In addition, the word line WL0 is commonly connected to the drains of the PMOS transistors P1 and P2 and the drains of the NMOS transistors N1 and N2.

The sub word line driver 120 'includes a PMOS transistor P1' and P2 ', and an NMOS transistor N1' and N2 '. Here, the row decoding signal px_i is applied to the sources of the PMOS transistors P1 'and P2', and the gate thereof is connected to the sub word line subxb0, and the drains thereof are connected to each other. The word line discharge signal xdecb_i is applied to the gate of the NMOS transistor N1 ', and the gate of the NMOS transistor N2' is connected to the sub word line subxb0. In addition, ground voltages Vss are applied to the sources of the NMOS transistors N1 'and N2', respectively, and their drains are connected to each other. The word line WL0 'is commonly connected to the drains of the PMOS transistors P1' and P2 'and the drains of the NMOS transistors N1' and N2 '. Here, the sub word lines subxb0 to 127 are enabled by low level signals.

FIG. 5 is a block diagram illustrating a configuration of the composite memory device of FIG. 1. Referring to FIG. 1, a conventional composite memory device includes a clock signal CLK, a clock enable signal CKE, a chip select signal CS #, a low address strobe signal RAS #, and a column address strobe signal. (CAS #), write enable signal (WE #), data masking signal (DQM), and internal bank address signal (ba) are received, row active signal (ROW_act), column active And a command interpreter 30 for generating various control signals such as the signal COL_act and the refresh signal Refr.

In addition, the conventional composite memory device includes an address buffer 31 which temporarily stores and outputs the address signals A0 to A10 and the bank address signal BA, and an internal bank according to the output signal of the address buffer 31. The internal address from the address register 32 is controlled in accordance with the address register 32 generating the address signal ba, the internal column and the low address signal, and the low active signal ROW_act from the command interpreter 30. The address register is controlled in accordance with a row predecoder 33 which decodes an address signal in advance and generates block selection signals bax0 to bax10, and a column active signal COL_act from the command interpreter 30. And a column predecoder 34 which decodes the internal column address signal from (32) in advance.

Self-refresh logic / timer 35 for controlling the refresh operation of the memory cell in accordance with the refresh signal Refr from the command interpreter 30, and from the cell refresh logic / timer 35. An internal low address counter 36 for counting a low address for refresh according to a control signal and applying it to the column predecoder 34, and a memory cell array 37 including a plurality of memory cells for storing data; X decoders 37a, 37b, 38c, 38d that decode the block selection signals bax0 to bax10 from the low predecoder 33 to drive the word lines of the memory cell array 37. It is composed of

The operation of the conventional composite memory device configured as described above will be described with reference to FIGS. 1 to 6.

The command interpreter 30 receives the low address strobe signal RAS # in synchronization with the clock signal CLK and generates a low active signal ROW_act. At this time, the command interpreter 30 receiving the internal bank address signal ba from the address register 32 selects the upper bank or the lower bank of FIG. 1. Subsequently, the low predecoder 33 decodes the internal low addresses corresponding to the address signals A0, A1, A2, A3, A4, A5, A6, A7, and A8 to select a block. The signals bax0 to bax10 are applied to the X decoders 37a, 37b, 38c, and 38d. Here, the block selection signals bax0 and bax1 are used to generate the row decoding signals px0 to px3 of FIGS. 3 and 4, and the 128 block selection signals bax2 to bax8 are illustrated in FIG. 4 by the block selection signals bax2 to bax8. One of the sub word lines subxb0 to subxb127 is selected. The block selection signals bax9 and bax10 are used to select one of the holes H1 to H4 or the holes H1 'to H4' of FIG. 1.

4 and 6, according to the above-described operation, one signal px among the row decoding signals px0 to px3 becomes high level, and one line subxb among the subword lines subxb0 to subxb127 is formed. When selected, the PMOS transistors P1 and P2 connected to the subword line subxb are turned on to enable the corresponding word line WL. That is, a high level signal is generated at the corresponding word line WL, for example, word line WL0, and at this time, the discharge signal xdecb of the word line WL0 becomes low level.

However, in the conventional case, when decoding the low address, as described above, the word lines WL0 to WL127 using only the row decoding signals px0 to px3 generated by the decoding of the address signals A0 and A1. Was driven. However, when the word lines WL0 to WL127 are driven by decoding the address signals A0 and A1 in this manner, the connection is performed by the row decoding signals px0 to px3 as described above with reference to FIGS. 3 and 4. There are so many subword line drivers 120 and 120 'that parasitic capacitance is generated at the source junction of the subword line drivers 120 and 120' and thus the timing is not correct. do. That is, for normal operation, the row decoding signal px should be changed to a high level before the subword line subxb is enabled. However, as shown in FIG. 6, the subword line subxb is actually first. A case occurs that is enabled. As a result, there is a problem that the driving of the word line WL is delayed.

Accordingly, an object of the present invention is to provide a word line driving circuit of a composite memory device which improves an operation characteristic of a word line driving circuit by reducing a load connected to a sub word line driver. There is this.

1 is a schematic diagram showing a configuration of a general composite memory device having a sub word line driver.

2 is a structural diagram of a data bus line for the upper bank of FIG.

3 shows a half bank structure with the sub wordline driver of FIG.

FIG. 4 is a circuit diagram of a sub word line driver provided in FIG. 1. FIG.

FIG. 5 is a block diagram illustrating a configuration of the composite memory device of FIG. 1. FIG.

6 is a timing diagram illustrating an operation of the composite memory device of FIG. 5.

7 is a block diagram showing the configuration of a composite memory device to which an embodiment of the present invention is applied.

8 is a block diagram illustrating a configuration of a composite memory device to which another embodiment of the present invention is applied.

FIG. 9 is a diagram illustrating an embodiment of a block selection circuit driven by an output signal of the block enable unit of FIGS. 7 and 8.

FIG. 10 illustrates another embodiment of a block selection circuit driven by an output signal of the block enable unit of FIGS. 7 and 8.

FIG. 11 is a timing diagram illustrating an operation of the composite memory device of FIGS. 7 and 8.

* Description of the symbols for the main parts of the drawings *

10,10 ': Printed circuit board 11: Peripheral circuit

12: Subword line driver block 13: Sensor amplifier

20, 21, 37, 47: Memory cell array 30, 40: Command interpreter

31,41: address buffer 32, 42: address register

33, 43: column free decoder 44: low free decoder

35, 45: Self-fresh logic / timer 48: Block enable part

50: first block enable part 51: second block enable part

120,120 ': Subword line driver

In order to achieve the above object, the present invention provides a low predecoder for decoding a command interpreter, an address buffer, an address register, an internal low address, and generating a plurality of block selection signals, a memory cell array having a plurality of banks, and a plurality of X decoders. And a sub word line driver for driving a word line, the multi memory block receiving a block selection signal and selecting one of the sub word line driver blocks included in the memory cell array; A block enable unit for generating an enable signal; And a plurality of block selection circuits for selectively supplying a low decoding signal generated by the block selection signal to the subword line driver block according to the block enable signal from the block enable unit. It features.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

7 illustrates a configuration of a composite memory device to which an embodiment of the present invention is applied.

The complex memory device to which the present invention is applied includes the command interpreter 40, the address buffer 41, the address register 42, the low predecoder 43, the column predecoder 44, and the cell fresh logic that are configured in the same manner as in the prior art. / Timer 45, internal low address counter 46, memory cell array 47, and X decoders 37a, 37b, 38c, 38d.

In addition, the composite memory device to which the present invention is applied receives the block selection signals bax9 and bax10 from the low predecoder 43 and the subword line driver blocks included in the memory cell array 47. A block enable unit 48 for generating a block enable signal (pxen0 to pxen3) for selecting one is further provided.

8 illustrates a configuration of a composite memory device to which another embodiment of the present invention is applied. The composite memory device of FIG. 8 is configured in the same manner as in FIG. 7, but includes two block enable parts, that is, a first block enable part 50 and a second block enable part 51.

FIG. 9 illustrates an embodiment of a block selection circuit driven by an output signal of the block enable unit of FIGS. 7 and 8.

The block selection circuit includes a pair of PMOS transistors PM1 and PM2 driven by the block enable signals pxen0 to pxen3, respectively. The low decoding signals px0 to px3 are applied to the sources ND of the PMOS transistors PM1 and PM2 and the drains thereof are connected to the PMOS transistors (not shown) of the subword line driver block subxdrv. do.

The subword line driver block subxdrv includes 128 subword line drivers configured in the same manner as the subword line drivers 120 and 120 'of FIG. 4.

FIG. 10 illustrates another embodiment of a block selection circuit driven by an output signal of the block enable unit of FIGS. 7 and 8.

The block selection circuit according to this embodiment is composed of transmission gates TG1, TG2 and inverters INV1, INV2. The low decoding signals px0 to px3 are supplied to the gates of the PMOS transistors constituting the transmission gates TG1 and TG2, and the inverters are supplied to the gates of the NMOS transistors constituting the transmission gates TG1 and TG2, respectively. The output terminals of (INV1) and (INV2) are connected.

Referring to Figures 7 to 11 the operation of the present invention will be described.

First, the block selection signals bax0 to bax10 are output from the low predecoder 44 according to the above operation. At this time, the block selection signals bax0 and bax1 are applied to the block enable unit 48, and thus block enable signals pxen0 to pxen3 are generated and applied to the selected bank of the memory cell array 47. .

That is, the block enable signals pxen0 to pxen3 are applied to the block selection circuit of the memory cell block as shown in FIGS. 9 and 10, and the low decoding signals px0 to px3 are also supplied. At this time, only one signal pxen among the block enable signals pxen0 to pxen3 is enabled as the low level as shown in FIG. 11.

Therefore, in the block selection circuit of FIG. 9, for example, when only the block enable signal pxen0 is enabled, the PMOS transistors PM1 and PM2 connected to the block enable signal pxen0 line are turned on. The low decoding signal px0 is applied to the subword line driver subxdrv through the source junction ND. As a result, since the low decoding signal px0 is supplied only to the source junction ND corresponding to the subword line driver subxdrv of the first block, the junction capacitance is reduced as compared with the related art. That is, conventionally, in the case of the low decoding signal px0, 128 × 20 junction capacitances are generated, but according to the present invention, 128 × 5 junction capacitances are generated.

Therefore, as shown in FIG. 11, since only the high level low decoding signal px is supplied only to the block selected by the low level block enable signal pxen, the sub word after the low decoding signal px is activated. The line signal subxb is enabled at a low level. Therefore, the high level signal is supplied to the word line WL at normal timing.

Similarly, even when a desired block is selected using the block selection circuit of FIG. 10 described above, a normal timing diagram as shown in FIG. 11 can be obtained.

Meanwhile, as shown in FIG. 8, when two block enable parts are provided, that is, the first block enable part 50 and the second block enable part 51 are selected as compared to the embodiment of FIG. 7. Since the number of lines of the low decoding signals px0 to px3 connected to the subword line driver block subxdrv can be reduced in half, the junction capacitance can be further reduced.

As described above, the present invention includes a block enable portion for generating a signal for selecting a subword line driver block, and a block select circuit driven by an output signal of the block enable portion, thereby providing a subword. The number of low decoding signal lines connected to the line block can be reduced. Therefore, the present invention can reduce the parasitic capacitance generated at the source junction of the subword line driver, and consequently can prevent the driving delay of the word line.

Claims (5)

A low predecoder for decoding a command interpreter, an address buffer, an address register, an internal low address to generate a plurality of block selection signals, a memory cell array consisting of a plurality of banks, a plurality of X decoders, and a subword line for driving a word line. In a composite memory device comprising a driver, A block enable unit configured to receive the block selection signal and generate a plurality of block enable signals for selecting one of the subword line driver blocks included in the memory cell array; And And a plurality of block selection circuits for selectively supplying a low decoding signal generated by the block selection signal to the subword line driver block according to the block enable signal from the block enable unit. Word line drive circuit. The method of claim 1, wherein the block selection circuit is And a pair of PMOS transistors each driven by the block enable signal and supplying the low decoding signal to a corresponding subword line driver block. The method of claim 1, wherein the block selection circuit is And a pair of transmission gates driven by the block enable signal and its inverted signal. The word line driver circuit of claim 1, wherein the block enable signal is a low active signal. The word line driver circuit of claim 1, wherein the block selection circuit is provided for each of the subword line blocks.